2 * Driver for ATMEL DataFlash support
3 * Author : Hamid Ikdoumi (Atmel)
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/hardware.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/io.h>
26 #include <asm/arch/at91_pio.h>
27 #include <asm/arch/at91_spi.h>
29 #ifdef CONFIG_HAS_DATAFLASH
30 #include <dataflash.h>
32 #define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
33 #define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 0: NPCS0%1101 */
34 #define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
36 void AT91F_SpiInit(void)
39 writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR);
41 /* Configure SPI in Master Mode with No CS selected !!! */
42 writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS,
43 AT91_BASE_SPI + AT91_SPI_MR);
46 writel(AT91_SPI_NCPHA |
47 (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
48 (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
49 ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
50 AT91_BASE_SPI + AT91_SPI_CSR(0));
52 #ifdef CFG_DATAFLASH_LOGIC_ADDR_CS1
54 writel(AT91_SPI_NCPHA |
55 (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
56 (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
57 ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
58 AT91_BASE_SPI + AT91_SPI_CSR(1));
61 #ifdef CFG_DATAFLASH_LOGIC_ADDR_CS3
63 writel(AT91_SPI_NCPHA |
64 (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
65 (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
66 ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
67 AT91_BASE_SPI + AT91_SPI_CSR(3));
71 writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
73 while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_SPIENS));
76 * Add tempo to get SPI in a safe state.
77 * Should not be needed for new silicon (Rev B)
80 readl(AT91_BASE_SPI + AT91_SPI_SR);
81 readl(AT91_BASE_SPI + AT91_SPI_RDR);
85 void AT91F_SpiEnable(int cs)
89 case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
90 mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
92 writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
93 AT91_BASE_SPI + AT91_SPI_MR);
95 case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */
96 mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
98 writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
99 AT91_BASE_SPI + AT91_SPI_MR);
102 mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
104 writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
105 AT91_BASE_SPI + AT91_SPI_MR);
110 writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
113 unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
115 unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
117 unsigned int timeout;
122 writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
125 /* Initialize the Transmit and Receive Pointer */
126 writel((unsigned int)pDesc->rx_cmd_pt, AT91_BASE_SPI + AT91_SPI_RPR);
127 writel((unsigned int)pDesc->tx_cmd_pt, AT91_BASE_SPI + AT91_SPI_TPR);
129 /* Intialize the Transmit and Receive Counters */
130 writel(pDesc->rx_cmd_size, AT91_BASE_SPI + AT91_SPI_RCR);
131 writel(pDesc->tx_cmd_size, AT91_BASE_SPI + AT91_SPI_TCR);
133 if (pDesc->tx_data_size != 0) {
134 /* Initialize the Next Transmit and Next Receive Pointer */
135 writel((unsigned int)pDesc->rx_data_pt, AT91_BASE_SPI + AT91_SPI_RNPR);
136 writel((unsigned int)pDesc->tx_data_pt, AT91_BASE_SPI + AT91_SPI_TNPR);
138 /* Intialize the Next Transmit and Next Receive Counters */
139 writel(pDesc->rx_data_size, AT91_BASE_SPI + AT91_SPI_RNCR);
140 writel(pDesc->tx_data_size, AT91_BASE_SPI + AT91_SPI_TNCR);
143 /* arm simple, non interrupt dependent timer */
144 reset_timer_masked();
147 writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR);
148 while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
149 ((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT));
150 writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
153 if (timeout >= CFG_SPI_WRITE_TOUT) {
154 printf("Error Timeout\n\r");
155 return DATAFLASH_ERROR;