2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 #ifndef __ARCH_ARM_MACH_MX50_CRM_REGS_H__
20 #define __ARCH_ARM_MACH_MX50_CRM_REGS_H__
22 #define MXC_CCM_BASE CCM_BASE_ADDR
23 #define MXC_DPLL1_BASE PLL1_BASE_ADDR
24 #define MXC_DPLL2_BASE PLL2_BASE_ADDR
25 #define MXC_DPLL3_BASE PLL3_BASE_ADDR
27 /* PLL Register Offsets */
28 #define MXC_PLL_DP_CTL 0x00
29 #define MXC_PLL_DP_CONFIG 0x04
30 #define MXC_PLL_DP_OP 0x08
31 #define MXC_PLL_DP_MFD 0x0C
32 #define MXC_PLL_DP_MFN 0x10
33 #define MXC_PLL_DP_MFNMINUS 0x14
34 #define MXC_PLL_DP_MFNPLUS 0x18
35 #define MXC_PLL_DP_HFS_OP 0x1C
36 #define MXC_PLL_DP_HFS_MFD 0x20
37 #define MXC_PLL_DP_HFS_MFN 0x24
38 #define MXC_PLL_DP_MFN_TOGC 0x28
39 #define MXC_PLL_DP_DESTAT 0x2c
41 /* PLL Register Bit definitions */
42 #define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
43 #define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
44 #define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
45 #define MXC_PLL_DP_CTL_ADE 0x800
46 #define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
47 #define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
48 #define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
49 #define MXC_PLL_DP_CTL_HFSM 0x80
50 #define MXC_PLL_DP_CTL_PRE 0x40
51 #define MXC_PLL_DP_CTL_UPEN 0x20
52 #define MXC_PLL_DP_CTL_RST 0x10
53 #define MXC_PLL_DP_CTL_RCP 0x8
54 #define MXC_PLL_DP_CTL_PLM 0x4
55 #define MXC_PLL_DP_CTL_BRM0 0x2
56 #define MXC_PLL_DP_CTL_LRF 0x1
58 #define MXC_PLL_DP_CONFIG_BIST 0x8
59 #define MXC_PLL_DP_CONFIG_SJC_CE 0x4
60 #define MXC_PLL_DP_CONFIG_AREN 0x2
61 #define MXC_PLL_DP_CONFIG_LDREQ 0x1
63 #define MXC_PLL_DP_OP_MFI_OFFSET 4
64 #define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
65 #define MXC_PLL_DP_OP_PDF_OFFSET 0
66 #define MXC_PLL_DP_OP_PDF_MASK 0xF
68 #define MXC_PLL_DP_MFD_OFFSET 0
69 #define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
71 #define MXC_PLL_DP_MFN_OFFSET 0x0
72 #define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
74 #define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
75 #define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
76 #define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
77 #define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
79 #define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
80 #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
82 /* Register addresses of CCM*/
83 #define MXC_CCM_CCR (MXC_CCM_BASE + 0x00)
84 #define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04) /* Reserved */
85 #define MXC_CCM_CSR (MXC_CCM_BASE + 0x08)
86 #define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C)
87 #define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10)
88 #define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14)
89 #define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18)
90 #define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C)
91 #define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20) /* Reserved */
92 #define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24)
93 #define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28)
94 #define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C)
95 #define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30) /* Reserved */
96 #define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34) /* Reserved */
97 #define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38)
98 #define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C) /* Reserved */
99 #define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40) /* Reserved */
100 #define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44) /* Reserved */
101 #define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48)
102 #define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C)
103 #define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50)
104 #define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54)
105 #define MXC_CCM_CISR (MXC_CCM_BASE + 0x58)
106 #define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C)
107 #define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60)
108 #define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64) /* Reserved */
109 #define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68)
110 #define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C)
111 #define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70)
112 #define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74)
113 #define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78)
114 #define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C)
115 #define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80)
116 #define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x84)
117 #define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x88)
118 #define MXC_CCM_CSR2 (MXC_CCM_BASE + 0x8C)
119 #define MXC_CCM_CLKSEQ_BYPASS (MXC_CCM_BASE + 0x90)
120 #define MXC_CCM_CLK_SYS (MXC_CCM_BASE + 0x94)
121 #define MXC_CCM_CLK_DDR (MXC_CCM_BASE + 0x98)
123 /* Define the bits in register CCR */
124 #define MXC_CCM_CCR_COSC_EN (1 << 12)
125 #define MXC_CCM_CCR_CAMP1_EN (1 << 9)
126 #define MXC_CCM_CCR_OSCNT_OFFSET (0)
127 #define MXC_CCM_CCR_OSCNT_MASK (0xFF)
129 /* Define the bits in register CSR */
130 #define MXC_CCM_CSR_COSR_READY (1 << 5)
131 #define MXC_CCM_CSR_LVS_VALUE (1 << 4)
132 #define MXC_CCM_CSR_CAMP1_READY (1 << 2)
133 #define MXC_CCM_CSR_TEMP_MON_ALARM (1 << 1)
134 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
136 /* Define the bits in register CCSR */
137 #define MXC_CCM_CCSR_PLL3_PFD_EN (0x1 << 13)
138 #define MXC_CCM_CCSR_PLL2_PFD_EN (0x1 << 12)
139 #define MXC_CCM_CCSR_PLL1_PFD_EN (0x1 << 11)
140 #define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 10)
141 #define MXC_CCM_CCSR_LP_APM_SEL_OFFSET (1)
142 #define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
143 #define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
144 #define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
145 #define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
146 #define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
147 #define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
148 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
149 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
150 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
152 /* Define the bits in register CACRR */
153 #define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
154 #define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
156 /* Define the bits in register CBCDR */
157 #define MXC_CCM_CBCDR_WEIM_CLK_SEL (0x1 << 27)
158 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL_OFFSET (25)
159 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x3 << 25)
160 #define MXC_CCM_CBCDR_WEIM_PODF_OFFSET (22)
161 #define MXC_CCM_CBCDR_WEIM_PODF_MASK (7 << 22)
162 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
163 #define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
164 #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
165 #define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
166 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
167 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
168 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
169 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
170 #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
171 #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
172 #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
173 #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
174 #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
175 #define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
177 /* Define the bits in register CBCMR */
178 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (16)
179 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
180 #define MXC_CCM_CBCMR_DBG_APB_CLK_SEL_OFFSET (2)
181 #define MXC_CCM_CBCMR_DBG_APB_CLK_SEL_MASK (0x3 << 2)
182 #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
183 #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
184 #define MXC_CCM_CBCMR_LP_APM_SEL_OFFSET (0x1)
186 /* Define the bits in register CSCMR1 */
187 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
188 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
189 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
190 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
191 #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
192 #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
193 #define MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET (21)
194 #define MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 21)
195 #define MXC_CCM_CSCMR1_ESDHC2_CLK_SEL (0x1 << 20)
196 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 19)
197 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET (16)
198 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK (0x7 << 16)
199 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
200 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
201 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
202 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
203 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
204 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
205 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
206 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
207 #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
208 #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
210 /* Define the bits in register CSCDR1 */
211 #define MXC_CCM_CSCDR1_ESDHC3_CLK_PRED_OFFSET (22)
212 #define MXC_CCM_CSCDR1_ESDHC3_CLK_PRED_MASK (0x7 << 22)
213 #define MXC_CCM_CSCDR1_ESDHC3_CLK_PODF_OFFSET (19)
214 #define MXC_CCM_CSCDR1_ESDHC3_CLK_PODF_MASK (0x7 << 19)
215 #define MXC_CCM_CSCDR1_ESDHC1_CLK_PRED_OFFSET (16)
216 #define MXC_CCM_CSCDR1_ESDHC1_CLK_PRED_MASK (0x7 << 16)
217 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
218 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
219 #define MXC_CCM_CSCDR1_ESDHC1_CLK_PODF_OFFSET (11)
220 #define MXC_CCM_CSCDR1_ESDHC1_CLK_PODF_MASK (0x7 << 11)
221 #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
222 #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
223 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
224 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
226 /* Define the bits in register CS1CDR and CS2CDR */
227 #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
228 #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
229 #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
230 #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
231 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
232 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
233 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
234 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
236 #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
237 #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
238 #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
239 #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
240 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
241 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
242 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
243 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
245 /* Define the bits in register CSCDR2 */
246 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
247 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
248 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
249 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
251 /* Define the bits in register CDHIPR */
252 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
253 #define MXC_CCM_CDHIPR_WEIM_CLK_SEL_BUSY (1 << 6)
254 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
255 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
256 #define MXC_CCM_CDHIPR_WEIM_PODF_BUSY (1 << 2)
257 #define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
258 #define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
260 /* Define the bits in register CDCR */
262 #define MXC_CCM_CDCR_SW_PERIPH_CLK_DIV_REQ_STATUS (0x1 << 7)
263 #define MXC_CCM_CDCR_SW_PERIPH_CLK_DIV_REQ (0x1 << 6)
264 #define MXC_CCM_CDCR_SW_DVFS_EN (0x1 << 5)
265 #define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
266 #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
267 #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
269 /* Define the bits in register CLPCR */
270 #define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25)
271 #define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 24)
272 #define MXC_CCM_CLPCR_BYPASS_RNGB_LPM_HS (0x1 << 23)
273 #define MXC_CCM_CLPCR_BYPASS_WEIM_LPM_HS (0x1 << 19)
274 #define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
275 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
276 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
277 #define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
278 #define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
279 #define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
280 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
281 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (0x1 << 2)
282 #define MXC_CCM_CLPCR_LPM_OFFSET (0)
283 #define MXC_CCM_CLPCR_LPM_MASK (0x3)
285 /* Define the bits in register CISR */
286 #define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 26)
287 #define MXC_CCM_CISR_TEMP_MON_ALARM (0x1 << 25)
288 #define MXC_CCM_CISR_WEIM_CLK_SEL_LOADED (0x1 << 23)
289 #define MXC_CCM_CISR_PER_CLK_SEL_LOADED (0x1 << 22)
290 #define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
291 #define MXC_CCM_CISR_WEIM_PODF_LOADED (0x1 << 19)
292 #define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
293 #define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
294 #define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
295 #define MXC_CCM_CISR_COSC_READY (0x1 << 6)
296 #define MXC_CCM_CISR_CAMP1_READY (0x1 << 4)
297 #define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
298 #define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
299 #define MXC_CCM_CISR_LRF_PLL1 (0x1)
301 /* Define the bits in register CIMR */
302 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 26)
303 #define MXC_CCM_CIMR_MASK_TEMP_MON_ALARM (0x1 << 25)
304 #define MXC_CCM_CIMR_MASK_WEIM_CLK_SEL_LOADED (0x1 << 23)
305 #define MXC_CCM_CIMR_MASK_PER_CLK_SEL_LOADED (0x1 << 22)
306 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (0x1 << 20)
307 #define MXC_CCM_CIMR_MASK_WEIM_PODF_LOADED (0x1 << 19)
308 #define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
309 #define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
310 #define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
311 #define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 6)
312 #define MXC_CCM_CIMR_MASK_CAMP1_READY (0x1 << 4)
313 #define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
314 #define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
315 #define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
317 /* Define the bits in register CCOSR */
318 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
319 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
320 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
321 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
322 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
323 #define MXC_CCM_CCOSR_CKO1_SLOW_SEL (0x1 << 8)
324 #define MXC_CCM_CCOSR_CKO1_EN (0x1 << 7)
325 #define MXC_CCM_CCOSR_CKO1_DIV_OFFSET (4)
326 #define MXC_CCM_CCOSR_CKO1_DIV_MASK (0x7 << 4)
327 #define MXC_CCM_CCOSR_CKO1_SEL_OFFSET (0)
328 #define MXC_CCM_CCOSR_CKO1_SEL_MASK (0xF)
330 /* Define the bits in registers CCGRx */
331 #define MXC_CCM_CCGR_CG_MASK 0x3
333 #define MXC_CCM_CCGR0_CG15_OFFSET 30
334 #define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
335 #define MXC_CCM_CCGR0_CG14_OFFSET 28
336 #define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
337 #define MXC_CCM_CCGR0_CG13_OFFSET 26
338 #define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
339 #define MXC_CCM_CCGR0_CG12_OFFSET 24
340 #define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
341 #define MXC_CCM_CCGR0_CG11_OFFSET 22
342 #define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
343 #define MXC_CCM_CCGR0_CG10_OFFSET 20
344 #define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
345 #define MXC_CCM_CCGR0_CG9_OFFSET 18
346 #define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
347 #define MXC_CCM_CCGR0_CG8_OFFSET 16
348 #define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
349 #define MXC_CCM_CCGR0_CG7_OFFSET 14
350 #define MXC_CCM_CCGR0_CG6_OFFSET 12
351 #define MXC_CCM_CCGR0_CG5_OFFSET 10
352 #define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
353 #define MXC_CCM_CCGR0_CG4_OFFSET 8
354 #define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
355 #define MXC_CCM_CCGR0_CG3_OFFSET 6
356 #define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
357 #define MXC_CCM_CCGR0_CG2_OFFSET 4
358 #define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
359 #define MXC_CCM_CCGR0_CG1_OFFSET 2
360 #define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
361 #define MXC_CCM_CCGR0_CG0_OFFSET 0
362 #define MXC_CCM_CCGR0_CG0_MASK 0x3
364 #define MXC_CCM_CCGR1_CG15_OFFSET 30
365 #define MXC_CCM_CCGR1_CG14_OFFSET 28
366 #define MXC_CCM_CCGR1_CG13_OFFSET 26
367 #define MXC_CCM_CCGR1_CG12_OFFSET 24
368 #define MXC_CCM_CCGR1_CG11_OFFSET 22
369 #define MXC_CCM_CCGR1_CG10_OFFSET 20
370 #define MXC_CCM_CCGR1_CG9_OFFSET 18
371 #define MXC_CCM_CCGR1_CG8_OFFSET 16
372 #define MXC_CCM_CCGR1_CG7_OFFSET 14
373 #define MXC_CCM_CCGR1_CG6_OFFSET 12
374 #define MXC_CCM_CCGR1_CG5_OFFSET 10
375 #define MXC_CCM_CCGR1_CG4_OFFSET 8
376 #define MXC_CCM_CCGR1_CG3_OFFSET 6
377 #define MXC_CCM_CCGR1_CG2_OFFSET 4
378 #define MXC_CCM_CCGR1_CG1_OFFSET 2
379 #define MXC_CCM_CCGR1_CG0_OFFSET 0
381 #define MXC_CCM_CCGR2_CG15_OFFSET 30
382 #define MXC_CCM_CCGR2_CG14_OFFSET 28
383 #define MXC_CCM_CCGR2_CG13_OFFSET 26
384 #define MXC_CCM_CCGR2_CG12_OFFSET 24
385 #define MXC_CCM_CCGR2_CG11_OFFSET 22
386 #define MXC_CCM_CCGR2_CG10_OFFSET 20
387 #define MXC_CCM_CCGR2_CG9_OFFSET 18
388 #define MXC_CCM_CCGR2_CG8_OFFSET 16
389 #define MXC_CCM_CCGR2_CG7_OFFSET 14
390 #define MXC_CCM_CCGR2_CG6_OFFSET 12
391 #define MXC_CCM_CCGR2_CG5_OFFSET 10
392 #define MXC_CCM_CCGR2_CG4_OFFSET 8
393 #define MXC_CCM_CCGR2_CG3_OFFSET 6
394 #define MXC_CCM_CCGR2_CG2_OFFSET 4
395 #define MXC_CCM_CCGR2_CG1_OFFSET 2
396 #define MXC_CCM_CCGR2_CG0_OFFSET 0
398 #define MXC_CCM_CCGR3_CG15_OFFSET 30
399 #define MXC_CCM_CCGR3_CG14_OFFSET 28
400 #define MXC_CCM_CCGR3_CG13_OFFSET 26
401 #define MXC_CCM_CCGR3_CG12_OFFSET 24
402 #define MXC_CCM_CCGR3_CG11_OFFSET 22
403 #define MXC_CCM_CCGR3_CG10_OFFSET 20
404 #define MXC_CCM_CCGR3_CG9_OFFSET 18
405 #define MXC_CCM_CCGR3_CG8_OFFSET 16
406 #define MXC_CCM_CCGR3_CG7_OFFSET 14
407 #define MXC_CCM_CCGR3_CG6_OFFSET 12
408 #define MXC_CCM_CCGR3_CG5_OFFSET 10
409 #define MXC_CCM_CCGR3_CG4_OFFSET 8
410 #define MXC_CCM_CCGR3_CG3_OFFSET 6
411 #define MXC_CCM_CCGR3_CG2_OFFSET 4
412 #define MXC_CCM_CCGR3_CG1_OFFSET 2
413 #define MXC_CCM_CCGR3_CG0_OFFSET 0
415 #define MXC_CCM_CCGR4_CG15_OFFSET 30
416 #define MXC_CCM_CCGR4_CG14_OFFSET 28
417 #define MXC_CCM_CCGR4_CG13_OFFSET 26
418 #define MXC_CCM_CCGR4_CG12_OFFSET 24
419 #define MXC_CCM_CCGR4_CG11_OFFSET 22
420 #define MXC_CCM_CCGR4_CG10_OFFSET 20
421 #define MXC_CCM_CCGR4_CG9_OFFSET 18
422 #define MXC_CCM_CCGR4_CG8_OFFSET 16
423 #define MXC_CCM_CCGR4_CG7_OFFSET 14
424 #define MXC_CCM_CCGR4_CG6_OFFSET 12
425 #define MXC_CCM_CCGR4_CG5_OFFSET 10
426 #define MXC_CCM_CCGR4_CG4_OFFSET 8
427 #define MXC_CCM_CCGR4_CG3_OFFSET 6
428 #define MXC_CCM_CCGR4_CG2_OFFSET 4
429 #define MXC_CCM_CCGR4_CG1_OFFSET 2
430 #define MXC_CCM_CCGR4_CG0_OFFSET 0
432 #define MXC_CCM_CCGR5_CG15_OFFSET 30
433 #define MXC_CCM_CCGR5_CG14_OFFSET 28
434 #define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
435 #define MXC_CCM_CCGR5_CG13_OFFSET 26
436 #define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
437 #define MXC_CCM_CCGR5_CG12_OFFSET 24
438 #define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
439 #define MXC_CCM_CCGR5_CG11_OFFSET 22
440 #define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
441 #define MXC_CCM_CCGR5_CG10_OFFSET 20
442 #define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
443 #define MXC_CCM_CCGR5_CG9_OFFSET 18
444 #define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
445 #define MXC_CCM_CCGR5_CG8_OFFSET 16
446 #define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
447 #define MXC_CCM_CCGR5_CG7_OFFSET 14
448 #define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
449 #define MXC_CCM_CCGR5_CG6_1_OFFSET 12
450 #define MXC_CCM_CCGR5_CG6_2_OFFSET 13
451 #define MXC_CCM_CCGR5_CG6_OFFSET 12
452 #define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12)
453 #define MXC_CCM_CCGR5_CG5_OFFSET 10
454 #define MXC_CCM_CCGR5_CG4_OFFSET 8
455 #define MXC_CCM_CCGR5_CG3_OFFSET 6
456 #define MXC_CCM_CCGR5_CG2_OFFSET 4
457 #define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
458 #define MXC_CCM_CCGR5_CG1_OFFSET 2
459 #define MXC_CCM_CCGR5_CG0_OFFSET 0
461 #define MXC_CCM_CCGR6_CG15_OFFSET 30
462 #define MXC_CCM_CCGR6_CG14_OFFSET 28
463 #define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28)
464 #define MXC_CCM_CCGR6_CG13_OFFSET 26
465 #define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26)
466 #define MXC_CCM_CCGR6_CG12_OFFSET 24
467 #define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24)
468 #define MXC_CCM_CCGR6_CG11_OFFSET 22
469 #define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22)
470 #define MXC_CCM_CCGR6_CG10_OFFSET 20
471 #define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20)
472 #define MXC_CCM_CCGR6_CG9_OFFSET 18
473 #define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18)
474 #define MXC_CCM_CCGR6_CG8_OFFSET 16
475 #define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16)
476 #define MXC_CCM_CCGR6_CG7_OFFSET 14
477 #define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14)
478 #define MXC_CCM_CCGR6_CG6_OFFSET 12
479 #define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12)
480 #define MXC_CCM_CCGR6_CG5_OFFSET 10
481 #define MXC_CCM_CCGR6_CG5_MASK (0x3 << 10)
482 #define MXC_CCM_CCGR6_CG4_OFFSET 8
483 #define MXC_CCM_CCGR6_CG4_MASK (0x3 << 8)
484 #define MXC_CCM_CCGR6_CG3_OFFSET 6
485 #define MXC_CCM_CCGR6_CG2_OFFSET 4
486 #define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4)
487 #define MXC_CCM_CCGR6_CG1_OFFSET 2
488 #define MXC_CCM_CCGR6_CG0_OFFSET 0
490 #define MXC_CCM_CCGR7_CG15_OFFSET 30
491 #define MXC_CCM_CCGR7_CG14_OFFSET 28
492 #define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28)
493 #define MXC_CCM_CCGR7_CG13_OFFSET 26
494 #define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26)
495 #define MXC_CCM_CCGR7_CG12_OFFSET 24
496 #define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24)
497 #define MXC_CCM_CCGR7_CG11_OFFSET 22
498 #define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22)
499 #define MXC_CCM_CCGR7_CG10_OFFSET 20
500 #define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20)
501 #define MXC_CCM_CCGR7_CG9_OFFSET 18
502 #define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18)
503 #define MXC_CCM_CCGR7_CG8_OFFSET 16
504 #define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16)
505 #define MXC_CCM_CCGR7_CG7_OFFSET 14
506 #define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14)
507 #define MXC_CCM_CCGR7_CG6_OFFSET 12
508 #define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12)
509 #define MXC_CCM_CCGR7_CG5_OFFSET 10
510 #define MXC_CCM_CCGR7_CG4_OFFSET 8
511 #define MXC_CCM_CCGR7_CG3_OFFSET 6
512 #define MXC_CCM_CCGR7_CG2_OFFSET 4
513 #define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4)
514 #define MXC_CCM_CCGR7_CG1_OFFSET 2
515 #define MXC_CCM_CCGR7_CG0_OFFSET 0
517 /* Define the bits in registers CLKSEQ_BYPASS */
518 #define MXC_CCM_CLKSEQ_BYPASS_ELCDIF_PIX_OFFSET 14
519 #define MXC_CCM_CLKSEQ_BYPASS_ELCDIF_PIX_MASK (0x3 << 14)
520 #define MXC_CCM_CLKSEQ_BYPASS_EPDC_PIX_OFFSET 12
521 #define MXC_CCM_CLKSEQ_BYPASS_EPDC_PIX_MASK (0x3 << 12)
522 #define MXC_CCM_CLKSEQ_BYPASS_MSHCX_OFFSET 10
523 #define MXC_CCM_CLKSEQ_BYPASS_MSHCX_MASK (0x3 << 10)
524 #define MXC_CCM_CLKSEQ_BYPASS_BCH_OFFSET 8
525 #define MXC_CCM_CLKSEQ_BYPASS_BCH_MASK (0x3 << 8)
526 #define MXC_CCM_CLKSEQ_BYPASS_GPMI_OFFSET 6
527 #define MXC_CCM_CLKSEQ_BYPASS_GPMI_MASK (0x3 << 6)
528 #define MXC_CCM_CLKSEQ_BYPASS_EPDC_OFFSET 4
529 #define MXC_CCM_CLKSEQ_BYPASS_EPDC_MASK (0x3 << 4)
530 #define MXC_CCM_CLKSEQ_BYPASS_DISPLY_AXI_OFFSET 2
531 #define MXC_CCM_CLKSEQ_BYPASS_DISPLY_AXI_MASK (0x3 << 2)
532 #define MXC_CCM_CLKSEQ_BYPASS_SYS_CLK_1 (0x1 << 1)
533 #define MXC_CCM_CLKSEQ_BYPASS_SYS_CLK_0 (0x1 << 0)
535 /* Define the bits in registers CLK_SYS */
536 #define MXC_CCM_CLK_SYS_XTAL_CLKGATE_OFFSET 30
537 #define MXC_CCM_CLK_SYS_XTAL_CLKGATE_MASK (0x3 << 30)
538 #define MXC_CCM_CLK_SYS_PLL_CLKGATE_OFFSET 28
539 #define MXC_CCM_CLK_SYS_PLL_CLKGATE_MASK (0x3 << 28)
540 #define MXC_CCM_CLK_SYS_DIV_XTAL_OFFSET 6
541 #define MXC_CCM_CLK_SYS_DIV_XTAL_MASK (0xf << 6)
542 #define MXC_CCM_CLK_SYS_DIV_PLL_OFFSET 0
543 #define MXC_CCM_CLK_SYS_DIV_PLL_MASK (0x3f << 0)
545 /* Define the bits in registers CLK_DDR */
546 #define MXC_CCM_CLK_DDR_DDR_CLKGATE_OFFSET (30)
547 #define MXC_CCM_CLK_DDR_DDR_CLKGATE_MASK (0x3 << 30)
548 #define MXC_CCM_CLK_DDR_DDR_PFD_SEL (1 << 6)
549 #define MXC_CCM_CLK_DDR_DDR_DIV_PLL_OFFSET (0)
550 #define MXC_CCM_CLK_DDR_DDR_DIV_PLL_MASK (0x3F)
553 #define MXC_GPC_BASE (IO_ADDRESS(GPC_BASE_ADDR))
554 #define MXC_DPTC_LP_BASE (MXC_GPC_BASE + 0x80)
555 #define MXC_DPTC_GP_BASE (MXC_GPC_BASE + 0x100)
556 #define MXC_DVFS_CORE_BASE (MXC_GPC_BASE + 0x180)
557 #define MXC_DVFS_PER_BASE (MXC_GPC_BASE + 0x1C4)
558 #define MXC_PGC_IPU_BASE (MXC_GPC_BASE + 0x220)
559 #define MXC_PGC_VPU_BASE (MXC_GPC_BASE + 0x240)
560 #define MXC_PGC_GPU_BASE (MXC_GPC_BASE + 0x260)
561 #define MXC_SRPG_NEON_BASE (MXC_GPC_BASE + 0x280)
562 #define MXC_SRPG_ARM_BASE (MXC_GPC_BASE + 0x2A0)
563 #define MXC_SRPG_EMPGC0_BASE (MXC_GPC_BASE + 0x2C0)
564 #define MXC_SRPG_EMPGC1_BASE (MXC_GPC_BASE + 0x2D0)
565 #define MXC_SRPG_MEGAMIX_BASE (MXC_GPC_BASE + 0x2E0)
566 #define MXC_SRPG_EMI_BASE (MXC_GPC_BASE + 0x300)
569 #define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
570 #define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
571 #define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
572 #define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
573 #define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
574 #define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
575 #define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
576 #define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
577 #define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
578 #define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
579 #define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
580 #define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
581 #define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
582 #define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
583 #define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
584 #define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
585 #define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
588 #define MXC_DVFSPER_LTR0 (MXC_DVFS_PER_BASE)
589 #define MXC_DVFSPER_LTR1 (MXC_DVFS_PER_BASE + 0x04)
590 #define MXC_DVFSPER_LTR2 (MXC_DVFS_PER_BASE + 0x08)
591 #define MXC_DVFSPER_LTR3 (MXC_DVFS_PER_BASE + 0x0C)
592 #define MXC_DVFSPER_LTBR0 (MXC_DVFS_PER_BASE + 0x10)
593 #define MXC_DVFSPER_LTBR1 (MXC_DVFS_PER_BASE + 0x14)
594 #define MXC_DVFSPER_PMCR0 (MXC_DVFS_PER_BASE + 0x18)
595 #define MXC_DVFSPER_PMCR1 (MXC_DVFS_PER_BASE + 0x1C)
598 #define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0)
599 #define MXC_GPC_PGR (MXC_GPC_BASE + 0x4)
600 #define MXC_GPC_VCR (MXC_GPC_BASE + 0x8)
601 #define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC)
602 #define MXC_GPC_NEON (MXC_GPC_BASE + 0x10)
605 #define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
606 #define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
607 #define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
608 #define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
609 #define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
610 #define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
612 #define MXC_PGCR_PCR 1
613 #define MXC_SRPGCR_PCR 1
614 #define MXC_EMPGCR_PCR 1
615 #define MXC_PGSR_PSR 1
618 #define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
619 #define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
622 #define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
623 #define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
624 #define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
626 #define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
627 #define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
628 #define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
630 #define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
631 #define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
632 #define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
634 #define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
635 #define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
636 #define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
638 #define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
639 #define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
640 #define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
642 #define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
643 #define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
644 #define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
646 #endif /* __ARCH_ARM_MACH_MX50_CRM_REGS_H__ */