3 * Texas Instruments, <www.ti.com>
6 * Manikandan Pillai <mani.pillai@ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/mem.h>
31 #include <asm/arch/sys_proto.h>
35 * Only One NAND allowed on board at a time.
36 * The GPMC CS Base for the same
38 unsigned int boot_flash_base;
39 unsigned int boot_flash_off;
40 unsigned int boot_flash_sec;
41 unsigned int boot_flash_type;
42 volatile unsigned int boot_flash_env_addr;
44 struct gpmc *gpmc_cfg;
46 #if defined(CONFIG_CMD_NAND)
47 static u32 gpmc_m_nand[GPMC_MAX_REG] = {
53 M_NAND_GPMC_CONFIG6, 0
56 #if defined(CONFIG_ENV_IS_IN_NAND)
64 #if defined(CONFIG_CMD_ONENAND)
65 static u32 gpmc_onenand[GPMC_MAX_REG] = {
71 ONENAND_GPMC_CONFIG6, 0
74 #if defined(CONFIG_ENV_IS_IN_ONENAND)
82 static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
84 /**************************************************************************
85 * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
86 * command line mem=xyz use all memory with out discontinuous support
87 * compiled in. Could do it at the ATAG, but there really is two banks...
88 * Called as part of 2nd phase DDR init.
89 **************************************************************************/
90 void make_cs1_contiguous(void)
92 u32 size, a_add_low, a_add_high;
94 size = get_sdr_cs_size(CS0);
95 size >>= 25; /* divide by 32 MiB to find size to offset CS1 */
96 a_add_high = (size & 3) << 8; /* set up low field */
97 a_add_low = (size & 0x3C) >> 2; /* set up high field */
98 writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
102 /********************************************************
103 * mem_ok() - test used to see if timings are correct
104 * for a part. Helps in guessing which part
105 * we are currently using.
106 *******************************************************/
109 u32 val1, val2, addr;
110 u32 pattern = 0x12345678;
112 addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
114 writel(0x0, addr + 0x400); /* clear pos A */
115 writel(pattern, addr); /* pattern to pos B */
116 writel(0x0, addr + 4); /* remove pattern off the bus */
117 val1 = readl(addr + 0x400); /* get pos A value */
118 val2 = readl(addr); /* get val2 */
120 if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
126 /********************************************************
127 * sdrc_init() - init the sdrc chip selects CS0 and CS1
128 * - early init routines, called from flash or
130 *******************************************************/
133 /* only init up first bank here */
134 do_sdrc_init(CS0, EARLY_INIT);
137 /*************************************************************************
138 * do_sdrc_init(): initialize the SDRAM for use.
139 * -code sets up SDRAM basic SDRC timings for CS0
140 * -optimal settings can be placed here, or redone after i2c
141 * inspection of board info
143 * - code called once in C-Stack only context for CS0 and a possible 2nd
144 * time depending on memory configuration from stack+global context
145 **************************************************************************/
147 void do_sdrc_init(u32 cs, u32 early)
149 struct sdrc_actim *sdrc_actim_base;
152 sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
154 sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
157 /* reset sdrc controller */
158 writel(SOFTRESET, &sdrc_base->sysconfig);
159 wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
161 writel(0, &sdrc_base->sysconfig);
163 /* setup sdrc to ball mux */
164 writel(SDP_SDRC_SHARING, &sdrc_base->sharing);
166 /* Disable Power Down of CKE cuz of 1 CKE on combo part */
167 writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
169 writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
173 writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
174 RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
175 DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
176 writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
177 writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
178 writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
180 writel(CMD_NOP, &sdrc_base ->cs[cs].manual);
181 writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
182 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
183 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
186 * CAS latency 3, Write Burst = Read Burst, Serial Mode,
189 writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
192 writel(0, &sdrc_base->cs[cs].mcfg);
195 void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
198 writel(0, &cs->config7);
200 /* Delay for settling */
201 writel(gpmc_config[0], &cs->config1);
202 writel(gpmc_config[1], &cs->config2);
203 writel(gpmc_config[2], &cs->config3);
204 writel(gpmc_config[3], &cs->config4);
205 writel(gpmc_config[4], &cs->config5);
206 writel(gpmc_config[5], &cs->config6);
207 /* Enable the config */
208 writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
209 (1 << 6)), &cs->config7);
213 /*****************************************************
214 * gpmc_init(): init gpmc bus
215 * Init GPMC for x16, MuxMode (SDRAM in x32).
216 * This code can only be executed from SRAM or SDRAM.
217 *****************************************************/
220 /* putting a blanket check on GPMC based on ZeBu for now */
221 u32 *gpmc_config = NULL;
222 gpmc_cfg = (struct gpmc *)GPMC_BASE;
225 u32 f_off = CONFIG_SYS_MONITOR_LEN;
229 /* global settings */
230 writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
231 writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
233 config = readl(&gpmc_cfg->config);
235 writel(config, &gpmc_cfg->config);
238 * Disable the GPMC0 config set by ROM code
239 * It conflicts with our MPDB (both at 0x08000000)
241 writel(0, &gpmc_cfg->cs[0].config7);
244 #if defined(CONFIG_CMD_NAND) /* CS 0 */
245 gpmc_config = gpmc_m_nand;
247 base = PISMO1_NAND_BASE;
248 size = PISMO1_NAND_SIZE;
249 enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
250 #if defined(CONFIG_ENV_IS_IN_NAND)
251 f_off = SMNAND_ENV_OFFSET;
252 f_sec = (128 << 10); /* 128 KiB */
254 boot_flash_base = base;
255 boot_flash_off = f_off;
256 boot_flash_sec = f_sec;
257 boot_flash_env_addr = f_off;
261 #if defined(CONFIG_CMD_ONENAND)
262 gpmc_config = gpmc_onenand;
263 base = PISMO1_ONEN_BASE;
264 size = PISMO1_ONEN_SIZE;
265 enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
266 #if defined(CONFIG_ENV_IS_IN_ONENAND)
267 f_off = ONENAND_ENV_OFFSET;
268 f_sec = (128 << 10); /* 128 KiB */
270 boot_flash_base = base;
271 boot_flash_off = f_off;
272 boot_flash_sec = f_sec;
273 boot_flash_env_addr = f_off;