2 * U-boot - start.S Startup file of u-boot for BF537
4 * Copyright (c) 2005-2007 Analog Devices Inc.
6 * This file is based on head.S
7 * Copyright (c) 2003 Metrowerks/Motorola
8 * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
9 * Kenneth Albanowski <kjahds@kjahds.com>,
10 * The Silver Hammer Group, Ltd.
11 * (c) 1995, Dionne & Associates
12 * (c) 1995, DKG Display Tech.
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
34 * Note: A change in this file subsequently requires a change in
35 * board/$(board_name)/config.mk for a valid u-boot.bin
40 #include <linux/config.h>
42 #include <asm/blackfin.h>
44 #include <asm/mach-common/bits/core.h>
45 #include <asm/mach-common/bits/dma.h>
46 #include <asm/mach-common/bits/pll.h>
55 .global _icache_enable;
56 .global _dcache_enable;
57 #if defined(CONFIG_BF537)&&defined(CONFIG_POST)
58 .global _memory_post_test;
62 #if (BFIN_BOOT_MODE == BF537_UART_BOOT)
63 #if (CONFIG_CCLK_DIV == 1)
64 #define CONFIG_CCLK_ACT_DIV CCLK_DIV1
66 #if (CONFIG_CCLK_DIV == 2)
67 #define CONFIG_CCLK_ACT_DIV CCLK_DIV2
69 #if (CONFIG_CCLK_DIV == 4)
70 #define CONFIG_CCLK_ACT_DIV CCLK_DIV4
72 #if (CONFIG_CCLK_DIV == 8)
73 #define CONFIG_CCLK_ACT_DIV CCLK_DIV8
75 #ifndef CONFIG_CCLK_ACT_DIV
76 #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
89 /* As per HW reference manual DAG registers,
90 * DATA and Address resgister shall be zero'd
91 * in initialization, after a reset state
93 r1 = 0; /* Data registers zero'd */
101 p0 = 0; /* Address registers zero'd */
108 i0 = 0; /* DAG Registers zero'd */
125 /* Set loop counters to zero, to make sure that
126 * hw loops are disabled.
134 /* Check soft reset status */
136 p0.l = SWRST & 0xFFFF;
140 if !cc jump no_soft_reset;
142 /* Clear Soft reset */
150 /* Clear EVT registers */
152 p0.l = (EVT0 & 0xFFFF);
156 LSETUP(4,4) lc0 = p1;
159 #if (BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT)
167 #if (BFIN_BOOT_MODE == BF537_UART_BOOT)
176 * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
178 p0.h = hi(PLL_LOCKCNT);
179 p0.l = lo(PLL_LOCKCNT);
185 * Put SDRAM in self-refresh, incase anything is running
187 P2.H = hi(EBIU_SDGCTL);
188 P2.L = lo(EBIU_SDGCTL);
195 * Set PLL_CTL with the value that we calculate in R0
196 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
197 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
198 * - [7] = output delay (add 200ps of delay to mem signals)
199 * - [6] = input delay (add 200ps of input delay to mem signals)
200 * - [5] = PDWN : 1=All Clocks off
201 * - [3] = STOPCK : 1=Core Clock off
202 * - [1] = PLL_OFF : 1=Disable Power to PLL
203 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
204 * all other bits set to zero
207 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
208 r0 = r0 << 9; /* Shift it over, */
209 r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
211 r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
212 r1 = r1 << 8; /* Shift it over */
213 r0 = r1 | r0; /* add them all together */
216 p0.l = lo(PLL_CTL); /* Load the address */
217 cli r2; /* Disable interrupts */
219 w[p0] = r0.l; /* Set the value */
220 idle; /* Wait for the PLL to stablize */
221 sti r2; /* Enable interrupts */
228 if ! CC jump check_again;
230 /* Configure SCLK & CCLK Dividers */
231 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
239 * We now are running at speed, time to set the Async mem bank wait states
240 * This will speed up execution, since we are normally running from FLASH.
241 * we need to read MAC address from FLASH
243 p2.h = (EBIU_AMBCTL1 >> 16);
244 p2.l = (EBIU_AMBCTL1 & 0xFFFF);
245 r0.h = (AMBCTL1VAL >> 16);
246 r0.l = (AMBCTL1VAL & 0xFFFF);
250 p2.h = (EBIU_AMBCTL0 >> 16);
251 p2.l = (EBIU_AMBCTL0 & 0xFFFF);
252 r0.h = (AMBCTL0VAL >> 16);
253 r0.l = (AMBCTL0VAL & 0xFFFF);
257 p2.h = (EBIU_AMGCTL >> 16);
258 p2.l = (EBIU_AMGCTL & 0xffff);
263 #if ((BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT) && (BFIN_BOOT_MODE != BF537_UART_BOOT))
264 sp.l = (0xffb01000 & 0xFFFF);
265 sp.h = (0xffb01000 >> 16);
271 #if defined(CONFIG_BF537)&&defined(CONFIG_POST)
272 /* DMA POST code to Hi of L1 SRAM */
274 /* P1 Points to the beginning of SYSTEM MMR Space */
275 P1.H = hi(SYSMMR_BASE);
276 P1.L = lo(SYSMMR_BASE);
282 R2 = R1 - R0; /* Count */
285 R1.H = (CFG_MONITOR_BASE >> 16);
286 R1.L = (CFG_MONITOR_BASE & 0xFFFF);
288 R1.H = (CFG_FLASH_BASE >> 16);
289 R1.L = (CFG_FLASH_BASE & 0xFFFF);
290 R0 = R0 + R1; /* Source Address */
291 R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */
292 R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */
293 R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
294 /* Destination DMAConfig Value (8-bit words) */
295 R4.L = (DI_EN | WNR | DMAEN);
298 W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
299 W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
301 [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
302 W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
303 /* Set Source DMAConfig = DMA Enable,
304 Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
305 W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
307 [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
308 W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
309 /* Set Destination DMAConfig = DMA Enable,
310 Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
311 W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
314 p0.h = hi(MDMA_D0_IRQ_STATUS);
315 p0.l = lo(MDMA_D0_IRQ_STATUS);
318 if ! CC jump POST_DMA_DONE
321 W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
323 /* DMA POST data to Hi of L1 SRAM */
328 R2 = R1 - R0; /* Count */
331 R1.H = (CFG_MONITOR_BASE >> 16);
332 R1.L = (CFG_MONITOR_BASE & 0xFFFF);
334 R1.H = (CFG_FLASH_BASE >> 16);
335 R1.L = (CFG_FLASH_BASE & 0xFFFF);
336 R0 = R0 + R1; /* Source Address */
337 R1.H = hi(DATA_BANKB_SRAM); /* Destination Address (high) */
338 R1.L = lo(DATA_BANKB_SRAM); /* Destination Address (low) */
339 R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
340 R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
343 W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
344 W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
346 [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
347 W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
348 /* Set Source DMAConfig = DMA Enable,
349 Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
350 W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
352 [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
353 W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
354 /* Set Destination DMAConfig = DMA Enable,
355 Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
356 W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
359 p0.h = hi(MDMA_D0_IRQ_STATUS);
360 p0.l = lo(MDMA_D0_IRQ_STATUS);
363 if ! CC jump POST_DATA_DMA_DONE
366 W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
368 p0.l = _memory_post_test;
369 p0.h = _memory_post_test;
372 r7 = r0; /* save return value */
377 /* relocate into to RAM */
389 p2.l = (CFG_MONITOR_BASE & 0xffff);
390 p2.h = (CFG_MONITOR_BASE >> 16);
393 p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
394 p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
403 r0.h = (CONFIG_STACKBASE >> 16);
404 r0.l = (CONFIG_STACKBASE & 0xFFFF);
409 * This next section keeps the processor in supervisor mode
410 * during kernel boot. Switches to user mode at end of boot.
411 * See page 3-9 of Hardware Reference manual for documentation.
414 /* To keep ourselves in the supervisor mode */
415 p0.l = (EVT15 & 0xFFFF);
416 p0.h = (EVT15 >> 16);
422 p0.l = (IMASK & 0xFFFF);
423 p0.h = (IMASK >> 16);
424 r0.l = LO(EVT_IVG15);
425 r0.h = HI(EVT_IVG15);
441 /* Initialise General-Purpose I/O Modules on BF537
442 * Rev 0.0 Anomaly 05000212 - PORTx_FER,
443 * PORT_MUX Registers Do Not accept "writes" correctly
445 p0.h = hi(PORTF_FER);
446 p0.l = lo(PORTF_FER);
447 R0.L = W[P0]; /* Read */
453 W[P0] = R0.L; /* Write */
458 W[P0] = R0.L; /* Enable peripheral function of PORTF for UART0 and UART1 */
464 p0.h = hi(PORTH_FER);
465 p0.l = lo(PORTH_FER);
466 R0.L = W[P0]; /* Read */
472 W[P0] = R0.L; /* Write */
477 W[P0] = R0.L; /* Enable peripheral function of PORTH for MAC */
485 /* DMA reset code to Hi of L1 SRAM */
487 P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
488 P1.L = lo(SYSMMR_BASE);
490 R0.H = reset_start; /* Source Address (high) */
491 R0.L = reset_start; /* Source Address (low) */
494 R2 = R1 - R0; /* Count */
495 R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */
496 R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */
497 R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
498 R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
502 W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
503 W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
505 [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
506 W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
507 /* Set Source DMAConfig = DMA Enable,
508 Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
509 W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
511 [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
512 W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
513 /* Set Destination DMAConfig = DMA Enable,
514 Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
515 W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
518 p0.h = hi(MDMA_D0_IRQ_STATUS);
519 p0.l = lo(MDMA_D0_IRQ_STATUS);
522 if ! CC jump WAIT_DMA_DONE
525 W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
527 /* Initialize BSS Section with 0 s */
537 lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
539 if CC jump _clear_bss_skip;
546 #if defined(CONFIG_BF537)&&defined(CONFIG_POST)
558 p0.h = WDOG_CNT >> 16;
559 p0.l = WDOG_CNT & 0xffff;
562 p0.h = WDOG_CTL >> 16;
563 p0.l = WDOG_CTL & 0xffff;