3 * (C) Copyright 2004 eslab.whut.edu.cn
4 * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
33 #include <asm/arch/ixp425.h>
34 #include <asm/arch/ixp425pci.h>
36 static void non_prefetch_read (unsigned int addr, unsigned int cmd,
38 static void non_prefetch_write (unsigned int addr, unsigned int cmd,
40 static void configure_pins (void);
41 static void sys_pci_gpio_clock_config (void);
42 static void pci_bus_scan (void);
43 static int pci_device_exists (unsigned int deviceNo);
44 static void sys_pci_bar_info_get (unsigned int devnum, unsigned int bus,
45 unsigned int dev, unsigned int func);
46 static void sys_pci_device_bars_write (void);
47 static void calc_bars (PciBar * Bars[], unsigned int nBars,
48 unsigned int startAddr);
50 #define PCI_MEMORY_BUS 0x00000000
51 #define PCI_MEMORY_PHY 0x48000000
52 #define PCI_MEMORY_SIZE 0x04000000
54 #define PCI_MEM_BUS 0x40000000
55 #define PCI_MEM_PHY 0x00000000
56 #define PCI_MEM_SIZE 0x04000000
58 #define PCI_IO_BUS 0x40000000
59 #define PCI_IO_PHY 0x50000000
60 #define PCI_IO_SIZE 0x10000000
62 struct pci_controller hose;
64 unsigned int nDevices;
67 PciBar *memBars[IXP425_PCI_MAX_BAR];
68 PciBar *ioBars[IXP425_PCI_MAX_BAR];
69 PciDevice devices[IXP425_PCI_MAX_FUNC_ON_BUS];
71 extern void out_8 (volatile unsigned *addr, char val)
75 extern void out_le16 (volatile unsigned *addr, unsigned short val)
77 *addr = cpu_to_le16 (val);
79 extern void out_le32 (volatile unsigned *addr, unsigned int val)
81 *addr = cpu_to_le32 (val);
84 extern unsigned char in_8 (volatile unsigned *addr)
91 extern unsigned short in_le16 (volatile unsigned *addr)
96 val = le16_to_cpu (val);
99 extern unsigned in_le32 (volatile unsigned *addr)
104 val = le32_to_cpu (val);
108 int pci_read_config_dword (pci_dev_t dev, int where, unsigned int *val)
113 /*address bits 31:28 specify the device 10:8 specify the function */
114 /*Set the address to be read */
115 addr = BIT ((31 - dev)) | (where & ~3);
116 non_prefetch_read (addr, NP_CMD_CONFIGREAD, &retval);
123 int pci_read_config_word (pci_dev_t dev, int where, unsigned short *val)
128 unsigned int byteEnables;
131 /*byte enables are 4 bits active low, the position of each
132 bit maps to the byte that it enables */
134 (~(BIT (n) | BIT ((n + 1)))) &
135 IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
136 byteEnables = byteEnables << PCI_NP_CBE_BESL;
137 /*address bits 31:28 specify the device 10:8 specify the function */
138 /*Set the address to be read */
139 addr = BIT ((31 - dev)) | (where & ~3);
140 non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
142 /*Pick out the word we are interested in */
143 *val = (retval >> (8 * n));
148 int pci_read_config_byte (pci_dev_t dev, int where, unsigned char *val)
152 unsigned int byteEnables;
156 /*byte enables are 4 bits, active low, the position of each
157 bit maps to the byte that it enables */
158 byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
159 byteEnables = byteEnables << PCI_NP_CBE_BESL;
161 /*address bits 31:28 specify the device, 10:8 specify the function */
162 /*Set the address to be read */
163 addr = BIT ((31 - dev)) | (where & ~3);
164 non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
165 /*Pick out the byte we are interested in */
166 *val = (retval >> (8 * n));
171 int pci_write_config_byte (pci_dev_t dev, int where, unsigned char val)
174 unsigned int byteEnables;
179 /*byte enables are 4 bits active low, the position of each
180 bit maps to the byte that it enables */
181 byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
182 byteEnables = byteEnables << PCI_NP_CBE_BESL;
183 ldata = val << (8 * n);
184 /*address bits 31:28 specify the device 10:8 specify the function */
185 /*Set the address to be written */
186 addr = BIT ((31 - dev)) | (where & ~3);
187 non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
192 int pci_write_config_word (pci_dev_t dev, int where, unsigned short val)
195 unsigned int byteEnables;
200 /*byte enables are 4 bits active low, the position of each
201 bit maps to the byte that it enables */
203 (~(BIT (n) | BIT ((n + 1)))) &
204 IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
205 byteEnables = byteEnables << PCI_NP_CBE_BESL;
206 ldata = val << (8 * n);
207 /*address bits 31:28 specify the device 10:8 specify the function */
208 /*Set the address to be written */
209 addr = BIT (31 - dev) | (where & ~3);
210 non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
215 int pci_write_config_dword (pci_dev_t dev, int where, unsigned int val)
219 /*address bits 31:28 specify the device 10:8 specify the function */
220 /*Set the address to be written */
221 addr = BIT (31 - dev) | (where & ~3);
222 non_prefetch_write (addr, NP_CMD_CONFIGWRITE, val);
227 void non_prefetch_read (unsigned int addr,
228 unsigned int cmd, unsigned int *data)
230 REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr);
232 /*set up and execute the read */
233 REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd);
235 /*The result of the read is now in np_rdata */
236 REG_READ (PCI_CSR_BASE, PCI_NP_RDATA_OFFSET, *data);
241 void non_prefetch_write (unsigned int addr,
242 unsigned int cmd, unsigned int data)
245 REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr);
246 /*set up the write */
247 REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd);
248 /*Execute the write by writing to NP_WDATA */
249 REG_WRITE (PCI_CSR_BASE, PCI_NP_WDATA_OFFSET, data);
255 * PCI controller config registers are accessed through these functions
256 * i.e. these allow us to set up our own BARs etc.
258 void crp_read (unsigned int offset, unsigned int *data)
260 REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, offset);
261 REG_READ (PCI_CSR_BASE, PCI_CRP_RDATA_OFFSET, *data);
264 void crp_write (unsigned int offset, unsigned int data)
266 /*The CRP address register bit 16 indicates that we want to do a write */
267 REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET,
268 PCI_CRP_WRITE | offset);
269 REG_WRITE (PCI_CSR_BASE, PCI_CRP_WDATA_OFFSET, data);
272 /*struct pci_controller *hose*/
273 void pci_ixp_init (struct pci_controller *hose)
277 hose->first_busno = 0;
278 hose->last_busno = 0x00;
280 /* System memory space */
281 pci_set_region (hose->regions + 0,
283 PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_MEMORY);
285 /* PCI memory space */
286 pci_set_region (hose->regions + 1,
288 PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM);
290 pci_set_region (hose->regions + 2,
291 PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO);
293 hose->region_count = 3;
295 pci_register_hose (hose);
298 ==========================================================
300 ==========================================================
302 REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
304 REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
308 READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval);
309 WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval & (~(1 << 13)));
311 sys_pci_gpio_clock_config ();
312 REG_WRITE (PCI_CSR_BASE, PCI_INTEN_OFFSET, 0);
314 READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval);
315 WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval | (1 << 13));
317 crp_write (PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_0_DEFAULT);
318 crp_write (PCI_CFG_BASE_ADDRESS_1, IXP425_PCI_BAR_1_DEFAULT);
319 crp_write (PCI_CFG_BASE_ADDRESS_2, IXP425_PCI_BAR_2_DEFAULT);
320 crp_write (PCI_CFG_BASE_ADDRESS_3, IXP425_PCI_BAR_3_DEFAULT);
321 crp_write (PCI_CFG_BASE_ADDRESS_4, IXP425_PCI_BAR_4_DEFAULT);
322 crp_write (PCI_CFG_BASE_ADDRESS_5, IXP425_PCI_BAR_5_DEFAULT);
323 /*Setup PCI-AHB and AHB-PCI address mappings */
324 REG_WRITE (PCI_CSR_BASE, PCI_AHBMEMBASE_OFFSET,
325 IXP425_PCI_AHBMEMBASE_DEFAULT);
327 REG_WRITE (PCI_CSR_BASE, PCI_AHBIOBASE_OFFSET,
328 IXP425_PCI_AHBIOBASE_DEFAULT);
330 REG_WRITE (PCI_CSR_BASE, PCI_PCIMEMBASE_OFFSET,
331 IXP425_PCI_PCIMEMBASE_DEFAULT);
333 crp_write (PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM);
335 REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
336 regval |= PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS;
337 REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
338 crp_write (PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME);
341 pci_write_config_word (0, PCI_CFG_COMMAND, INITIAL_PCI_CMD);
342 REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
343 | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE);
344 #ifdef CONFIG_PCI_SCAN_SHOW
345 printf ("Device bus dev func deviceID vendorID \n");
350 void configure_pins (void)
354 /* Disable clock on GPIO PIN 14 */
355 READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
356 WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval & (~(1 << 8)));
357 READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
359 READ_GPIO_REG (IXP425_GPIO_GPOER, regval);
360 WRITE_GPIO_REG (IXP425_GPIO_GPOER,
361 (((~(3 << 13)) & regval) | (0xf << 8)));
362 READ_GPIO_REG (IXP425_GPIO_GPOER, regval);
364 READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval);
365 WRITE_GPIO_REG (IXP425_GPIO_GPIT2R,
367 ((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1)));
368 READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval);
370 READ_GPIO_REG (IXP425_GPIO_GPISR, regval);
371 WRITE_GPIO_REG (IXP425_GPIO_GPISR, (regval | (0xf << 8)));
372 READ_GPIO_REG (IXP425_GPIO_GPISR, regval);
375 void sys_pci_gpio_clock_config (void)
379 READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
381 WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
382 READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
384 WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
387 void pci_bus_scan (void)
389 unsigned int bus = 0, dev, func = 0;
390 unsigned short data16;
392 unsigned char intPin;
394 /* Assign first device to ourselves */
396 devices[0].device = 0;
399 crp_read (PCI_CFG_VENDOR_ID, &data32);
401 devices[0].vendor_id = data32 & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK;
402 devices[0].device_id = data32 >> 16;
403 devices[0].error = FALSE;
404 devices[0].bar[NO_BAR].size = 0; /*dummy - required */
411 for (dev = 0; dev < IXP425_PCI_MAX_DEV; dev++) {
413 /*Check whether a device is present */
414 if (pci_device_exists (dev) != TRUE) {
416 /*Clear error bits in ISR, write 1 to clear */
417 REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
418 | PCI_ISR_PFE | PCI_ISR_PPE |
423 /*A device is present, add an entry to the array */
424 devices[nDevices].bus = bus;
425 devices[nDevices].device = dev;
426 devices[nDevices].func = func;
428 pci_read_config_word (dev, PCI_CFG_VENDOR_ID, &data16);
430 devices[nDevices].vendor_id = data16;
432 pci_read_config_word (dev, PCI_CFG_DEVICE_ID, &data16);
433 devices[nDevices].device_id = data16;
435 /*The device is functioning correctly, set error to FALSE */
436 devices[nDevices].error = FALSE;
438 /*Figure out what BARs are on this device */
439 sys_pci_bar_info_get (nDevices, bus, dev, func);
440 /*Figure out what INTX# line the card uses */
441 pci_read_config_byte (dev, PCI_CFG_DEV_INT_PIN, &intPin);
443 /*assign the appropriate irq line */
444 if (intPin > PCI_IRQ_LINES) {
445 devices[nDevices].error = TRUE;
446 } else if (intPin != 0) {
447 /*This device uses an interrupt line */
448 /*devices[nDevices].irq = ixp425PciIntTranslate[dev][intPin-1]; */
449 devices[nDevices].irq = intPin;
451 #ifdef CONFIG_PCI_SCAN_SHOW
452 printf ("%06d %03d %03d %04d %08d %08x\n", nDevices,
453 devices[nDevices].vendor_id);
459 calc_bars (memBars, nMBars, IXP425_PCI_BAR_MEM_BASE);
460 sys_pci_device_bars_write ();
462 REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
463 | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE);
466 void sys_pci_bar_info_get (unsigned int devnum,
468 unsigned int dev, unsigned int func)
474 pci_write_config_dword (devnum,
475 PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_QUERY);
476 pci_read_config_dword (devnum, PCI_CFG_BASE_ADDRESS_0, &data32);
478 devices[devnum].bar[0].address = (data32 & 1);
484 devices[devnum].bar[0].size = size;
486 if (nIOBars < IXP425_PCI_MAX_BAR) {
487 ioBars[nIOBars++] = &devices[devnum].bar[0];
491 tmp = data32 & ~IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
493 devices[devnum].bar[0].size = size;
495 if (nMBars < IXP425_PCI_MAX_BAR) {
496 memBars[nMBars++] = &devices[devnum].bar[0];
498 devices[devnum].error = TRUE;
503 devices[devnum].bar[1].size = 0;
506 void sortBars (PciBar * Bars[], unsigned int nBars)
515 /* Sort biggest to smallest */
516 for (i = 0; i < nBars - 1; i++) {
517 for (j = i + 1; j < nBars; j++) {
518 if (Bars[j]->size > Bars[i]->size) {
528 void calc_bars (PciBar * Bars[], unsigned int nBars, unsigned int startAddr)
536 for (i = 0; i < nBars; i++) {
537 Bars[i]->address |= startAddr;
538 startAddr += Bars[i]->size;
542 void sys_pci_device_bars_write (void)
547 for (i = 1; i < nDevices; i++) {
548 if (devices[i].error) {
552 pci_write_config_dword (devices[i].device,
553 PCI_CFG_BASE_ADDRESS_0,
554 devices[i].bar[0].address);
557 device) | (0 << PCI_NP_AD_FUNCSL) |
558 (PCI_CFG_BASE_ADDRESS_0) & ~3;
559 pci_write_config_dword (devices[i].device,
560 PCI_CFG_DEV_INT_LINE, devices[i].irq);
562 pci_write_config_word (devices[i].device,
563 PCI_CFG_COMMAND, INITIAL_PCI_CMD);
569 int pci_device_exists (unsigned int deviceNo)
571 unsigned int vendorId;
574 pci_read_config_dword (deviceNo, PCI_CFG_VENDOR_ID, &vendorId);
576 /* There are two ways to find out an empty device.
577 * 1. check Master Abort bit after the access.
578 * 2. check whether the vendor id read back is 0x0.
580 REG_READ (PCI_CSR_BASE, PCI_ISR_OFFSET, regval);
581 if ((vendorId != 0x0) && ((regval & PCI_ISR_PFE) == 0)) {
584 /*no device present, make sure that the master abort bit is reset */
586 REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PFE);
590 pci_dev_t pci_find_devices (struct pci_device_id * ids, int devNo)
593 unsigned int devdidvid;
595 unsigned int vendorId, deviceId;
597 vendorId = ids->vendor;
598 deviceId = ids->device;
599 didvid = ((deviceId << 16) & IXP425_PCI_TOP_WORD_OF_LONG_MASK) |
600 (vendorId & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK);
602 for (i = devNo + 1; i < nDevices; i++) {
604 pci_read_config_dword (devices[i].device, PCI_CFG_VENDOR_ID,
607 if (devdidvid == didvid) {
608 return devices[i].device;
613 #endif /* CONFIG_PCI */