2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001, 2002, 2007 Wolfgang Denk <wd@denx.de>
5 * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Based on the MPC83xx code.
29 * U-Boot - Startup Code for MPC512x based Embedded Boards
36 #define CONFIG_521X 1 /* needed for Linux kernel header files*/
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
44 #ifndef CONFIG_IDENT_STRING
45 #define CONFIG_IDENT_STRING "MPC512X"
49 * Floating Point enable, Machine Check and Recoverable Interr.
53 #define MSR_KERNEL (MSR_FP|MSR_RI)
55 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
58 /* Macros for manipulating CSx_START/STOP */
59 #define START_REG(start) ((start) >> 16)
60 #define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
63 * Set up GOT: Global Offset Table
65 * Use r14 to access the GOT
68 GOT_ENTRY(_GOT2_TABLE_)
69 GOT_ENTRY(_FIXUP_TABLE_)
72 GOT_ENTRY(_start_of_vectors)
73 GOT_ENTRY(_end_of_vectors)
74 GOT_ENTRY(transfer_to_handler)
78 GOT_ENTRY(__bss_start)
82 * Magic number and version string
84 .long 0x27051956 /* U-Boot Magic Number */
88 .ascii " (", __DATE__, " - ", __TIME__, ")"
89 .ascii " ", CONFIG_IDENT_STRING, "\0"
98 /* Start from here after reset/power on */
100 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
103 .globl _start_of_vectors
107 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
109 /* Data Storage exception. */
110 STD_EXCEPTION(0x300, DataStorage, UnknownException)
112 /* Instruction Storage exception. */
113 STD_EXCEPTION(0x400, InstStorage, UnknownException)
115 /* External Interrupt exception. */
116 STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
118 /* Alignment exception. */
121 EXCEPTION_PROLOG(SRR0, SRR1)
126 addi r3,r1,STACK_FRAME_OVERHEAD
128 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
129 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
130 lwz r6,GOT(transfer_to_handler)
134 .long AlignmentException - _start + EXC_OFF_SYS_RESET
135 .long int_return - _start + EXC_OFF_SYS_RESET
137 /* Program check exception */
140 EXCEPTION_PROLOG(SRR0, SRR1)
141 addi r3,r1,STACK_FRAME_OVERHEAD
143 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
144 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
145 lwz r6,GOT(transfer_to_handler)
149 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
150 .long int_return - _start + EXC_OFF_SYS_RESET
152 /* Floating Point Unit unavailable exception */
153 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
156 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
158 /* Critical interrupt */
159 STD_EXCEPTION(0xa00, Critical, UnknownException)
162 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
164 /* Trace interrupt */
165 STD_EXCEPTION(0xd00, Trace, UnknownException)
167 /* Performance Monitor interrupt */
168 STD_EXCEPTION(0xf00, PerfMon, UnknownException)
170 /* Intruction Translation Miss */
171 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
173 /* Data Load Translation Miss */
174 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
176 /* Data Store Translation Miss */
177 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
179 /* Instruction Address Breakpoint */
180 STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
182 /* System Management interrupt */
183 STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
185 .globl _end_of_vectors
190 /* Save msr contents */
193 /* Set IMMR area to our preferred location */
194 lis r4, CONFIG_DEFAULT_IMMR@h
196 ori r3, r3, CFG_IMMR@l
198 mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */
200 /* Initialise the machine */
204 * Set up Local Access Windows:
206 * 1) Boot/CS0 (boot FLASH)
207 * 2) On-chip SRAM (initial stack purposes)
210 /* Boot CS/CS0 window range */
212 ori r3, r3, CFG_IMMR@l
214 lis r4, START_REG(CFG_FLASH_BASE)
215 ori r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE)
219 * The SRAM window has a fixed size (256K), so only the start address
222 lis r4, START_REG(CFG_SRAM_BASE) & 0xff00
226 * According to MPC5121e RM, configuring local access windows should
227 * be followed by a dummy read of the config register that was
228 * modified last and an isync
234 * Set configuration of the Boot/CS0, the SRAM window does not have a
235 * config register so no params can be set for it
237 lis r3, (CFG_IMMR + LPC_OFFSET)@h
238 ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l
240 lis r4, CFG_CS0_CFG@h
241 ori r4, r4, CFG_CS0_CFG@l
242 stw r4, CS0_CONFIG(r3)
244 /* Master enable all CS's */
246 ori r4, r4, CS_CTRL_ME@l
249 lis r4, (CFG_MONITOR_BASE)@h
250 ori r4, r4, (CFG_MONITOR_BASE)@l
251 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
256 lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
257 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
259 li r0, 0 /* Make room for stack frame header and */
260 stwu r0, -4(r1) /* clear final stack frame so that */
261 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
263 /* let the C-code set up the rest */
265 /* Be careful to keep code relocatable & stack humble */
266 /*------------------------------------------------------*/
268 GET_GOT /* initialize GOT access */
272 /* run low-level CPU init code (in Flash) */
277 /* run 1st part of board init code (in Flash) */
280 /* NOTREACHED - board_init_f() does not return */
283 * This code finishes saving the registers to the exception frame
284 * and jumps to the appropriate handler for the exception.
285 * Register r21 is pointer into trap frame, r1 has new stack pointer.
287 .globl transfer_to_handler
298 andi. r24,r23,0x3f00 /* get vector offset */
302 lwz r24,0(r23) /* virtual address of handler */
303 lwz r23,4(r23) /* where to go when done */
308 rfi /* jump to handler, enable MMU */
311 mfmsr r28 /* Disable interrupts */
315 SYNC /* Some chip revs need this... */
330 lwz r2,_NIP(r1) /* Restore environment */
341 * This code initialises the machine, it expects original MSR contents to be in r5.
344 /* Initialize machine status; enable machine check interrupt */
345 /*-----------------------------------------------------------*/
347 li r3, MSR_KERNEL /* Set ME and RI flags */
348 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */
350 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */
354 mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */
358 #if defined(CONFIG_WATCHDOG)
359 /* Initialise the watchdog and reset it */
360 /*--------------------------------------*/
361 lis r4, CFG_WATCHDOG_VALUE
362 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
372 /* Disable the watchdog */
373 /*----------------------*/
376 * Check to see if it's enabled for disabling: once disabled by s/w
377 * it's not possible to re-enable it
384 #endif /* CONFIG_WATCHDOG */
386 /* Initialize the Hardware Implementation-dependent Registers */
387 /* HID0 also contains cache control */
388 /*------------------------------------------------------*/
389 lis r3, CFG_HID0_INIT@h
390 ori r3, r3, CFG_HID0_INIT@l
394 lis r3, CFG_HID0_FINAL@h
395 ori r3, r3, CFG_HID0_FINAL@l
400 ori r3, r3, CFG_HID2@l
409 * Note: requires that all cache bits in
410 * HID0 are in the low half word.
417 ori r4, r4, HID0_ILOCK
419 ori r4, r3, HID0_ICFI
421 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
423 mtspr HID0, r3 /* clears invalidate */
426 .globl icache_disable
430 ori r4, r4, HID0_ICE|HID0_ILOCK
432 ori r4, r3, HID0_ICFI
434 mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
436 mtspr HID0, r3 /* clears invalidate */
442 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
448 li r5, HID0_DCFI|HID0_DLOCK
450 mtspr HID0, r3 /* no invalidate, unlock */
452 ori r5, r3, HID0_DCFI
453 mtspr HID0, r5 /* enable + invalidate */
454 mtspr HID0, r3 /* enable */
458 .globl dcache_disable
462 ori r4, r4, HID0_DCE|HID0_DLOCK
466 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
468 mtspr HID0, r3 /* clears invalidate */
474 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
482 /*-------------------------------------------------------------------*/
485 * void relocate_code (addr_sp, gd, addr_moni)
487 * This "function" does not return, instead it continues in RAM
488 * after relocating the monitor code.
492 * r5 = length in bytes
497 mr r1, r3 /* Set new stack pointer */
498 mr r9, r4 /* Save copy of Global Data pointer */
499 mr r10, r5 /* Save copy of Destination Address */
501 mr r3, r5 /* Destination Address */
502 lis r4, CFG_MONITOR_BASE@h /* Source Address */
503 ori r4, r4, CFG_MONITOR_BASE@l
504 lwz r5, GOT(__init_end)
506 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
511 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE)
512 * + Destination Address
518 /* First our own GOT */
520 /* then the one used by the C code */
529 beq cr1,4f /* In place copy is not necessary */
530 beq 7f /* Protect against 0 count */
559 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
567 * Now flush the cache: note that we must start from a cache aligned
568 * address. Otherwise we might miss one cache line.
572 beq 7f /* Always flush prefetch queue in any case */
580 sync /* Wait for all dcbst to complete on bus */
586 7: sync /* Wait for all icbi to complete on bus */
590 * We are done. Do not return, instead branch to second part of board
591 * initialization, now running from RAM.
593 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
599 * Relocation Function, r14 point to got2+0x8000
601 * Adjust got2 pointers, no need to check for 0, this code
602 * already puts a few entries in the table.
604 li r0,__got2_entries@sectoff@l
605 la r3,GOT(_GOT2_TABLE_)
606 lwz r11,GOT(_GOT2_TABLE_)
616 * Now adjust the fixups and the pointers to the fixups
617 * in case we need to move ourselves again.
619 2: li r0,__fixup_entries@sectoff@l
620 lwz r3,GOT(_FIXUP_TABLE_)
634 * Now clear BSS segment
636 lwz r3,GOT(__bss_start)
649 mr r3, r9 /* Global Data pointer */
650 mr r4, r10 /* Destination Address */
654 * Copy exception vector code to low memory
657 * r7: source address, r8: end address, r9: target address
662 lwz r8, GOT(_end_of_vectors)
664 li r9, 0x100 /* reset vector at 0x100 */
667 bgelr /* return if r7>=r8 - just in case */
669 mflr r4 /* save link register */
679 * relocate `hdlr' and `int_return' entries
681 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
682 li r8, Alignment - _start + EXC_OFF_SYS_RESET
685 addi r7, r7, 0x100 /* next exception vector */
689 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
692 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
695 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
696 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
699 addi r7, r7, 0x100 /* next exception vector */
703 li r7, .L_Trace - _start + EXC_OFF_SYS_RESET
704 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
707 addi r7, r7, 0x100 /* next exception vector */
711 mfmsr r3 /* now that the vectors have */
712 lis r7, MSR_IP@h /* relocated into low memory */
713 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
714 andc r3, r3, r7 /* (if it was on) */
715 SYNC /* Some chip revs need this... */
719 mtlr r4 /* restore link register */
723 * Function: relocate entries for one exception vector
726 lwz r0, 0(r7) /* hdlr ... */
727 add r0, r0, r3 /* ... += dest_addr */
730 lwz r0, 4(r7) /* int_return ... */
731 add r0, r0, r3 /* ... += dest_addr */