2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * Breath some life into the CPU...
30 * Set up the memory map,
31 * initialize a bunch of registers.
33 void cpu_init_f (void)
35 DECLARE_GLOBAL_DATA_PTR;
37 volatile flexbus8220_t *flexbus = (volatile flexbus8220_t *) MMAP_FB;
38 volatile pcfg8220_t *portcfg = (volatile pcfg8220_t *) MMAP_PCFG;
39 volatile xlbarb8220_t *xlbarb = (volatile xlbarb8220_t *) MMAP_XLBARB;
41 /* Pointer is writable since we allocated a register for it */
42 gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
44 /* Clear initial global data */
45 memset ((void *) gd, 0, sizeof (gd_t));
47 /* Clear all port configuration */
54 * Flexbus Controller: configure chip selects and enable them
56 #if defined (CFG_CS0_BASE)
57 flexbus->csar0 = CFG_CS0_BASE;
58 flexbus->cscr0 = CFG_CS0_CTRL;
59 flexbus->csmr0 = ((CFG_CS0_MASK - 1) & 0xffff0000) | 1;
60 __asm__ volatile ("sync");
62 #if defined (CFG_CS1_BASE)
63 flexbus->csar1 = CFG_CS1_BASE;
64 flexbus->cscr1 = CFG_CS1_CTRL;
65 flexbus->csmr1 = ((CFG_CS1_MASK - 1) & 0xffff0000) | 1;
66 __asm__ volatile ("sync");
68 #if defined (CFG_CS2_BASE)
69 flexbus->csar2 = CFG_CS2_BASE;
70 flexbus->cscr2 = CFG_CS2_CTRL;
71 flexbus->csmr2 = ((CFG_CS2_MASK - 1) & 0xffff0000) | 1;
72 portcfg->pcfg3 |= CFG_CS2_PORT3_CONFIG;
73 __asm__ volatile ("sync");
75 #if defined (CFG_CS3_BASE)
76 flexbus->csar3 = CFG_CS3_BASE;
77 flexbus->cscr3 = CFG_CS3_CTRL;
78 flexbus->csmr3 = ((CFG_CS3_MASK - 1) & 0xffff0000) | 1;
79 portcfg->pcfg3 |= CFG_CS3_PORT3_CONFIG;
80 __asm__ volatile ("sync");
82 #if defined (CFG_CS4_BASE)
83 flexbus->csar4 = CFG_CS4_BASE;
84 flexbus->cscr4 = CFG_CS4_CTRL;
85 flexbus->csmr4 = ((CFG_CS4_MASK - 1) & 0xffff0000) | 1;
86 portcfg->pcfg3 |= CFG_CS4_PORT3_CONFIG;
87 __asm__ volatile ("sync");
89 #if defined (CFG_CS5_BASE)
90 flexbus->csar5 = CFG_CS5_BASE;
91 flexbus->cscr5 = CFG_CS5_CTRL;
92 flexbus->csmr5 = ((CFG_CS5_MASK - 1) & 0xffff0000) | 1;
93 portcfg->pcfg3 |= CFG_CS5_PORT3_CONFIG;
94 __asm__ volatile ("sync");
97 /* This section of the code cannot place in cpu_init_r(),
98 it will cause the system to hang */
100 xlbarb->config = 0x00002000;
102 xlbarb->addrTenTimeOut = 0x1000;
103 xlbarb->dataTenTimeOut = 0x1000;
104 xlbarb->busActTimeOut = 0x2000;
106 /* Master Priority Enable */
107 xlbarb->mastPriEn = 0x1f;
108 xlbarb->mastPriority = 0;
112 * initialize higher level parts of CPU like time base and timers
114 int cpu_init_r (void)
116 /* this may belongs to disable interrupt section */
117 /* mask all interrupts */
118 *(vu_long *) 0xf0000700 = 0xfffffc00;
119 *(vu_long *) 0xf0000714 |= 0x0001ffff;
120 *(vu_long *) 0xf0000710 &= ~0x00000f00;
122 /* route critical ints to normal ints */
123 *(vu_long *) 0xf0000710 |= 0x00000001;
125 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC8220_FEC)
126 /* load FEC microcode */