3 /*********************************************************
5 * copyright @ Motorola, 1999
6 *********************************************************/
8 #define I2O_REG_OFFSET 0x0004
10 #define PCI_CFG_CLA 0x0B
11 #define PCI_CFG_SCL 0x0A
12 #define PCI_CFG_PIC 0x09
14 #define I2O_IMR0 0x0050
15 #define I2O_IMR1 0x0054
16 #define I2O_OMR0 0x0058
17 #define I2O_OMR1 0x005C
19 #define I2O_ODBR 0x0060
20 #define I2O_IDBR 0x0068
22 #define I2O_OMISR 0x0030
23 #define I2O_OMIMR 0x0034
24 #define I2O_IMISR 0x0100
25 #define I2O_IMIMR 0x0104
27 /* accessable to PCI master but local processor */
28 #define I2O_IFQPR 0x0040
29 #define I2O_OFQPR 0x0044
31 /* accessable to local processor */
32 #define I2O_IFHPR 0x0120
33 #define I2O_IFTPR 0x0128
34 #define I2O_IPHPR 0x0130
35 #define I2O_IPTPR 0x0138
36 #define I2O_OFHPR 0x0140
37 #define I2O_OFTPR 0x0148
38 #define I2O_OPHPR 0x0150
39 #define I2O_OPTPR 0x0158
40 #define I2O_MUCR 0x0164
41 #define I2O_QBAR 0x0170
45 typedef enum _i2o_status
57 typedef enum _queue_size
66 typedef enum _location
68 LOCAL = 0, /* used by local processor to access its own on board device,
69 local processor's eumbbar is required */
70 REMOTE, /* used by PCI master to access the devices on its PCI device,
71 device's pcsrbar is required */
75 typedef enum _i2o_in_db
78 MC, /* machine check */
81 /* I2O PCI configuration identification */
82 typedef struct _i2o_iop
84 unsigned int base_class : 8;
85 unsigned int sub_class : 8;
86 unsigned int prg_code : 8;
89 /* I2O Outbound Message Interrupt Status Register */
90 typedef struct _i2o_om_stat
92 unsigned int rsvd0 : 26;
93 unsigned int opqi : 1;
94 unsigned int rsvd1 : 1;
96 unsigned int rsvd2 : 1;
97 unsigned int om1i : 1;
98 unsigned int om0i : 1;
101 /* I2O inbound Message Interrupt Status Register */
102 typedef struct _i2o_im_stat
104 unsigned int rsvd0 : 23;
105 unsigned int ofoi : 1;
106 unsigned int ipoi : 1;
107 unsigned int rsvd1 : 1;
108 unsigned int ipqi : 1;
109 unsigned int mci : 1;
110 unsigned int idi : 1;
111 unsigned int rsvd2 : 1;
112 unsigned int im1i : 1;
113 unsigned int im0i : 1;
117 Enable the interrupt associated with in/out bound msg
119 Inbound message interrupt generated by PCI master and serviced by local processor
120 local processor needs to enable its inbound interrupts it wants to handle (LOCAL)
122 Outbound message interrupt generated by local processor and serviced by PCI master
123 PCI master needs to enable the devices' outbound interrupts it wants to handle (REMOTE)
125 extern I2OSTATUS I2OMsgEnable( LOCATION, /* REMOTE/LOCAL */
126 unsigned int base, /* pcsrbar/eumbbar */
127 unsigned char n ); /* b'1' - msg 0
133 Disable the interrupt associated with in/out bound msg
135 local processor needs to disable its inbound interrupts it is not interested (LOCAL)
137 PCI master needs to disable outbound interrupts of devices it is not interested (REMOTE)
139 extern I2OSTATUS I2OMsgDisable( LOCATION, /* REMOTE/LOCAL */
140 unsigned int base, /* pcsrbar/eumbbar */
141 unsigned char n ); /* b'1' - msg 0
147 Read the msg register either from local inbound msg 0/1,
148 or an outbound msg 0/1 of devices.
150 If it is not local, pcsrbar must be passed to the function.
151 Otherwise eumbbar is passed.
153 If it is remote, outbound msg of the device is read.
154 Otherwise local inbound msg is read.
156 extern I2OSTATUS I2OMsgGet ( LOCATION, /* REMOTE/LOCAL */
157 unsigned int base, /*pcsrbar/eumbbar */
158 unsigned int n, /* 0 or 1 */
162 Write to nth Msg register either on local outbound msg 0/1,
163 or aninbound msg 0/1 of devices
165 If it is not local, pcsrbar must be passed to the function.
166 Otherwise eumbbar is passed.
168 If it is remote, inbound msg on the device is written.
169 Otherwise local outbound msg is written.
171 extern I2OSTATUS I2OMsgPost( LOCATION, /* REMOTE/LOCAL */
172 unsigned int base, /*pcsrbar/eumbbar */
173 unsigned int n, /* 0 or 1 */
177 Enable the In/Out DoorBell Interrupt
179 InDoorBell interrupt is generated by PCI master and serviced by local processor
180 local processor needs to enable its inbound doorbell interrupts it wants to handle
182 OutDoorbell interrupt is generated by local processor and serviced by PCI master
183 PCI master needs to enable outbound doorbell interrupts of the devices it wants to handle
185 extern I2OSTATUS I2ODBEnable( LOCATION, /* REMOTE/LOCAL */
186 unsigned int base, /* pcsrbar/eumbbar */
187 unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
190 Disable the In/Out DoorBell Interrupt
192 local processor needs to disable its inbound doorbell interrupts it is not interested
194 PCI master needs to disable outbound doorbell interrupts of devices it is not interested
197 extern I2OSTATUS I2ODBDisable( LOCATION, /* REMOTE/LOCAL */
198 unsigned int base, /* pcsrbar/eumbbar */
199 unsigned int in_db ); /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
202 Read a local indoorbell register, or an outdoorbell of devices.
203 Reading a doorbell register, the register will be cleared.
205 If it is not local, pcsrbar must be passed to the function.
206 Otherwise eumbbar is passed.
208 If it is remote, outdoorbell register on the device is read.
209 Otherwise local in doorbell is read
211 extern unsigned int I2ODBGet( LOCATION, /* REMOTE/LOCAL */
212 unsigned int base); /* pcsrbar/eumbbar */
215 Write to a local outdoorbell register, or an indoorbell register of devices.
217 If it is not local, pcsrbar must be passed to the function.
218 Otherwise eumbbar is passed.
220 If it is remote, in doorbell register on the device is written.
221 Otherwise local out doorbell is written
223 extern void I2ODBPost( LOCATION, /* REMOTE/LOCAL */
224 unsigned int base, /* pcsrbar/eumbbar */
225 unsigned int msg ); /* in / out */
228 Read the outbound msg unit interrupt status of devices. Reading an interrupt status register,
229 the register will be cleared.
231 The outbound interrupt status is AND with the outbound
232 interrupt mask. The result is returned.
234 PCI master must pass the pcsrbar to the function.
236 extern I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT * );
239 Read the inbound msg unit interrupt status. Reading an interrupt status register,
240 the register will be cleared.
242 The inbound interrupt status is AND with the inbound
243 interrupt mask. The result is returned.
245 Local process must pass its eumbbar to the function.
247 extern I2OSTATUS I2OInMsgStatGet( unsigned int eumbbar, I2OIMSTAT * );
250 Configure the I2O FIFO, including QBAR, IFHPR/IFTPR,IPHPR/IPTPR,OFHPR/OFTPR, OPHPR/OPTPR,
253 extern I2OSTATUS I2OFIFOInit( unsigned int eumbbar,
255 unsigned int qba);/* queue base address that must be aligned at 1M */
257 Enable the circular queue
259 extern I2OSTATUS I2OFIFOEnable( unsigned int eumbbar );
262 Disable the circular queue
264 extern void I2OFIFODisable( unsigned int eumbbar );
267 Enable the circular queue interrupt
268 PCI master enables outbound FIFO interrupt of device
269 Device enables its inbound FIFO interrupt
271 extern void I2OFIFOIntEnable( LOCATION, unsigned int base );
274 Disable the circular queue interrupt
275 PCI master disables outbound FIFO interrupt of device
276 Device disables its inbound FIFO interrupt
278 extern void I2OFIFOIntDisable( LOCATION, unsigned int base );
281 Enable the circular queue overflow interrupt
283 extern void I2OFIFOOverflowIntEnable( unsigned int eumbbar );
286 Disable the circular queue overflow interrupt
288 extern void I2OFIFOOverflowIntDisable( unsigned int eumbbar );
291 Allocate a free msg frame from free FIFO.
293 PCI Master allocates a free msg frame through inbound queue port of device(IFQPR)
294 while local processor allocates a free msg frame from outbound free queue(OFTPR)
296 Unless both free queues are initialized, allocating a free MF will return 0xffffffff
298 extern I2OSTATUS I2OFIFOAlloc( LOCATION,
302 Free a used msg frame back to free queue
303 PCI Master frees a MFA through outbound queue port of device(OFQPR)
304 while local processor frees a MFA into its inbound free queue(IFHPR)
306 Used msg frame does not need to be recycled in the order they
309 This function has to be called by PCI master to initialize Inbound free queue
310 and by device to initialize Outbound free queue before I2OFIFOAlloc can be used.
312 extern I2OSTATUS I2OFIFOFree( LOCATION,
318 PCI Master posts a msg through inbound queue port of device(IFQPR)
319 while local processor post a msg into its outbound post queue(OPHPR)
321 The total number of msg must be less than the max size of the queue
322 Otherwise queue overflow interrupt will assert.
324 extern I2OSTATUS I2OFIFOPost( LOCATION,
330 PCI Master reads a msg through outbound queue port of device(OFQPR)
331 while local processor reads a msg from its inbound post queue(IPTPR)
333 extern I2OSTATUS I2OFIFOGet( LOCATION,
338 Get the I2O PCI configuration identification register
340 extern I2OSTATUS I2OPCIConfigGet( LOCATION,