2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00
30 #include <mpc8260_irq.h>
31 #include <asm/processor.h>
33 /****************************************************************************/
35 unsigned decrementer_count; /* count val for 1e6/HZ microseconds */
38 interrupt_handler_t *handler;
43 static struct irq_action irq_handlers[NR_IRQS];
45 static ulong ppc_cached_irq_mask[NR_MASK_WORDS];
47 /****************************************************************************/
48 /* this section was ripped out of arch/ppc/kernel/ppc8260_pic.c in the */
49 /* Linux/PPC 2.4.x source. There was no copyright notice in that file. */
51 /* The 8260 internal interrupt controller. It is usually
52 * the only interrupt controller.
53 * There are two 32-bit registers (high/low) for up to 64
54 * possible interrupts.
56 * Now, the fun starts.....Interrupt Numbers DO NOT MAP
57 * in a simple arithmetic fashion to mask or pending registers.
58 * That is, interrupt 4 does not map to bit position 4.
59 * We create two tables, indexed by vector number, to indicate
60 * which register to use and which bit in the register to use.
62 static u_char irq_to_siureg[] = {
63 1, 1, 1, 1, 1, 1, 1, 1,
64 1, 1, 1, 1, 1, 1, 1, 1,
65 0, 0, 0, 0, 0, 0, 0, 0,
66 0, 0, 0, 0, 0, 0, 0, 0,
67 1, 1, 1, 1, 1, 1, 1, 1,
68 1, 1, 1, 1, 1, 1, 1, 1,
69 0, 0, 0, 0, 0, 0, 0, 0,
70 0, 0, 0, 0, 0, 0, 0, 0
73 static u_char irq_to_siubit[] = {
74 31, 16, 17, 18, 19, 20, 21, 22,
75 23, 24, 25, 26, 27, 28, 29, 30,
76 29, 30, 16, 17, 18, 19, 20, 21,
77 22, 23, 24, 25, 26, 27, 28, 31,
78 0, 1, 2, 3, 4, 5, 6, 7,
79 8, 9, 10, 11, 12, 13, 14, 15,
80 15, 14, 13, 12, 11, 10, 9, 8,
81 7, 6, 5, 4, 3, 2, 1, 0
84 static void m8260_mask_irq (unsigned int irq_nr)
86 volatile immap_t *immr = (immap_t *) CFG_IMMR;
90 bit = irq_to_siubit[irq_nr];
91 word = irq_to_siureg[irq_nr];
93 simr = &(immr->im_intctl.ic_simrh);
94 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
95 simr[word] = ppc_cached_irq_mask[word];
98 static void m8260_unmask_irq (unsigned int irq_nr)
100 volatile immap_t *immr = (immap_t *) CFG_IMMR;
104 bit = irq_to_siubit[irq_nr];
105 word = irq_to_siureg[irq_nr];
107 simr = &(immr->im_intctl.ic_simrh);
108 ppc_cached_irq_mask[word] |= (1 << (31 - bit));
109 simr[word] = ppc_cached_irq_mask[word];
112 static void m8260_mask_and_ack (unsigned int irq_nr)
114 volatile immap_t *immr = (immap_t *) CFG_IMMR;
116 volatile uint *simr, *sipnr;
118 bit = irq_to_siubit[irq_nr];
119 word = irq_to_siureg[irq_nr];
121 simr = &(immr->im_intctl.ic_simrh);
122 sipnr = &(immr->im_intctl.ic_sipnrh);
123 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
124 simr[word] = ppc_cached_irq_mask[word];
125 sipnr[word] = 1 << (31 - bit);
128 static int m8260_get_irq (struct pt_regs *regs)
130 volatile immap_t *immr = (immap_t *) CFG_IMMR;
134 /* For MPC8260, read the SIVEC register and shift the bits down
135 * to get the irq number. */
136 bits = immr->im_intctl.ic_sivec;
141 /* end of code ripped out of arch/ppc/kernel/ppc8260_pic.c */
142 /****************************************************************************/
144 static __inline__ unsigned long get_msr (void)
148 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
153 static __inline__ void set_msr (unsigned long msr)
155 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
158 static __inline__ unsigned long get_dec (void)
162 __asm__ __volatile__ ("mfdec %0":"=r" (val):);
167 static __inline__ void set_dec (unsigned long val)
169 __asm__ __volatile__ ("mtdec %0"::"r" (val));
172 void enable_interrupts (void)
174 set_msr (get_msr () | MSR_EE);
177 /* returns flag if MSR_EE was set before */
178 int disable_interrupts (void)
180 ulong msr = get_msr ();
182 set_msr (msr & ~MSR_EE);
183 return ((msr & MSR_EE) != 0);
186 /****************************************************************************/
188 int interrupt_init (void)
190 DECLARE_GLOBAL_DATA_PTR;
192 volatile immap_t *immr = (immap_t *) CFG_IMMR;
194 decrementer_count = (gd->bus_clk / 4) / CFG_HZ;
196 /* Initialize the default interrupt mapping priorities */
197 immr->im_intctl.ic_sicr = 0;
198 immr->im_intctl.ic_siprr = 0x05309770;
199 immr->im_intctl.ic_scprrh = 0x05309770;
200 immr->im_intctl.ic_scprrl = 0x05309770;
202 /* disable all interrupts and clear all pending bits */
203 immr->im_intctl.ic_simrh = ppc_cached_irq_mask[0] = 0;
204 immr->im_intctl.ic_simrl = ppc_cached_irq_mask[1] = 0;
205 immr->im_intctl.ic_sipnrh = 0xffffffff;
206 immr->im_intctl.ic_sipnrl = 0xffffffff;
208 set_dec (decrementer_count);
210 set_msr (get_msr () | MSR_EE);
215 /****************************************************************************/
218 * Handle external interrupts
220 void external_interrupt (struct pt_regs *regs)
224 irq = m8260_get_irq (regs);
226 m8260_mask_and_ack (irq);
228 set_msr (get_msr () | MSR_EE);
230 if (irq_handlers[irq].handler != NULL)
231 (*irq_handlers[irq].handler) (irq_handlers[irq].arg);
233 printf ("\nBogus External Interrupt IRQ %d\n", irq);
235 * turn off the bogus interrupt, otherwise it
236 * might repeat forever
242 m8260_unmask_irq (irq);
245 /****************************************************************************/
248 * Install and free an interrupt handler.
252 irq_install_handler (int irq, interrupt_handler_t * handler, void *arg)
254 if (irq < 0 || irq >= NR_IRQS) {
255 printf ("irq_install_handler: bad irq number %d\n", irq);
259 if (irq_handlers[irq].handler != NULL)
260 printf ("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
261 (ulong) handler, (ulong) irq_handlers[irq].handler);
263 irq_handlers[irq].handler = handler;
264 irq_handlers[irq].arg = arg;
266 m8260_unmask_irq (irq);
269 void irq_free_handler (int irq)
271 if (irq < 0 || irq >= NR_IRQS) {
272 printf ("irq_free_handler: bad irq number %d\n", irq);
276 m8260_mask_irq (irq);
278 irq_handlers[irq].handler = NULL;
279 irq_handlers[irq].arg = NULL;
282 /****************************************************************************/
284 volatile ulong timestamp = 0;
287 * timer_interrupt - gets called when the decrementer overflows,
288 * with interrupts disabled.
289 * Trivial implementation - no need to be really accurate.
291 void timer_interrupt (struct pt_regs *regs)
293 #if defined(CONFIG_WATCHDOG) || defined(CFG_HYMOD_DBLEDS)
294 volatile immap_t *immr = (immap_t *) CFG_IMMR;
295 #endif /* CONFIG_WATCHDOG */
297 /* Restore Decrementer Count */
298 set_dec (decrementer_count);
302 #if defined(CONFIG_WATCHDOG) || \
303 defined(CFG_CMA_LCD_HEARTBEAT) || \
304 defined(CFG_HYMOD_DBLEDS)
306 if ((timestamp % CFG_HZ) == 0) {
307 #if defined(CFG_CMA_LCD_HEARTBEAT)
308 extern void lcd_heartbeat (void);
309 #endif /* CFG_CMA_LCD_HEARTBEAT */
310 #if defined(CFG_HYMOD_DBLEDS)
311 volatile iop8260_t *iop = &immr->im_ioport;
312 static int shift = 0;
313 #endif /* CFG_HYMOD_DBLEDS */
315 #if defined(CFG_CMA_LCD_HEARTBEAT)
317 #endif /* CFG_CMA_LCD_HEARTBEAT */
319 #if defined(CONFIG_WATCHDOG)
320 reset_8260_watchdog (immr);
321 #endif /* CONFIG_WATCHDOG */
323 #if defined(CFG_HYMOD_DBLEDS)
324 /* hymod daughter board LEDs */
328 (iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift));
329 #endif /* CFG_HYMOD_DBLEDS */
331 #endif /* CONFIG_WATCHDOG || CFG_CMA_LCD_HEARTBEAT */
334 /****************************************************************************/
336 void reset_timer (void)
341 ulong get_timer (ulong base)
343 return (timestamp - base);
346 void set_timer (ulong t)
351 /****************************************************************************/
353 #if (CONFIG_COMMANDS & CFG_CMD_IRQ)
355 /* ripped this out of ppc4xx/interrupts.c */
357 /*******************************************************************************
359 * irqinfo - print information about PCI devices
363 do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
367 re_enable = disable_interrupts ();
369 printf ("\nInterrupt-Information:\n");
370 printf ("Nr Routine Arg Count\n");
372 for (irq = 0; irq < 32; irq++)
373 if (irq_handlers[irq].handler != NULL)
374 printf ("%02d %08lx %08lx %ld\n", irq,
375 (ulong) irq_handlers[irq].handler,
376 (ulong) irq_handlers[irq].arg,
377 irq_handlers[irq].count);
380 enable_interrupts ();
383 #endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */