cpu/mpc85xx/fdt.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <libfdt.h>
  28 #include <fdt_support.h>
  29 #include <asm/processor.h>
  30 #ifdef CONFIG_FSL_ESDHC
  31 #include <fsl_esdhc.h>
  32 #endif
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 extern void ft_qe_setup(void *blob);
  37 extern void ft_fixup_num_cores(void *blob);
  38
  39 #ifdef CONFIG_MP
  40 #include "mp.h"
  41
  42 void ft_fixup_cpu(void *blob, u64 memory_limit)
  43 {
  44         int off;
  45         ulong spin_tbl_addr = get_spin_addr();
  46         u32 bootpg = determine_mp_bootpg();
  47         u32 id = get_my_id();
  48
  49         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  50         while (off != -FDT_ERR_NOTFOUND) {
  51                 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  52
  53                 if (reg) {
  54                         if (*reg == id) {
  55                                 fdt_setprop_string(blob, off, "status", "okay");
  56                         } else {
  57                                 u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
  58                                 val = cpu_to_fdt32(val);
  59                                 fdt_setprop_string(blob, off, "status",
  60                                                                 "disabled");
  61                                 fdt_setprop_string(blob, off, "enable-method",
  62                                                                 "spin-table");
  63                                 fdt_setprop(blob, off, "cpu-release-addr",
  64                                                 &val, sizeof(val));
  65                         }
  66                 } else {
  67                         printf ("cpu NULL\n");
  68                 }
  69                 off = fdt_node_offset_by_prop_value(blob, off,
  70                                 "device_type", "cpu", 4);
  71         }
  72
  73         /* Reserve the boot page so OSes dont use it */
  74         if ((u64)bootpg < memory_limit) {
  75                 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
  76                 if (off < 0)
  77                         printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
  78         }
  79 }
  80 #endif
  81
  82 #define ft_fixup_l3cache(x, y)
  83
  84 #if defined(CONFIG_L2_CACHE)
  85 /* return size in kilobytes */
  86 static inline u32 l2cache_size(void)
  87 {
  88         volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
  89         volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
  90         u32 ver = SVR_SOC_VER(get_svr());
  91
  92         switch (l2siz_field) {
  93         case 0x0:
  94                 break;
  95         case 0x1:
  96                 if (ver == SVR_8540 || ver == SVR_8560   ||
  97                     ver == SVR_8541 || ver == SVR_8541_E ||
  98                     ver == SVR_8555 || ver == SVR_8555_E)
  99                         return 128;
 100                 else
 101                         return 256;
 102                 break;
 103         case 0x2:
 104                 if (ver == SVR_8540 || ver == SVR_8560   ||
 105                     ver == SVR_8541 || ver == SVR_8541_E ||
 106                     ver == SVR_8555 || ver == SVR_8555_E)
 107                         return 256;
 108                 else
 109                         return 512;
 110                 break;
 111         case 0x3:
 112                 return 1024;
 113                 break;
 114         }
 115
 116         return 0;
 117 }
 118
 119 static inline void ft_fixup_l2cache(void *blob)
 120 {
 121         int len, off;
 122         u32 *ph;
 123         struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
 124         char compat_buf[38];
 125
 126         const u32 line_size = 32;
 127         const u32 num_ways = 8;
 128         const u32 size = l2cache_size() * 1024;
 129         const u32 num_sets = size / (line_size * num_ways);
 130
 131         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 132         if (off < 0) {
 133                 debug("no cpu node fount\n");
 134                 return;
 135         }
 136
 137         ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
 138
 139         if (ph == NULL) {
 140                 debug("no next-level-cache property\n");
 141                 return ;
 142         }
 143
 144         off = fdt_node_offset_by_phandle(blob, *ph);
 145         if (off < 0) {
 146                 printf("%s: %s\n", __func__, fdt_strerror(off));
 147                 return ;
 148         }
 149
 150         if (cpu) {
 151                 len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller",
 152                                 cpu->name);
 153                 sprintf(&compat_buf[len + 1], "cache");
 154         }
 155         fdt_setprop(blob, off, "cache-unified", NULL, 0);
 156         fdt_setprop_cell(blob, off, "cache-block-size", line_size);
 157         fdt_setprop_cell(blob, off, "cache-size", size);
 158         fdt_setprop_cell(blob, off, "cache-sets", num_sets);
 159         fdt_setprop_cell(blob, off, "cache-level", 2);
 160         fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
 161
 162         /* we dont bother w/L3 since no platform of this type has one */
 163 }
 164 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
 165 static inline void ft_fixup_l2cache(void *blob)
 166 {
 167         int off, l2_off, l3_off = -1;
 168         u32 *ph;
 169         u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 170         u32 size, line_size, num_ways, num_sets;
 171
 172         size = (l2cfg0 & 0x3fff) * 64 * 1024;
 173         num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
 174         line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
 175         num_sets = size / (line_size * num_ways);
 176
 177         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 178
 179         while (off != -FDT_ERR_NOTFOUND) {
 180                 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
 181
 182                 if (ph == NULL) {
 183                         debug("no next-level-cache property\n");
 184                         goto next;
 185                 }
 186
 187                 l2_off = fdt_node_offset_by_phandle(blob, *ph);
 188                 if (l2_off < 0) {
 189                         printf("%s: %s\n", __func__, fdt_strerror(off));
 190                         goto next;
 191                 }
 192
 193                 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
 194                 fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
 195                 fdt_setprop_cell(blob, l2_off, "cache-size", size);
 196                 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
 197                 fdt_setprop_cell(blob, l2_off, "cache-level", 2);
 198                 fdt_setprop(blob, l2_off, "compatible", "cache", 6);
 199
 200                 if (l3_off < 0) {
 201                         ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
 202
 203                         if (ph == NULL) {
 204                                 debug("no next-level-cache property\n");
 205                                 goto next;
 206                         }
 207                         l3_off = *ph;
 208                 }
 209 next:
 210                 off = fdt_node_offset_by_prop_value(blob, off,
 211                                 "device_type", "cpu", 4);
 212         }
 213         if (l3_off > 0) {
 214                 l3_off = fdt_node_offset_by_phandle(blob, l3_off);
 215                 if (l3_off < 0) {
 216                         printf("%s: %s\n", __func__, fdt_strerror(off));
 217                         return ;
 218                 }
 219                 ft_fixup_l3cache(blob, l3_off);
 220         }
 221 }
 222 #else
 223 #define ft_fixup_l2cache(x)
 224 #endif
 225
 226 static inline void ft_fixup_cache(void *blob)
 227 {
 228         int off;
 229
 230         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 231
 232         while (off != -FDT_ERR_NOTFOUND) {
 233                 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
 234                 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
 235                 u32 isize, iline_size, inum_sets, inum_ways;
 236                 u32 dsize, dline_size, dnum_sets, dnum_ways;
 237
 238                 /* d-side config */
 239                 dsize = (l1cfg0 & 0x7ff) * 1024;
 240                 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
 241                 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
 242                 dnum_sets = dsize / (dline_size * dnum_ways);
 243
 244                 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
 245                 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
 246                 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
 247
 248                 /* i-side config */
 249                 isize = (l1cfg1 & 0x7ff) * 1024;
 250                 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
 251                 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
 252                 inum_sets = isize / (iline_size * inum_ways);
 253
 254                 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
 255                 fdt_setprop_cell(blob, off, "i-cache-size", isize);
 256                 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
 257
 258                 off = fdt_node_offset_by_prop_value(blob, off,
 259                                 "device_type", "cpu", 4);
 260         }
 261
 262         ft_fixup_l2cache(blob);
 263 }
 264
 265
 266 void fdt_add_enet_stashing(void *fdt)
 267 {
 268         do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
 269
 270         do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
 271
 272         do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
 273 }
 274
 275 void ft_cpu_setup(void *blob, bd_t *bd)
 276 {
 277         int off;
 278         int val;
 279         sys_info_t sysinfo;
 280
 281         /* delete crypto node if not on an E-processor */
 282         if (!IS_E_PROCESSOR(get_svr()))
 283                 fdt_fixup_crypto_node(blob, 0);
 284
 285         fdt_fixup_ethernet(blob);
 286
 287         fdt_add_enet_stashing(blob);
 288
 289         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 290                 "timebase-frequency", bd->bi_busfreq / 8, 1);
 291         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 292                 "bus-frequency", bd->bi_busfreq, 1);
 293         get_sys_info(&sysinfo);
 294         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 295         while (off != -FDT_ERR_NOTFOUND) {
 296                 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 297                 val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]);
 298                 fdt_setprop(blob, off, "clock-frequency", &val, 4);
 299                 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
 300                                                         "cpu", 4);
 301         }
 302         do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
 303                 "bus-frequency", bd->bi_busfreq, 1);
 304
 305         do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
 306                 "bus-frequency", gd->lbc_clk, 1);
 307         do_fixup_by_compat_u32(blob, "fsl,elbc",
 308                 "bus-frequency", gd->lbc_clk, 1);
 309 #ifdef CONFIG_QE
 310         ft_qe_setup(blob);
 311 #endif
 312
 313 #ifdef CONFIG_SYS_NS16550
 314         do_fixup_by_compat_u32(blob, "ns16550",
 315                 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 316 #endif
 317
 318 #ifdef CONFIG_CPM2
 319         do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
 320                 "current-speed", bd->bi_baudrate, 1);
 321
 322         do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
 323                 "clock-frequency", bd->bi_brgfreq, 1);
 324 #endif
 325
 326         fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 327
 328 #ifdef CONFIG_MP
 329         ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
 330 #endif
 331         ft_fixup_num_cores(blob);
 332
 333         ft_fixup_cache(blob);
 334
 335 #if defined(CONFIG_FSL_ESDHC)
 336         fdt_fixup_esdhc(blob, bd);
 337 #endif
 338 }