2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * written or collected and sometimes rewritten by
30 * Magnus Damm <damm@bitsmart.com>
32 * minor modifications by
33 * Wolfgang Denk <wd@denx.de>
41 #include <asm/cache.h>
43 #if defined(CONFIG_OF_LIBFDT)
45 #include <libfdt_env.h>
46 #include <fdt_support.h>
49 DECLARE_GLOBAL_DATA_PTR;
51 static char *cpu_warning = "\n " \
52 "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
54 #if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
55 !defined(CONFIG_MPC862))
57 static int check_CPU (long clock, uint pvr, uint immr)
60 # if defined(CONFIG_MPC855)
62 # elif defined(CONFIG_MPC860P)
67 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
74 /* the highest 16 bits should be 0x0050 for a 860 */
76 if ((pvr >> 16) != 0x0050)
79 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
84 * Some boards use sockets so different CPUs can be used.
85 * We have to check chip version in run time.
88 case 0x00020001: pre = 'P'; break;
89 case 0x00030001: break;
90 case 0x00120003: suf = "A"; break;
91 case 0x00130003: suf = "A3"; break;
93 case 0x00200004: suf = "B"; break;
95 case 0x00300004: suf = "C"; break;
96 case 0x00310004: suf = "C1"; m = 1; break;
98 case 0x00200064: mid = "SR"; suf = "B"; break;
99 case 0x00300065: mid = "SR"; suf = "C"; break;
100 case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
101 case 0x05010000: suf = "D3"; m = 1; break;
102 case 0x05020000: suf = "D4"; m = 1; break;
103 /* this value is not documented anywhere */
104 case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
105 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
106 case 0x08010004: /* Rev. A.0 */
109 case 0x08000003: /* Rev. 0.3 */
113 # if defined(CONFIG_MPC852T)
115 # elif defined(CONFIG_MPC859T)
117 # elif defined(CONFIG_MPC859DSL)
119 # elif defined(CONFIG_MPC866T)
122 "PC866x"; /* Unknown chip from MPC866 family */
125 case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
127 id_str = "PC885"; /* 870/875/880/885 */
130 default: suf = NULL; break;
134 id_str = "PC86x"; /* Unknown 86x chip */
136 printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
138 printf ("unknown M%s (0x%08x)", id_str, k);
141 #if defined(CONFIG_SYS_8xx_CPUCLK_MIN) && defined(CONFIG_SYS_8xx_CPUCLK_MAX)
142 printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
144 CONFIG_SYS_8xx_CPUCLK_MIN / 1000000,
145 ((CONFIG_SYS_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
146 CONFIG_SYS_8xx_CPUCLK_MAX / 1000000,
147 ((CONFIG_SYS_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
150 printf (" at %s MHz: ", strmhz (buf, clock));
152 printf ("%u kB I-Cache %u kB D-Cache",
153 checkicache () >> 10,
157 /* do we have a FEC (860T/P or 852/859/866/885)? */
159 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
160 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
161 printf (" FEC present");
171 if(clock != measure_gclk()) {
172 printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
179 #elif defined(CONFIG_MPC862)
181 static int check_CPU (long clock, uint pvr, uint immr)
183 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
190 /* the highest 16 bits should be 0x0050 for a 8xx */
192 if ((pvr >> 16) != 0x0050)
195 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
200 /* this value is not documented anywhere */
201 case 0x06000000: mid = "P"; suf = "0"; break;
202 case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
203 case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
204 default: suf = NULL; break;
207 #ifndef CONFIG_MPC857
209 printf ("%cPC862%sZPnn%s", pre, mid, suf);
211 printf ("unknown MPC862 (0x%08x)", k);
214 printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */
216 printf ("unknown MPC857 (0x%08x)", k);
219 printf (" at %s MHz:", strmhz (buf, clock));
221 printf (" %u kB I-Cache", checkicache () >> 10);
222 printf (" %u kB D-Cache", checkdcache () >> 10);
224 /* lets check and see if we're running on a 862T (or P?) */
226 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
227 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
228 printf (" FEC present");
240 #elif defined(CONFIG_MPC823)
242 static int check_CPU (long clock, uint pvr, uint immr)
244 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
249 /* the highest 16 bits should be 0x0050 for a 8xx */
251 if ((pvr >> 16) != 0x0050)
254 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
259 case 0x20000000: suf = "0"; break;
260 case 0x20010000: suf = "0.1"; break;
261 case 0x20020000: suf = "Z2/3"; break;
262 case 0x20020001: suf = "Z3"; break;
263 case 0x21000000: suf = "A"; break;
264 case 0x21010000: suf = "B"; m = 1; break;
265 case 0x21010001: suf = "B2"; m = 1; break;
267 case 0x24010000: suf = NULL;
268 puts ("PPC823EZTnnB2");
273 printf ("unknown MPC823 (0x%08x)", k);
277 printf ("PPC823ZTnn%s", suf);
279 printf (" at %s MHz:", strmhz (buf, clock));
281 printf (" %u kB I-Cache", checkicache () >> 10);
282 printf (" %u kB D-Cache", checkdcache () >> 10);
284 /* lets check and see if we're running on a 860T (or P?) */
286 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
287 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
288 puts (" FEC present");
300 #elif defined(CONFIG_MPC850)
302 static int check_CPU (long clock, uint pvr, uint immr)
304 volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
308 /* the highest 16 bits should be 0x0050 for a 8xx */
310 if ((pvr >> 16) != 0x0050)
313 k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
318 printf ("XPC850xxZT");
321 printf ("XPC850xxZTA");
324 printf ("XPC850xxZTB");
328 printf ("XPC850xxZTC");
332 printf ("unknown MPC850 (0x%08x)", k);
334 printf (" at %s MHz:", strmhz (buf, clock));
336 printf (" %u kB I-Cache", checkicache () >> 10);
337 printf (" %u kB D-Cache", checkdcache () >> 10);
339 /* lets check and see if we're running on a 850T (or P?) */
341 immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
342 if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
343 printf (" FEC present");
357 /* ------------------------------------------------------------------------- */
361 ulong clock = gd->cpu_clk;
362 uint immr = get_immr (0); /* Return full IMMR contents */
363 uint pvr = get_pvr ();
367 /* 850 has PARTNUM 20 */
368 /* 801 has PARTNUM 10 */
369 return check_CPU (clock, pvr, immr);
372 /* ------------------------------------------------------------------------- */
374 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
375 /* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */
377 int checkicache (void)
379 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
380 volatile memctl8xx_t *memctl = &immap->im_memctl;
381 u32 cacheon = rd_ic_cst () & IDC_ENABLED;
384 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
386 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
391 wr_ic_cst (IDC_UNALL);
392 wr_ic_cst (IDC_INVALL);
393 wr_ic_cst (IDC_DISABLE);
394 __asm__ volatile ("isync");
396 while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
398 wr_ic_cst (IDC_LDLCK);
399 __asm__ volatile ("isync");
402 k += 0x10; /* the number of bytes in a cacheline */
405 wr_ic_cst (IDC_UNALL);
406 wr_ic_cst (IDC_INVALL);
409 wr_ic_cst (IDC_ENABLE);
411 wr_ic_cst (IDC_DISABLE);
413 __asm__ volatile ("isync");
418 /* ------------------------------------------------------------------------- */
420 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */
421 /* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */
422 /* call with cache disabled */
424 int checkdcache (void)
426 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
427 volatile memctl8xx_t *memctl = &immap->im_memctl;
428 u32 cacheon = rd_dc_cst () & IDC_ENABLED;
431 u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
433 u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
438 wr_dc_cst (IDC_UNALL);
439 wr_dc_cst (IDC_INVALL);
440 wr_dc_cst (IDC_DISABLE);
442 while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
444 wr_dc_cst (IDC_LDLCK);
446 k += 0x10; /* the number of bytes in a cacheline */
449 wr_dc_cst (IDC_UNALL);
450 wr_dc_cst (IDC_INVALL);
453 wr_dc_cst (IDC_ENABLE);
455 wr_dc_cst (IDC_DISABLE);
460 /* ------------------------------------------------------------------------- */
462 void upmconfig (uint upm, uint * table, uint size)
466 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
467 volatile memctl8xx_t *memctl = &immap->im_memctl;
469 for (i = 0; i < size; i++) {
470 memctl->memc_mdr = table[i]; /* (16-15) */
471 memctl->memc_mcr = addr | upm; /* (16-16) */
476 /* ------------------------------------------------------------------------- */
480 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
484 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
486 immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
488 /* Interrupts and MMU off */
489 __asm__ volatile ("mtspr 81, 0");
490 __asm__ volatile ("mfmsr %0":"=r" (msr));
493 __asm__ volatile ("mtmsr %0"::"r" (msr));
496 * Trying to execute the next instruction at a non-existing address
497 * should cause a machine check, resulting in reset
499 #ifdef CONFIG_SYS_RESET_ADDRESS
500 addr = CONFIG_SYS_RESET_ADDRESS;
503 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
504 * - sizeof (ulong) is usually a valid address. Better pick an address
505 * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
506 * "(ulong)-1" used to be a good choice for many systems...
508 addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
510 ((void (*)(void)) addr) ();
514 #else /* CONFIG_LWMON */
517 * On the LWMON board, the MCLR reset input of the PIC's on the board
518 * uses a 47K/1n RC combination which has a 47us time constant. The
519 * low signal on the HRESET pin of the CPU is only 512 clocks = 8 us
520 * and thus too short to reset the external hardware. So we use the
521 * watchdog to reset the board.
523 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
525 /* prevent triggering the watchdog */
526 disable_interrupts ();
528 /* make sure the watchdog is running */
529 reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
531 /* wait for watchdog reset */
538 #endif /* CONFIG_LWMON */
540 /* ------------------------------------------------------------------------- */
543 * Get timebase clock frequency (like cpu_clk in Hz)
545 * See sections 14.2 and 14.6 of the User's Manual
547 unsigned long get_tbclk (void)
549 uint immr = get_immr (0); /* Return full IMMR contents */
550 volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
551 ulong oscclk, factor, pll;
553 if (immap->im_clkrst.car_sccr & SCCR_TBS) {
554 return (gd->cpu_clk / 16);
557 pll = immap->im_clkrst.car_plprcr;
559 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
562 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
563 * factor is calculated as follows:
568 * factor = -----------------
571 * For older chips, it's just MF field of PLPRCR plus one.
573 if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
574 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
575 (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
577 factor = PLPRCR_val(MF)+1;
580 oscclk = gd->cpu_clk / factor;
582 if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
585 return (oscclk / 16);
588 /* ------------------------------------------------------------------------- */
590 #if defined(CONFIG_WATCHDOG)
591 void watchdog_reset (void)
593 int re_enable = disable_interrupts ();
595 reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
597 enable_interrupts ();
599 #endif /* CONFIG_WATCHDOG */
601 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON)
603 void reset_8xx_watchdog (volatile immap_t * immr)
605 # if defined(CONFIG_LWMON)
607 * The LWMON board uses a MAX6301 Watchdog
608 * with the trigger pin connected to port PA.7
610 * (The old board version used a MAX706TESA Watchdog, which
611 * had to be handled exactly the same.)
613 # define WATCHDOG_BIT 0x0100
614 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
615 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
616 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
618 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
619 # elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
621 * The KUP4 boards uses a TPS3705 Watchdog
622 * with the trigger pin connected to port PA.5
624 # define WATCHDOG_BIT 0x0400
625 immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */
626 immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */
627 immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */
629 immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */
632 * All other boards use the MPC8xx Internal Watchdog
634 immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
635 immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
636 # endif /* CONFIG_LWMON */
638 #endif /* CONFIG_WATCHDOG */
641 * Initializes on-chip ethernet controllers.
642 * to override, implement board_eth_init()
644 int cpu_eth_init(bd_t *bis)
646 #if defined(FEC_ENET)