1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
78 *-----------------------------------------------------------------------------*/
83 #include <asm/processor.h>
85 #include <asm/cache.h>
89 #include <ppc4xx_enet.h>
93 #include <asm/ppc4xx-intvec.h>
96 * Only compile for platform with AMCC EMAC ethernet controller and
97 * network support enabled.
98 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
100 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
102 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
103 #error "CONFIG_MII has to be defined!"
106 #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
107 #error "CONFIG_NET_MULTI has to be defined for NetConsole"
110 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
111 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
113 /* Ethernet Transmit and Receive Buffers */
115 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
116 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
118 #define ENET_MAX_MTU PKTSIZE
119 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
121 /*-----------------------------------------------------------------------------+
122 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
123 * Interrupt Controller).
124 *-----------------------------------------------------------------------------*/
125 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
126 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
127 #define EMAC_UIC_DEF UIC_ENET
128 #define EMAC_UIC_DEF1 UIC_ENET1
129 #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
133 #define BI_PHYMODE_NONE 0
134 #define BI_PHYMODE_ZMII 1
135 #define BI_PHYMODE_RGMII 2
136 #define BI_PHYMODE_GMII 3
137 #define BI_PHYMODE_RTBI 4
138 #define BI_PHYMODE_TBI 5
139 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
140 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
141 defined(CONFIG_405EX)
142 #define BI_PHYMODE_SMII 6
143 #define BI_PHYMODE_MII 7
144 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
145 #define BI_PHYMODE_RMII 8
149 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
150 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
151 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
152 defined(CONFIG_405EX)
153 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
156 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
157 #define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n))
160 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
161 #define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */
163 #define MAL_RX_CHAN_MUL 1
166 /*-----------------------------------------------------------------------------+
167 * Global variables. TX and RX descriptors and buffers.
168 *-----------------------------------------------------------------------------*/
170 static uint32_t mal_ier;
172 #if !defined(CONFIG_NET_MULTI)
173 struct eth_device *emac0_dev = NULL;
177 * Get count of EMAC devices (doesn't have to be the max. possible number
178 * supported by the cpu)
180 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
181 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
182 * 405EX/405EXr eval board, using the same binary.
184 #if defined(CONFIG_BOARD_EMAC_COUNT)
185 #define LAST_EMAC_NUM board_emac_count()
186 #else /* CONFIG_BOARD_EMAC_COUNT */
187 #if defined(CONFIG_HAS_ETH3)
188 #define LAST_EMAC_NUM 4
189 #elif defined(CONFIG_HAS_ETH2)
190 #define LAST_EMAC_NUM 3
191 #elif defined(CONFIG_HAS_ETH1)
192 #define LAST_EMAC_NUM 2
194 #define LAST_EMAC_NUM 1
196 #endif /* CONFIG_BOARD_EMAC_COUNT */
198 /* normal boards start with EMAC0 */
199 #if !defined(CONFIG_EMAC_NR_START)
200 #define CONFIG_EMAC_NR_START 0
203 #if defined(CONFIG_405EX) || defined(CONFIG_440EPX)
204 #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev)))
206 #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2))
209 #define MAL_RX_DESC_SIZE 2048
210 #define MAL_TX_DESC_SIZE 2048
211 #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
213 /*-----------------------------------------------------------------------------+
214 * Prototypes and externals.
215 *-----------------------------------------------------------------------------*/
216 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
218 int enetInt (struct eth_device *dev);
219 static void mal_err (struct eth_device *dev, unsigned long isr,
220 unsigned long uic, unsigned long maldef,
221 unsigned long mal_errr);
222 static void emac_err (struct eth_device *dev, unsigned long isr);
224 extern int phy_setup_aneg (char *devname, unsigned char addr);
225 extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
226 unsigned char reg, unsigned short *value);
227 extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
228 unsigned char reg, unsigned short value);
230 int board_emac_count(void);
232 static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p)
234 #if defined(CONFIG_440SPE) || \
235 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
236 defined(CONFIG_405EX)
240 val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
242 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
245 mfsdr(SDR0_ETH_CFG, val);
246 val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
247 mtsdr(SDR0_ETH_CFG, val);
251 static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
253 #if defined(CONFIG_440SPE) || \
254 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
255 defined(CONFIG_405EX)
259 val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
261 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
264 mfsdr(SDR0_ETH_CFG, val);
265 val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
266 mtsdr(SDR0_ETH_CFG, val);
270 /*-----------------------------------------------------------------------------+
272 | Disable MAL channel, and EMACn
273 +-----------------------------------------------------------------------------*/
274 static void ppc_4xx_eth_halt (struct eth_device *dev)
276 EMAC_4XX_HW_PST hw_p = dev->priv;
277 uint32_t failsafe = 10000;
280 out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
282 /* 1st reset MAL channel */
283 /* Note: writing a 0 to a channel has no effect */
284 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
285 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
287 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
289 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
292 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
293 udelay (1000); /* Delay 1 MS so as not to hammer the register */
299 /* provide clocks for EMAC internal loopback */
300 emac_loopback_enable(hw_p);
303 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
305 /* remove clocks for EMAC internal loopback */
306 emac_loopback_disable(hw_p);
308 #ifndef CONFIG_NETCONSOLE
309 hw_p->print_speed = 1; /* print speed message again next time */
312 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
313 /* don't bypass the TAHOE0/TAHOE1 cores for Linux */
314 mfsdr(SDR0_ETH_CFG, eth_cfg);
315 eth_cfg &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
316 mtsdr(SDR0_ETH_CFG, eth_cfg);
322 #if defined (CONFIG_440GX)
323 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
326 unsigned long zmiifer;
327 unsigned long rmiifer;
329 mfsdr(sdr_pfc1, pfc1);
330 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
337 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
338 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
339 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
340 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
341 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
342 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
343 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
344 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
347 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
348 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
349 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
350 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
351 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
352 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
353 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
354 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
357 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
358 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
359 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
360 bis->bi_phymode[1] = BI_PHYMODE_NONE;
361 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
362 bis->bi_phymode[3] = BI_PHYMODE_NONE;
365 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
366 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
367 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
368 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
369 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
370 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
371 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
372 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
375 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
376 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
377 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
378 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
379 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
380 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
381 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
382 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
385 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
386 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
387 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
388 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
389 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
390 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
394 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
396 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
397 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
398 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
399 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
403 /* Ensure we setup mdio for this devnum and ONLY this devnum */
404 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
406 out_be32((void *)ZMII_FER, zmiifer);
407 out_be32((void *)RGMII_FER, rmiifer);
411 #endif /* CONFIG_440_GX */
413 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
414 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
416 unsigned long zmiifer=0x0;
419 mfsdr(sdr_pfc1, pfc1);
420 pfc1 &= SDR0_PFC1_SELECT_MASK;
423 case SDR0_PFC1_SELECT_CONFIG_2:
425 out_be32((void *)ZMII_FER, 0x00);
426 out_be32((void *)RGMII_FER, 0x00000037);
427 bis->bi_phymode[0] = BI_PHYMODE_GMII;
428 bis->bi_phymode[1] = BI_PHYMODE_NONE;
430 case SDR0_PFC1_SELECT_CONFIG_4:
431 /* 2 x RGMII ports */
432 out_be32((void *)ZMII_FER, 0x00);
433 out_be32((void *)RGMII_FER, 0x00000055);
434 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
435 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
437 case SDR0_PFC1_SELECT_CONFIG_6:
439 out_be32((void *)ZMII_FER,
440 ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
441 ((ZMII_FER_SMII) << ZMII_FER_V(1)));
442 out_be32((void *)RGMII_FER, 0x00000000);
443 bis->bi_phymode[0] = BI_PHYMODE_SMII;
444 bis->bi_phymode[1] = BI_PHYMODE_SMII;
446 case SDR0_PFC1_SELECT_CONFIG_1_2:
447 /* only 1 x MII supported */
448 out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
449 out_be32((void *)RGMII_FER, 0x00000000);
450 bis->bi_phymode[0] = BI_PHYMODE_MII;
451 bis->bi_phymode[1] = BI_PHYMODE_NONE;
457 /* Ensure we setup mdio for this devnum and ONLY this devnum */
458 zmiifer = in_be32((void *)ZMII_FER);
459 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
460 out_be32((void *)ZMII_FER, zmiifer);
464 #endif /* CONFIG_440EPX */
466 #if defined(CONFIG_405EX)
467 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
472 * Right now only 2*RGMII is supported. Please extend when needed.
477 /* 2 x RGMII ports */
478 out_be32((void *)RGMII_FER, 0x00000055);
479 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
480 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
489 /* Ensure we setup mdio for this devnum and ONLY this devnum */
490 gmiifer = in_be32((void *)RGMII_FER);
491 gmiifer |= (1 << (19-devnum));
492 out_be32((void *)RGMII_FER, gmiifer);
496 #endif /* CONFIG_405EX */
498 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
499 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
502 u32 zmiifer; /* ZMII0_FER reg. */
503 u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */
504 u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */
511 #if defined(CONFIG_460EX)
518 * NOTE: 460GT has 2 RGMII bridge cores:
519 * emac0 ------ RGMII0_BASE
523 * emac2 ------ RGMII1_BASE
527 * 460EX has 1 RGMII bridge core:
528 * and RGMII1_BASE is disabled
529 * emac0 ------ RGMII0_BASE
535 * Right now only 2*RGMII is supported. Please extend when needed.
541 /* GMC0 EMAC4_0, ZMII Bridge */
542 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
543 bis->bi_phymode[0] = BI_PHYMODE_MII;
544 bis->bi_phymode[1] = BI_PHYMODE_NONE;
545 bis->bi_phymode[2] = BI_PHYMODE_NONE;
546 bis->bi_phymode[3] = BI_PHYMODE_NONE;
550 /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
551 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
552 zmiifer |= ZMII_FER_MII << ZMII_FER_V(2);
553 bis->bi_phymode[0] = BI_PHYMODE_MII;
554 bis->bi_phymode[1] = BI_PHYMODE_NONE;
555 bis->bi_phymode[2] = BI_PHYMODE_MII;
556 bis->bi_phymode[3] = BI_PHYMODE_NONE;
560 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
561 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
562 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
563 bis->bi_phymode[0] = BI_PHYMODE_RMII;
564 bis->bi_phymode[1] = BI_PHYMODE_RMII;
565 bis->bi_phymode[2] = BI_PHYMODE_NONE;
566 bis->bi_phymode[3] = BI_PHYMODE_NONE;
570 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
572 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
573 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
574 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
575 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
576 bis->bi_phymode[0] = BI_PHYMODE_RMII;
577 bis->bi_phymode[1] = BI_PHYMODE_RMII;
578 bis->bi_phymode[2] = BI_PHYMODE_RMII;
579 bis->bi_phymode[3] = BI_PHYMODE_RMII;
583 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
584 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
585 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
586 bis->bi_phymode[0] = BI_PHYMODE_SMII;
587 bis->bi_phymode[1] = BI_PHYMODE_SMII;
588 bis->bi_phymode[2] = BI_PHYMODE_NONE;
589 bis->bi_phymode[3] = BI_PHYMODE_NONE;
593 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
595 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
596 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
597 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
598 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
599 bis->bi_phymode[0] = BI_PHYMODE_SMII;
600 bis->bi_phymode[1] = BI_PHYMODE_SMII;
601 bis->bi_phymode[2] = BI_PHYMODE_SMII;
602 bis->bi_phymode[3] = BI_PHYMODE_SMII;
605 /* This is the default mode that we want for board bringup - Maple */
607 /* GMC0 EMAC4_0, RGMII Bridge 0 */
608 rmiifer |= RGMII_FER_MDIO(0);
611 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
612 bis->bi_phymode[0] = BI_PHYMODE_GMII;
613 bis->bi_phymode[1] = BI_PHYMODE_NONE;
614 bis->bi_phymode[2] = BI_PHYMODE_NONE;
615 bis->bi_phymode[3] = BI_PHYMODE_NONE;
617 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */
618 bis->bi_phymode[0] = BI_PHYMODE_NONE;
619 bis->bi_phymode[1] = BI_PHYMODE_GMII;
620 bis->bi_phymode[2] = BI_PHYMODE_NONE;
621 bis->bi_phymode[3] = BI_PHYMODE_NONE;
626 /* GMC0 EMAC4_0, RGMII Bridge 0 */
627 /* GMC1 EMAC4_2, RGMII Bridge 1 */
628 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
629 rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */
630 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
631 rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */
633 bis->bi_phymode[0] = BI_PHYMODE_GMII;
634 bis->bi_phymode[1] = BI_PHYMODE_NONE;
635 bis->bi_phymode[2] = BI_PHYMODE_GMII;
636 bis->bi_phymode[3] = BI_PHYMODE_NONE;
639 /* 2 RGMII - 460EX */
640 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
641 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
642 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
643 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
645 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
646 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
647 bis->bi_phymode[2] = BI_PHYMODE_NONE;
648 bis->bi_phymode[3] = BI_PHYMODE_NONE;
651 /* 4 RGMII - 460GT */
652 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
653 /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
654 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
655 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
656 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2);
657 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3);
658 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
659 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
660 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
661 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
667 /* Set EMAC for MDIO */
668 mfsdr(SDR0_ETH_CFG, eth_cfg);
669 eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
670 mtsdr(SDR0_ETH_CFG, eth_cfg);
672 out_be32((void *)RGMII_FER, rmiifer);
673 #if defined(CONFIG_460GT)
674 out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1);
677 /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
678 mfsdr(SDR0_ETH_CFG, eth_cfg);
679 eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
680 mtsdr(SDR0_ETH_CFG, eth_cfg);
684 #endif /* CONFIG_460EX || CONFIG_460GT */
686 static inline void *malloc_aligned(u32 size, u32 align)
688 return (void *)(((u32)malloc(size + align) + align - 1) &
692 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
695 unsigned long reg = 0;
698 unsigned long duplex;
699 unsigned long failsafe;
701 unsigned short devnum;
702 unsigned short reg_short;
703 #if defined(CONFIG_440GX) || \
704 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
705 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
706 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
707 defined(CONFIG_405EX)
709 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
710 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
711 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
712 defined(CONFIG_405EX)
718 #ifdef CONFIG_4xx_DCACHE
719 static u32 last_used_ea = 0;
722 EMAC_4XX_HW_PST hw_p = dev->priv;
724 /* before doing anything, figure out if we have a MAC address */
726 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
727 printf("ERROR: ethaddr not set!\n");
731 #if defined(CONFIG_440GX) || \
732 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
733 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
734 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
735 defined(CONFIG_405EX)
736 /* Need to get the OPB frequency so we can access the PHY */
737 get_sys_info (&sysinfo);
741 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
743 devnum = hw_p->devnum;
748 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
749 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
750 * is possible that new packets (without relationship with
751 * current transfer) have got the time to arrived before
752 * netloop calls eth_halt
754 printf ("About preceeding transfer (eth%d):\n"
755 "- Sent packet number %d\n"
756 "- Received packet number %d\n"
757 "- Handled packet number %d\n",
760 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
762 hw_p->stats.pkts_tx = 0;
763 hw_p->stats.pkts_rx = 0;
764 hw_p->stats.pkts_handled = 0;
765 hw_p->print_speed = 1; /* print speed message again next time */
768 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
769 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
771 hw_p->rx_slot = 0; /* MAL Receive Slot */
772 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
773 hw_p->rx_u_index = 0; /* Receive User Queue Index */
775 hw_p->tx_slot = 0; /* MAL Transmit Slot */
776 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
777 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
779 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
781 /* NOTE: 440GX spec states that mode is mutually exclusive */
782 /* NOTE: Therefore, disable all other EMACS, since we handle */
783 /* NOTE: only one emac at a time */
785 out_be32((void *)ZMII_FER, 0);
788 #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
789 out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
790 #elif defined(CONFIG_440GX) || \
791 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
792 defined(CONFIG_460EX) || defined(CONFIG_460GT)
793 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
796 out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
797 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
798 #if defined(CONFIG_405EX)
799 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
804 /* provide clocks for EMAC internal loopback */
805 emac_loopback_enable(hw_p);
808 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
810 /* remove clocks for EMAC internal loopback */
811 emac_loopback_disable(hw_p);
814 while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
819 printf("\nProblem resetting EMAC!\n");
821 #if defined(CONFIG_440GX) || \
822 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
823 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
824 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
825 defined(CONFIG_405EX)
826 /* Whack the M1 register */
828 mode_reg &= ~0x00000038;
829 if (sysinfo.freqOPB <= 50000000);
830 else if (sysinfo.freqOPB <= 66666667)
831 mode_reg |= EMAC_M1_OBCI_66;
832 else if (sysinfo.freqOPB <= 83333333)
833 mode_reg |= EMAC_M1_OBCI_83;
834 else if (sysinfo.freqOPB <= 100000000)
835 mode_reg |= EMAC_M1_OBCI_100;
837 mode_reg |= EMAC_M1_OBCI_GT100;
839 out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
840 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
842 /* wait for PHY to complete auto negotiation */
844 #ifndef CONFIG_CS8952_PHY
847 reg = CONFIG_PHY_ADDR;
849 #if defined (CONFIG_PHY1_ADDR)
851 reg = CONFIG_PHY1_ADDR;
854 #if defined (CONFIG_PHY2_ADDR)
856 reg = CONFIG_PHY2_ADDR;
859 #if defined (CONFIG_PHY3_ADDR)
861 reg = CONFIG_PHY3_ADDR;
865 reg = CONFIG_PHY_ADDR;
869 bis->bi_phynum[devnum] = reg;
871 #if defined(CONFIG_PHY_RESET)
873 * Reset the phy, only if its the first time through
874 * otherwise, just check the speeds & feeds
876 if (hw_p->first_init == 0) {
877 #if defined(CONFIG_M88E1111_PHY)
878 miiphy_write (dev->name, reg, 0x14, 0x0ce3);
879 miiphy_write (dev->name, reg, 0x18, 0x4101);
880 miiphy_write (dev->name, reg, 0x09, 0x0e00);
881 miiphy_write (dev->name, reg, 0x04, 0x01e1);
883 miiphy_reset (dev->name, reg);
885 #if defined(CONFIG_440GX) || \
886 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
887 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
888 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
889 defined(CONFIG_405EX)
891 #if defined(CONFIG_CIS8201_PHY)
893 * Cicada 8201 PHY needs to have an extended register whacked
896 if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
897 #if defined(CONFIG_CIS8201_SHORT_ETCH)
898 miiphy_write (dev->name, reg, 23, 0x1300);
900 miiphy_write (dev->name, reg, 23, 0x1000);
903 * Vitesse VSC8201/Cicada CIS8201 errata:
904 * Interoperability problem with Intel 82547EI phys
905 * This work around (provided by Vitesse) changes
906 * the default timer convergence from 8ms to 12ms
908 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
909 miiphy_write (dev->name, reg, 0x08, 0x0200);
910 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
911 miiphy_write (dev->name, reg, 0x02, 0x0004);
912 miiphy_write (dev->name, reg, 0x01, 0x0671);
913 miiphy_write (dev->name, reg, 0x00, 0x8fae);
914 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
915 miiphy_write (dev->name, reg, 0x08, 0x0000);
916 miiphy_write (dev->name, reg, 0x1f, 0x0000);
917 /* end Vitesse/Cicada errata */
921 #if defined(CONFIG_ET1011C_PHY)
923 * Agere ET1011c PHY needs to have an extended register whacked
926 if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
927 miiphy_read (dev->name, reg, 0x16, ®_short);
929 reg_short |= 0x6; /* RGMII DLL Delay*/
930 miiphy_write (dev->name, reg, 0x16, reg_short);
932 miiphy_read (dev->name, reg, 0x17, ®_short);
933 reg_short &= ~(0x40);
934 miiphy_write (dev->name, reg, 0x17, reg_short);
936 miiphy_write(dev->name, reg, 0x1c, 0x74f0);
941 /* Start/Restart autonegotiation */
942 phy_setup_aneg (dev->name, reg);
945 #endif /* defined(CONFIG_PHY_RESET) */
947 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
950 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
952 if ((reg_short & PHY_BMSR_AUTN_ABLE)
953 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
954 puts ("Waiting for PHY auto negotiation to complete");
956 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
960 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
961 puts (" TIMEOUT !\n");
965 if ((i++ % 1000) == 0) {
968 udelay (1000); /* 1 ms */
969 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
973 udelay (500000); /* another 500 ms (results in faster booting) */
975 #endif /* #ifndef CONFIG_CS8952_PHY */
977 speed = miiphy_speed (dev->name, reg);
978 duplex = miiphy_duplex (dev->name, reg);
980 if (hw_p->print_speed) {
981 hw_p->print_speed = 0;
982 printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
983 (int) speed, (duplex == HALF) ? "HALF" : "FULL",
987 #if defined(CONFIG_440) && \
988 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
989 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
990 !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
991 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
994 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
996 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
1001 /* Set ZMII/RGMII speed according to the phy link speed */
1002 reg = in_be32((void *)ZMII_SSR);
1003 if ( (speed == 100) || (speed == 1000) )
1004 out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
1006 out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
1008 if ((devnum == 2) || (devnum == 3)) {
1010 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
1011 else if (speed == 100)
1012 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
1013 else if (speed == 10)
1014 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
1016 printf("Error in RGMII Speed\n");
1019 out_be32((void *)RGMII_SSR, reg);
1021 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
1023 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1024 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1025 defined(CONFIG_405EX)
1027 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
1028 else if (speed == 100)
1029 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
1030 else if (speed == 10)
1031 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
1033 printf("Error in RGMII Speed\n");
1036 out_be32((void *)RGMII_SSR, reg);
1037 #if defined(CONFIG_460GT)
1038 if ((devnum == 2) || (devnum == 3))
1039 out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg);
1043 /* set the Mal configuration reg */
1044 #if defined(CONFIG_440GX) || \
1045 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1046 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1047 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1048 defined(CONFIG_405EX)
1049 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
1050 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
1052 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
1053 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
1054 if (get_pvr() == PVR_440GP_RB) {
1055 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
1060 * Malloc MAL buffer desciptors, make sure they are
1061 * aligned on cache line boundary size
1062 * (401/403/IOP480 = 16, 405 = 32)
1063 * and doesn't cross cache block boundaries.
1065 if (hw_p->first_init == 0) {
1066 debug("*** Allocating descriptor memory ***\n");
1068 bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
1070 printf("%s: Error allocating MAL descriptor buffers!\n");
1074 #ifdef CONFIG_4xx_DCACHE
1075 flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
1077 bd_uncached = bis->bi_memsize;
1079 bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
1081 last_used_ea = bd_uncached;
1082 program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
1083 TLB_WORD2_I_ENABLE);
1085 bd_uncached = bd_cached;
1087 hw_p->tx_phys = bd_cached;
1088 hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
1089 hw_p->tx = (mal_desc_t *)(bd_uncached);
1090 hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
1091 debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx);
1094 for (i = 0; i < NUM_TX_BUFF; i++) {
1095 hw_p->tx[i].ctrl = 0;
1096 hw_p->tx[i].data_len = 0;
1097 if (hw_p->first_init == 0)
1098 hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
1100 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
1101 if ((NUM_TX_BUFF - 1) == i)
1102 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
1103 hw_p->tx_run[i] = -1;
1104 debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr);
1107 for (i = 0; i < NUM_RX_BUFF; i++) {
1108 hw_p->rx[i].ctrl = 0;
1109 hw_p->rx[i].data_len = 0;
1110 hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
1111 if ((NUM_RX_BUFF - 1) == i)
1112 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
1113 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
1114 hw_p->rx_ready[i] = -1;
1115 debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr);
1120 reg |= dev->enetaddr[0]; /* set high address */
1122 reg |= dev->enetaddr[1];
1124 out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg);
1127 reg |= dev->enetaddr[2]; /* set low address */
1129 reg |= dev->enetaddr[3];
1131 reg |= dev->enetaddr[4];
1133 reg |= dev->enetaddr[5];
1135 out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg);
1139 /* setup MAL tx & rx channel pointers */
1140 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
1141 mtdcr (maltxctp2r, hw_p->tx_phys);
1143 mtdcr (maltxctp1r, hw_p->tx_phys);
1145 #if defined(CONFIG_440)
1146 mtdcr (maltxbattr, 0x0);
1147 mtdcr (malrxbattr, 0x0);
1150 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
1151 mtdcr (malrxctp8r, hw_p->rx_phys);
1152 /* set RX buffer size */
1153 mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16);
1155 mtdcr (malrxctp1r, hw_p->rx_phys);
1156 /* set RX buffer size */
1157 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
1160 #if defined (CONFIG_440GX)
1162 /* setup MAL tx & rx channel pointers */
1163 mtdcr (maltxbattr, 0x0);
1164 mtdcr (malrxbattr, 0x0);
1165 mtdcr (maltxctp2r, hw_p->tx_phys);
1166 mtdcr (malrxctp2r, hw_p->rx_phys);
1167 /* set RX buffer size */
1168 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
1171 /* setup MAL tx & rx channel pointers */
1172 mtdcr (maltxbattr, 0x0);
1173 mtdcr (maltxctp3r, hw_p->tx_phys);
1174 mtdcr (malrxbattr, 0x0);
1175 mtdcr (malrxctp3r, hw_p->rx_phys);
1176 /* set RX buffer size */
1177 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
1179 #endif /* CONFIG_440GX */
1180 #if defined (CONFIG_460GT)
1182 /* setup MAL tx & rx channel pointers */
1183 mtdcr (maltxbattr, 0x0);
1184 mtdcr (malrxbattr, 0x0);
1185 mtdcr (maltxctp2r, hw_p->tx_phys);
1186 mtdcr (malrxctp16r, hw_p->rx_phys);
1187 /* set RX buffer size */
1188 mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16);
1191 /* setup MAL tx & rx channel pointers */
1192 mtdcr (maltxbattr, 0x0);
1193 mtdcr (malrxbattr, 0x0);
1194 mtdcr (maltxctp3r, hw_p->tx_phys);
1195 mtdcr (malrxctp24r, hw_p->rx_phys);
1196 /* set RX buffer size */
1197 mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16);
1199 #endif /* CONFIG_460GT */
1202 /* setup MAL tx & rx channel pointers */
1203 #if defined(CONFIG_440)
1204 mtdcr (maltxbattr, 0x0);
1205 mtdcr (malrxbattr, 0x0);
1207 mtdcr (maltxctp0r, hw_p->tx_phys);
1208 mtdcr (malrxctp0r, hw_p->rx_phys);
1209 /* set RX buffer size */
1210 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
1214 /* Enable MAL transmit and receive channels */
1215 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
1216 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
1218 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
1220 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
1222 /* set transmit enable & receive enable */
1223 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
1225 mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
1227 /* set rx-/tx-fifo size */
1228 mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
1231 if (speed == _1000BASET) {
1232 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1233 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1236 mfsdr (sdr_pfc1, pfc1);
1237 pfc1 |= SDR0_PFC1_EM_1000;
1238 mtsdr (sdr_pfc1, pfc1);
1240 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
1241 } else if (speed == _100BASET)
1242 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
1244 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
1246 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
1248 out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
1250 /* Enable broadcast and indvidual address */
1251 /* TBS: enabling runts as some misbehaved nics will send runts */
1252 out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
1254 /* we probably need to set the tx mode1 reg? maybe at tx time */
1256 /* set transmit request threshold register */
1257 out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
1259 /* set receive low/high water mark register */
1260 #if defined(CONFIG_440)
1261 /* 440s has a 64 byte burst length */
1262 out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
1264 /* 405s have a 16 byte burst length */
1265 out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
1266 #endif /* defined(CONFIG_440) */
1267 out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
1269 /* Set fifo limit entry in tx mode 0 */
1270 out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
1272 out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
1275 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
1276 if (speed == _100BASET)
1277 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
1279 out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
1280 out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
1282 if (hw_p->first_init == 0) {
1284 * Connect interrupt service routines
1286 irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
1287 (interrupt_handler_t *) enetInt, dev);
1290 mtmsr (msr); /* enable interrupts again */
1293 hw_p->first_init = 1;
1299 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
1302 struct enet_frame *ef_ptr;
1303 ulong time_start, time_now;
1304 unsigned long temp_txm0;
1305 EMAC_4XX_HW_PST hw_p = dev->priv;
1307 ef_ptr = (struct enet_frame *) ptr;
1309 /*-----------------------------------------------------------------------+
1310 * Copy in our address into the frame.
1311 *-----------------------------------------------------------------------*/
1312 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
1314 /*-----------------------------------------------------------------------+
1315 * If frame is too long or too short, modify length.
1316 *-----------------------------------------------------------------------*/
1317 /* TBS: where does the fragment go???? */
1318 if (len > ENET_MAX_MTU)
1321 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
1322 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
1323 flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
1325 /*-----------------------------------------------------------------------+
1326 * set TX Buffer busy, and send it
1327 *-----------------------------------------------------------------------*/
1328 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
1329 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
1330 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
1331 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
1332 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
1334 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
1335 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
1339 out_be32((void *)EMAC_TXM0 + hw_p->hw_addr,
1340 in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
1341 #ifdef INFO_4XX_ENET
1342 hw_p->stats.pkts_tx++;
1345 /*-----------------------------------------------------------------------+
1346 * poll unitl the packet is sent and then make sure it is OK
1347 *-----------------------------------------------------------------------*/
1348 time_start = get_timer (0);
1350 temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr);
1351 /* loop until either TINT turns on or 3 seconds elapse */
1352 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
1353 /* transmit is done, so now check for errors
1354 * If there is an error, an interrupt should
1355 * happen when we return
1357 time_now = get_timer (0);
1358 if ((time_now - time_start) > 3000) {
1368 #if defined (CONFIG_440) || defined(CONFIG_405EX)
1370 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1372 * Hack: On 440SP all enet irq sources are located on UIC1
1373 * Needs some cleanup. --sr
1375 #define UIC0MSR uic1msr
1376 #define UIC0SR uic1sr
1377 #define UIC1MSR uic1msr
1378 #define UIC1SR uic1sr
1379 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
1381 * Hack: On 460EX/GT all enet irq sources are located on UIC2
1382 * Needs some cleanup. --ag
1384 #define UIC0MSR uic2msr
1385 #define UIC0SR uic2sr
1386 #define UIC1MSR uic2msr
1387 #define UIC1SR uic2sr
1389 #define UIC0MSR uic0msr
1390 #define UIC0SR uic0sr
1391 #define UIC1MSR uic1msr
1392 #define UIC1SR uic1sr
1395 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1396 defined(CONFIG_405EX)
1397 #define UICMSR_ETHX uic0msr
1398 #define UICSR_ETHX uic0sr
1399 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
1400 #define UICMSR_ETHX uic2msr
1401 #define UICSR_ETHX uic2sr
1403 #define UICMSR_ETHX uic1msr
1404 #define UICSR_ETHX uic1sr
1407 int enetInt (struct eth_device *dev)
1410 int rc = -1; /* default to not us */
1411 unsigned long mal_isr;
1412 unsigned long emac_isr = 0;
1413 unsigned long mal_rx_eob;
1414 unsigned long my_uic0msr, my_uic1msr;
1415 unsigned long my_uicmsr_ethx;
1417 #if defined(CONFIG_440GX)
1418 unsigned long my_uic2msr;
1420 EMAC_4XX_HW_PST hw_p;
1423 * Because the mal is generic, we need to get the current
1426 #if defined(CONFIG_NET_MULTI)
1427 dev = eth_get_dev();
1434 /* enter loop that stays in interrupt code until nothing to service */
1438 my_uic0msr = mfdcr (UIC0MSR);
1439 my_uic1msr = mfdcr (UIC1MSR);
1440 #if defined(CONFIG_440GX)
1441 my_uic2msr = mfdcr (uic2msr);
1443 my_uicmsr_ethx = mfdcr (UICMSR_ETHX);
1445 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
1446 && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))
1447 && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) {
1451 #if defined (CONFIG_440GX)
1452 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
1453 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
1458 /* get and clear controller status interrupts */
1459 /* look at Mal and EMAC interrupts */
1460 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
1461 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1462 /* we have a MAL interrupt */
1463 mal_isr = mfdcr (malesr);
1464 /* look for mal error */
1465 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
1466 mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR);
1472 /* port by port dispatch of emac interrupts */
1473 if (hw_p->devnum == 0) {
1474 if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */
1475 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1476 if ((hw_p->emac_ier & emac_isr) != 0) {
1477 emac_err (dev, emac_isr);
1482 if ((hw_p->emac_ier & emac_isr)
1483 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1484 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1485 mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1486 mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */
1487 return (rc); /* we had errors so get out */
1491 #if !defined(CONFIG_440SP)
1492 if (hw_p->devnum == 1) {
1493 if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */
1494 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1495 if ((hw_p->emac_ier & emac_isr) != 0) {
1496 emac_err (dev, emac_isr);
1501 if ((hw_p->emac_ier & emac_isr)
1502 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1503 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1504 mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1505 mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */
1506 return (rc); /* we had errors so get out */
1509 #if defined (CONFIG_440GX)
1510 if (hw_p->devnum == 2) {
1511 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
1512 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1513 if ((hw_p->emac_ier & emac_isr) != 0) {
1514 emac_err (dev, emac_isr);
1519 if ((hw_p->emac_ier & emac_isr)
1520 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1521 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1522 mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1523 mtdcr (uic2sr, UIC_ETH2);
1524 return (rc); /* we had errors so get out */
1528 if (hw_p->devnum == 3) {
1529 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
1530 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1531 if ((hw_p->emac_ier & emac_isr) != 0) {
1532 emac_err (dev, emac_isr);
1537 if ((hw_p->emac_ier & emac_isr)
1538 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1539 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1540 mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1541 mtdcr (uic2sr, UIC_ETH3);
1542 return (rc); /* we had errors so get out */
1545 #endif /* CONFIG_440GX */
1546 #endif /* !CONFIG_440SP */
1548 /* handle MAX TX EOB interrupt from a tx */
1549 if (my_uic0msr & UIC_MTE) {
1550 mal_rx_eob = mfdcr (maltxeobisr);
1551 mtdcr (maltxeobisr, mal_rx_eob);
1552 mtdcr (UIC0SR, UIC_MTE);
1554 /* handle MAL RX EOB interupt from a receive */
1555 /* check for EOB on valid channels */
1556 if (my_uic0msr & UIC_MRE) {
1557 mal_rx_eob = mfdcr (malrxeobisr);
1559 (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)))
1560 != 0) { /* call emac routine for channel x */
1562 mtdcr(malrxeobisr, mal_rx_eob); */
1563 enet_rcv (dev, emac_isr);
1564 /* indicate that we serviced an interrupt */
1570 mtdcr (UIC0SR, UIC_MRE); /* Clear */
1571 mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1572 switch (hw_p->devnum) {
1574 mtdcr (UICSR_ETHX, UIC_ETH0);
1577 mtdcr (UICSR_ETHX, UIC_ETH1);
1579 #if defined (CONFIG_440GX)
1581 mtdcr (uic2sr, UIC_ETH2);
1584 mtdcr (uic2sr, UIC_ETH3);
1586 #endif /* CONFIG_440GX */
1595 #else /* CONFIG_440 */
1597 int enetInt (struct eth_device *dev)
1600 int rc = -1; /* default to not us */
1601 unsigned long mal_isr;
1602 unsigned long emac_isr = 0;
1603 unsigned long mal_rx_eob;
1604 unsigned long my_uicmsr;
1606 EMAC_4XX_HW_PST hw_p;
1609 * Because the mal is generic, we need to get the current
1612 #if defined(CONFIG_NET_MULTI)
1613 dev = eth_get_dev();
1620 /* enter loop that stays in interrupt code until nothing to service */
1624 my_uicmsr = mfdcr (uicmsr);
1626 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
1629 /* get and clear controller status interrupts */
1630 /* look at Mal and EMAC interrupts */
1631 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
1632 mal_isr = mfdcr (malesr);
1633 /* look for mal error */
1634 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
1635 mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
1641 /* port by port dispatch of emac interrupts */
1643 if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
1644 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1645 if ((hw_p->emac_ier & emac_isr) != 0) {
1646 emac_err (dev, emac_isr);
1651 if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
1652 mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
1653 return (rc); /* we had errors so get out */
1656 /* handle MAX TX EOB interrupt from a tx */
1657 if (my_uicmsr & UIC_MAL_TXEOB) {
1658 mal_rx_eob = mfdcr (maltxeobisr);
1659 mtdcr (maltxeobisr, mal_rx_eob);
1660 mtdcr (uicsr, UIC_MAL_TXEOB);
1662 /* handle MAL RX EOB interupt from a receive */
1663 /* check for EOB on valid channels */
1664 if (my_uicmsr & UIC_MAL_RXEOB)
1666 mal_rx_eob = mfdcr (malrxeobisr);
1667 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1669 mtdcr(malrxeobisr, mal_rx_eob); */
1670 enet_rcv (dev, emac_isr);
1671 /* indicate that we serviced an interrupt */
1676 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
1677 #if defined(CONFIG_405EZ)
1678 mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
1679 #endif /* defined(CONFIG_405EZ) */
1686 #endif /* CONFIG_440 */
1688 /*-----------------------------------------------------------------------------+
1690 *-----------------------------------------------------------------------------*/
1691 static void mal_err (struct eth_device *dev, unsigned long isr,
1692 unsigned long uic, unsigned long maldef,
1693 unsigned long mal_errr)
1695 EMAC_4XX_HW_PST hw_p = dev->priv;
1697 mtdcr (malesr, isr); /* clear interrupt */
1699 /* clear DE interrupt */
1700 mtdcr (maltxdeir, 0xC0000000);
1701 mtdcr (malrxdeir, 0x80000000);
1703 #ifdef INFO_4XX_ENET
1704 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
1707 eth_init (hw_p->bis); /* start again... */
1710 /*-----------------------------------------------------------------------------+
1711 * EMAC Error Routine
1712 *-----------------------------------------------------------------------------*/
1713 static void emac_err (struct eth_device *dev, unsigned long isr)
1715 EMAC_4XX_HW_PST hw_p = dev->priv;
1717 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1718 out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr);
1721 /*-----------------------------------------------------------------------------+
1722 * enet_rcv() handles the ethernet receive data
1723 *-----------------------------------------------------------------------------*/
1724 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1726 struct enet_frame *ef_ptr;
1727 unsigned long data_len;
1728 unsigned long rx_eob_isr;
1729 EMAC_4XX_HW_PST hw_p = dev->priv;
1735 rx_eob_isr = mfdcr (malrxeobisr);
1736 if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) {
1738 mtdcr (malrxeobisr, rx_eob_isr);
1741 while (1) { /* do all */
1744 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1745 || (loop_count >= NUM_RX_BUFF))
1750 data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */
1752 if (data_len > ENET_MAX_MTU) /* Check len */
1755 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1757 hw_p->stats.rx_err_log[hw_p->
1760 hw_p->rx_err_index++;
1761 if (hw_p->rx_err_index ==
1763 hw_p->rx_err_index =
1766 } /* data_len < max mtu */
1768 if (!data_len) { /* no data */
1769 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1771 hw_p->stats.data_len_err++; /* Error at Rx */
1776 /* Check if user has already eaten buffer */
1777 /* if not => ERROR */
1778 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1779 if (hw_p->is_receiving)
1780 printf ("ERROR : Receive buffers are full!\n");
1783 hw_p->stats.rx_frames++;
1784 hw_p->stats.rx += data_len;
1785 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1787 #ifdef INFO_4XX_ENET
1788 hw_p->stats.pkts_rx++;
1793 hw_p->rx_ready[hw_p->rx_i_index] = i;
1795 if (NUM_RX_BUFF == hw_p->rx_i_index)
1796 hw_p->rx_i_index = 0;
1799 if (NUM_RX_BUFF == hw_p->rx_slot)
1803 * free receive buffer only when
1804 * buffer has been handled (eth_rx)
1805 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1809 } /* if EMACK_RXCHL */
1813 static int ppc_4xx_eth_rx (struct eth_device *dev)
1818 EMAC_4XX_HW_PST hw_p = dev->priv;
1820 hw_p->is_receiving = 1; /* tell driver */
1824 * use ring buffer and
1825 * get index from rx buffer desciptor queue
1827 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1828 if (user_index == -1) {
1830 break; /* nothing received - leave for() loop */
1834 mtmsr (msr & ~(MSR_EE));
1836 length = hw_p->rx[user_index].data_len & 0x0fff;
1838 /* Pass the packet up to the protocol layers. */
1839 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1840 /* NetReceive(NetRxPackets[i], length); */
1841 invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
1842 (u32)hw_p->rx[user_index].data_ptr +
1844 NetReceive (NetRxPackets[user_index], length - 4);
1845 /* Free Recv Buffer */
1846 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1847 /* Free rx buffer descriptor queue */
1848 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1850 if (NUM_RX_BUFF == hw_p->rx_u_index)
1851 hw_p->rx_u_index = 0;
1853 #ifdef INFO_4XX_ENET
1854 hw_p->stats.pkts_handled++;
1857 mtmsr (msr); /* Enable IRQ's */
1860 hw_p->is_receiving = 0; /* tell driver */
1865 int ppc_4xx_eth_initialize (bd_t * bis)
1867 static int virgin = 0;
1868 struct eth_device *dev;
1870 EMAC_4XX_HW_PST hw = NULL;
1871 u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
1874 #if defined(CONFIG_440GX)
1877 mfsdr (sdr_pfc1, pfc1);
1878 pfc1 &= ~(0x01e00000);
1880 mtsdr (sdr_pfc1, pfc1);
1883 /* first clear all mac-addresses */
1884 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
1885 memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
1887 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1889 default: /* fall through */
1891 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1892 bis->bi_enetaddr, 6);
1893 hw_addr[eth_num] = 0x0;
1895 #ifdef CONFIG_HAS_ETH1
1897 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1898 bis->bi_enet1addr, 6);
1899 hw_addr[eth_num] = 0x100;
1902 #ifdef CONFIG_HAS_ETH2
1904 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1905 bis->bi_enet2addr, 6);
1906 #if defined(CONFIG_460GT)
1907 hw_addr[eth_num] = 0x300;
1909 hw_addr[eth_num] = 0x400;
1913 #ifdef CONFIG_HAS_ETH3
1915 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1916 bis->bi_enet3addr, 6);
1917 #if defined(CONFIG_460GT)
1918 hw_addr[eth_num] = 0x400;
1920 hw_addr[eth_num] = 0x600;
1927 /* set phy num and mode */
1928 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1929 bis->bi_phymode[0] = 0;
1931 #if defined(CONFIG_PHY1_ADDR)
1932 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1933 bis->bi_phymode[1] = 0;
1935 #if defined(CONFIG_440GX)
1936 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1937 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1938 bis->bi_phymode[2] = 2;
1939 bis->bi_phymode[3] = 2;
1942 #if defined(CONFIG_440GX) || \
1943 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1944 defined(CONFIG_405EX)
1945 ppc_4xx_eth_setup_bridge(0, bis);
1948 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1950 * See if we can actually bring up the interface,
1951 * otherwise, skip it
1953 if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
1954 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1958 /* Allocate device structure */
1959 dev = (struct eth_device *) malloc (sizeof (*dev));
1961 printf ("ppc_4xx_eth_initialize: "
1962 "Cannot allocate eth_device %d\n", eth_num);
1965 memset(dev, 0, sizeof(*dev));
1967 /* Allocate our private use data */
1968 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
1970 printf ("ppc_4xx_eth_initialize: "
1971 "Cannot allocate private hw data for eth_device %d",
1976 memset(hw, 0, sizeof(*hw));
1978 hw->hw_addr = hw_addr[eth_num];
1979 memcpy (dev->enetaddr, ethaddr[eth_num], 6);
1980 hw->devnum = eth_num;
1981 hw->print_speed = 1;
1983 sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
1984 dev->priv = (void *) hw;
1985 dev->init = ppc_4xx_eth_init;
1986 dev->halt = ppc_4xx_eth_halt;
1987 dev->send = ppc_4xx_eth_send;
1988 dev->recv = ppc_4xx_eth_rx;
1991 /* set the MAL IER ??? names may change with new spec ??? */
1992 #if defined(CONFIG_440SPE) || \
1993 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1994 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1995 defined(CONFIG_405EX)
1997 MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
1998 MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
2001 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
2002 MAL_IER_OPBE | MAL_IER_PLBE;
2004 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
2005 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
2006 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
2007 mtdcr (malier, mal_ier);
2009 /* install MAL interrupt handler */
2010 irq_install_handler (VECNUM_MS,
2011 (interrupt_handler_t *) enetInt,
2013 irq_install_handler (VECNUM_MTE,
2014 (interrupt_handler_t *) enetInt,
2016 irq_install_handler (VECNUM_MRE,
2017 (interrupt_handler_t *) enetInt,
2019 irq_install_handler (VECNUM_TXDE,
2020 (interrupt_handler_t *) enetInt,
2022 irq_install_handler (VECNUM_RXDE,
2023 (interrupt_handler_t *) enetInt,
2028 #if defined(CONFIG_NET_MULTI)
2034 #if defined(CONFIG_NET_MULTI)
2035 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
2036 miiphy_register (dev->name,
2037 emac4xx_miiphy_read, emac4xx_miiphy_write);
2040 } /* end for each supported device */
2045 #if !defined(CONFIG_NET_MULTI)
2046 void eth_halt (void) {
2048 ppc_4xx_eth_halt(emac0_dev);
2054 int eth_init (bd_t *bis)
2056 ppc_4xx_eth_initialize(bis);
2058 return ppc_4xx_eth_init(emac0_dev, bis);
2060 printf("ERROR: ethaddr not set!\n");
2065 int eth_send(volatile void *packet, int length)
2067 return (ppc_4xx_eth_send(emac0_dev, packet, length));
2072 return (ppc_4xx_eth_rx(emac0_dev));
2075 int emac4xx_miiphy_initialize (bd_t * bis)
2077 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
2078 miiphy_register ("ppc_4xx_eth0",
2079 emac4xx_miiphy_read, emac4xx_miiphy_write);
2084 #endif /* !defined(CONFIG_NET_MULTI) */