2 * (C) Copyright 2000-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <ppc4xx_enet.h>
27 #include <asm/processor.h>
31 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
32 DECLARE_GLOBAL_DATA_PTR;
35 #ifndef CFG_PLL_RECONFIG
36 #define CFG_PLL_RECONFIG 0
39 void reconfigure_pll(u32 new_cpu_freq)
41 #if defined(CONFIG_440EPX)
44 u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */
45 fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */
46 fbdv, target_fbdv, lfbdv, target_lfbdv,
47 perdv0, target_perdv0, /* CLK_PERD */
48 spcid0, target_spcid0; /* CLK_SPCID */
50 /* Reconfigure clocks if necessary.
51 * See PPC440EPx User's Manual, sections 8.2 and 14 */
52 if (new_cpu_freq == 667) {
61 mfcpr(clk_primbd, reg);
62 temp = (reg & PRBDV_MASK) >> 24;
63 prbdv0 = temp ? temp : 8;
64 if (prbdv0 != target_prbdv0) {
66 reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
67 mtcpr(clk_primbd, reg);
73 temp = (reg & PLLD_FWDVA_MASK) >> 16;
74 fwdva = temp ? temp : 16;
76 temp = (reg & PLLD_FWDVB_MASK) >> 8;
77 fwdvb = temp ? temp : 8;
79 temp = (reg & PLLD_FBDV_MASK) >> 24;
80 fbdv = temp ? temp : 32;
82 temp = (reg & PLLD_LFBDV_MASK);
83 lfbdv = temp ? temp : 64;
85 if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) {
86 reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
87 PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
88 reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) |
89 ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
90 ((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
91 (target_lfbdv == 64 ? 0 : target_lfbdv);
97 perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
98 if (perdv0 != target_perdv0) {
99 reg &= ~CPR0_PERD_PERDV0_MASK;
100 reg |= (target_perdv0 << 24);
101 mtcpr(clk_perd, reg);
105 mfcpr(clk_spcid, reg);
106 temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
107 spcid0 = temp ? temp : 4;
108 if (spcid0 != target_spcid0) {
109 reg &= ~CPR0_SPCID_SPCIDV0_MASK;
110 reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
111 mtcpr(clk_spcid, reg);
115 /* Set reload inhibit so configuration will persist across
116 * processor resets */
117 mfcpr(clk_icfg, reg);
118 reg &= ~CPR0_ICFG_RLI_MASK;
120 mtcpr(clk_icfg, reg);
123 /* Reset processor if configuration changed */
125 __asm__ __volatile__ ("sync; isync");
126 mtspr(dbcr0, 0x20000000);
132 * Breath some life into the CPU...
134 * Reconfigure PLL if necessary,
135 * set up the memory map,
136 * initialize a bunch of registers
141 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) || \
142 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
143 defined(CONFIG_460GT) || defined(CONFIG_460SX)
147 reconfigure_pll(CFG_PLL_RECONFIG);
149 #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
151 * GPIO0 setup (select GPIO or alternate function)
153 #if defined(CFG_GPIO0_OR)
154 out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */
156 #if defined(CFG_GPIO0_ODR)
157 out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */
159 out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
160 out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
161 out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
162 out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
163 out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
164 out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
165 #if defined(CFG_GPIO0_ISR2H)
166 out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H);
167 out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L);
169 #if defined (CFG_GPIO0_TCR)
170 out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
172 #endif /* CONFIG_405EP ... && !CFG_4xx_GPIO_TABLE */
174 #if defined (CONFIG_405EP)
176 * Set EMAC noise filter bits
178 mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
181 * Enable the internal PCI arbiter
183 mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
184 #endif /* CONFIG_405EP */
186 #if defined(CFG_4xx_GPIO_TABLE)
187 gpio_set_chip_configuration();
188 #endif /* CFG_4xx_GPIO_TABLE */
191 * External Bus Controller (EBC) Setup
193 #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
194 #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
195 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
196 defined(CONFIG_405EX) || defined(CONFIG_405))
198 * Move the next instructions into icache, since these modify the flash
199 * we are running from!
201 asm volatile(" bl 0f" ::: "lr");
202 asm volatile("0: mflr 3" ::: "r3");
203 asm volatile(" addi 4, 0, 14" ::: "r4");
204 asm volatile(" mtctr 4" ::: "ctr");
205 asm volatile("1: icbt 0, 3");
206 asm volatile(" addi 3, 3, 32" ::: "r3");
207 asm volatile(" bdnz 1b" ::: "ctr", "cr0");
208 asm volatile(" addis 3, 0, 0x0" ::: "r3");
209 asm volatile(" ori 3, 3, 0xA000" ::: "r3");
210 asm volatile(" mtctr 3" ::: "ctr");
211 asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
214 mtebc(pb0ap, CFG_EBC_PB0AP);
215 mtebc(pb0cr, CFG_EBC_PB0CR);
218 #if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
219 mtebc(pb1ap, CFG_EBC_PB1AP);
220 mtebc(pb1cr, CFG_EBC_PB1CR);
223 #if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
224 mtebc(pb2ap, CFG_EBC_PB2AP);
225 mtebc(pb2cr, CFG_EBC_PB2CR);
228 #if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
229 mtebc(pb3ap, CFG_EBC_PB3AP);
230 mtebc(pb3cr, CFG_EBC_PB3CR);
233 #if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
234 mtebc(pb4ap, CFG_EBC_PB4AP);
235 mtebc(pb4cr, CFG_EBC_PB4CR);
238 #if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
239 mtebc(pb5ap, CFG_EBC_PB5AP);
240 mtebc(pb5cr, CFG_EBC_PB5CR);
243 #if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
244 mtebc(pb6ap, CFG_EBC_PB6AP);
245 mtebc(pb6cr, CFG_EBC_PB6CR);
248 #if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
249 mtebc(pb7ap, CFG_EBC_PB7AP);
250 mtebc(pb7cr, CFG_EBC_PB7CR);
253 #if defined (CFG_EBC_CFG)
254 mtebc(EBC0_CFG, CFG_EBC_CFG);
257 #if defined(CONFIG_WATCHDOG)
259 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
260 val |= 0xb8000000; /* generate system reset after 1.34 seconds */
261 #elif defined(CONFIG_440EPX)
262 val |= 0xb0000000; /* generate system reset after 1.34 seconds */
264 val |= 0xf0000000; /* generate system reset after 2.684 seconds */
266 #if defined(CFG_4xx_RESET_TYPE)
267 val &= ~0x30000000; /* clear WRC bits */
268 val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */
273 val |= 0x80000000; /* enable watchdog timer */
276 reset_4xx_watchdog();
277 #endif /* CONFIG_WATCHDOG */
279 #if defined(CONFIG_440GX)
280 /* Take the GX out of compatibility mode
281 * Travis Sawyer, 9 Mar 2004
282 * NOTE: 440gx user manual inconsistency here
283 * Compatibility mode and Ethernet Clock select are not
284 * correct in the manual
289 #endif /* CONFIG_440GX */
291 #if defined(CONFIG_460EX)
293 * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and
294 * clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata
295 * regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA
297 mfsdr(SDR0_AHB_CFG, val);
300 mtsdr(SDR0_AHB_CFG, val);
301 mfsdr(SDR0_USB2HOST_CFG, val);
304 mtsdr(SDR0_USB2HOST_CFG, val);
305 #endif /* CONFIG_460EX */
307 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
308 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
309 defined(CONFIG_405EX) || defined(CONFIG_460SX)
311 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
313 val = (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
314 mtdcr(plb0_acr, val);
315 val = (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
316 mtdcr(plb1_acr, val);
317 #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
321 * initialize higher level parts of CPU like time base and timers
323 int cpu_init_r (void)
325 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
328 #if defined(CONFIG_405GP)
329 uint pvr = get_pvr();
333 * Write Ethernetaddress into on-chip register
336 reg |= bd->bi_enetaddr[0]; /* set high address */
338 reg |= bd->bi_enetaddr[1];
339 out32 (EMAC_IAH, reg);
342 reg |= bd->bi_enetaddr[2]; /* set low address */
344 reg |= bd->bi_enetaddr[3];
346 reg |= bd->bi_enetaddr[4];
348 reg |= bd->bi_enetaddr[5];
349 out32 (EMAC_IAL, reg);
351 #if defined(CONFIG_405GP)
353 * Set edge conditioning circuitry on PPC405GPr
354 * for compatibility to existing PPC405GP designs.
356 if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
357 mtdcr(ecr, 0x60606000);
359 #endif /* defined(CONFIG_405GP) */
360 #endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */