3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 /*------------------------------------------------------------------------------+ */
25 * This source code has been made available to you by IBM on an AS-IS
26 * basis. Anyone receiving this source is licensed under IBM
27 * copyrights to use it in any way he or she deems fit, including
28 * copying it, modifying it, compiling it, and redistributing it either
29 * with or without modifications. No license under IBM patents or
30 * patent applications is to be implied by the copyright license.
32 * Any user of this software should understand that IBM cannot provide
33 * technical support for this software and will not be responsible for
34 * any consequences resulting from the use of this software.
36 * Any person who transfers this source code or any derivative work
37 * must include the IBM copyright notice, this paragraph, and the
38 * preceding two paragraphs in the transferred software.
40 * COPYRIGHT I B M CORPORATION 1995
41 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
43 /*------------------------------------------------------------------------------- */
45 * Travis Sawyer 15 September 2004
46 * Added CONFIG_SERIAL_MULTI support
50 #include <asm/processor.h>
54 #ifdef CONFIG_SERIAL_MULTI
58 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
62 /*****************************************************************************/
65 #define SPU_BASE 0x40000000
67 #define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
68 #define spu_LineStat_w 0x04 /* Line Status Register (Set) */
69 #define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
70 #define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
71 #define spu_BRateDivh 0x10 /* Baud rate divisor high */
72 #define spu_BRateDivl 0x14 /* Baud rate divisor low */
73 #define spu_CtlReg 0x18 /* Control Register */
74 #define spu_RxCmd 0x1c /* Rx Command Register */
75 #define spu_TxCmd 0x20 /* Tx Command Register */
76 #define spu_RxBuff 0x24 /* Rx data buffer */
77 #define spu_TxBuff 0x24 /* Tx data buffer */
79 /*-----------------------------------------------------------------------------+
80 | Line Status Register.
81 +-----------------------------------------------------------------------------*/
82 #define asyncLSRport1 0x40000000
83 #define asyncLSRport1set 0x40000004
84 #define asyncLSRDataReady 0x80
85 #define asyncLSRFramingError 0x40
86 #define asyncLSROverrunError 0x20
87 #define asyncLSRParityError 0x10
88 #define asyncLSRBreakInterrupt 0x08
89 #define asyncLSRTxHoldEmpty 0x04
90 #define asyncLSRTxShiftEmpty 0x02
92 /*-----------------------------------------------------------------------------+
93 | Handshake Status Register.
94 +-----------------------------------------------------------------------------*/
95 #define asyncHSRport1 0x40000008
96 #define asyncHSRport1set 0x4000000c
97 #define asyncHSRDsr 0x80
98 #define asyncLSRCts 0x40
100 /*-----------------------------------------------------------------------------+
102 +-----------------------------------------------------------------------------*/
103 #define asyncCRport1 0x40000018
104 #define asyncCRNormal 0x00
105 #define asyncCRLoopback 0x40
106 #define asyncCRAutoEcho 0x80
107 #define asyncCRDtr 0x20
108 #define asyncCRRts 0x10
109 #define asyncCRWordLength7 0x00
110 #define asyncCRWordLength8 0x08
111 #define asyncCRParityDisable 0x00
112 #define asyncCRParityEnable 0x04
113 #define asyncCREvenParity 0x00
114 #define asyncCROddParity 0x02
115 #define asyncCRStopBitsOne 0x00
116 #define asyncCRStopBitsTwo 0x01
117 #define asyncCRDisableDtrRts 0x00
119 /*-----------------------------------------------------------------------------+
120 | Receiver Command Register.
121 +-----------------------------------------------------------------------------*/
122 #define asyncRCRport1 0x4000001c
123 #define asyncRCRDisable 0x00
124 #define asyncRCREnable 0x80
125 #define asyncRCRIntDisable 0x00
126 #define asyncRCRIntEnabled 0x20
127 #define asyncRCRDMACh2 0x40
128 #define asyncRCRDMACh3 0x60
129 #define asyncRCRErrorInt 0x10
130 #define asyncRCRPauseEnable 0x08
132 /*-----------------------------------------------------------------------------+
133 | Transmitter Command Register.
134 +-----------------------------------------------------------------------------*/
135 #define asyncTCRport1 0x40000020
136 #define asyncTCRDisable 0x00
137 #define asyncTCREnable 0x80
138 #define asyncTCRIntDisable 0x00
139 #define asyncTCRIntEnabled 0x20
140 #define asyncTCRDMACh2 0x40
141 #define asyncTCRDMACh3 0x60
142 #define asyncTCRTxEmpty 0x10
143 #define asyncTCRErrorInt 0x08
144 #define asyncTCRStopPause 0x04
145 #define asyncTCRBreakGen 0x02
147 /*-----------------------------------------------------------------------------+
148 | Miscellanies defines.
149 +-----------------------------------------------------------------------------*/
150 #define asyncTxBufferport1 0x40000024
151 #define asyncRxBufferport1 0x40000024
152 #define asyncDLABLsbport1 0x40000014
153 #define asyncDLABMsbport1 0x40000010
154 #define asyncXOFFchar 0x13
155 #define asyncXONchar 0x11
158 * Minimal serial functions needed to use one of the SMC ports
159 * as serial console interface.
162 int serial_init (void)
164 DECLARE_GLOBAL_DATA_PTR;
167 unsigned short br_reg;
169 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
174 out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
175 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
176 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
177 out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
178 out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
179 out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
180 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
181 val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
186 void serial_setbrg (void)
188 DECLARE_GLOBAL_DATA_PTR;
190 unsigned short br_reg;
192 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
194 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
195 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
198 void serial_putc (const char c)
203 /* load status from handshake register */
204 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
205 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
207 out8 (SPU_BASE + spu_TxBuff, c); /* Put char */
209 while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) {
210 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
211 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
215 void serial_puts (const char *s)
224 unsigned char status = 0;
227 status = in8 (asyncLSRport1);
228 if ((status & asyncLSRDataReady) != 0x0) {
231 if ((status & ( asyncLSRFramingError |
232 asyncLSROverrunError |
233 asyncLSRParityError |
234 asyncLSRBreakInterrupt )) != 0) {
235 (void) out8 (asyncLSRport1,
236 asyncLSRFramingError |
237 asyncLSROverrunError |
238 asyncLSRParityError |
239 asyncLSRBreakInterrupt );
242 return (0x000000ff & (int) in8 (asyncRxBufferport1));
247 unsigned char status;
249 status = in8 (asyncLSRport1);
250 if ((status & asyncLSRDataReady) != 0x0) {
253 if ((status & ( asyncLSRFramingError |
254 asyncLSROverrunError |
255 asyncLSRParityError |
256 asyncLSRBreakInterrupt )) != 0) {
257 (void) out8 (asyncLSRport1,
258 asyncLSRFramingError |
259 asyncLSROverrunError |
260 asyncLSRParityError |
261 asyncLSRBreakInterrupt);
266 #endif /* CONFIG_IOP480 */
268 /*****************************************************************************/
269 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
271 #if defined(CONFIG_440)
272 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
273 #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
274 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
276 #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
277 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
280 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
281 #define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
284 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
285 #define CR0_MASK 0xdfffffff
286 #define CR0_EXTCLK_ENA 0x00800000
287 #define CR0_UDIV_POS 0
289 #define CR0_MASK 0x3fff0000
290 #define CR0_EXTCLK_ENA 0x00600000
291 #define CR0_UDIV_POS 16
292 #endif /* CONFIG_440GX */
293 #elif defined(CONFIG_405EP)
294 #define UART0_BASE 0xef600300
295 #define UART1_BASE 0xef600400
296 #define UCR0_MASK 0x0000007f
297 #define UCR1_MASK 0x00007f00
298 #define UCR0_UDIV_POS 0
299 #define UCR1_UDIV_POS 8
301 #else /* CONFIG_405GP || CONFIG_405CR */
302 #define UART0_BASE 0xef600300
303 #define UART1_BASE 0xef600400
304 #define CR0_MASK 0x00001fff
305 #define CR0_EXTCLK_ENA 0x000000c0
306 #define CR0_UDIV_POS 1
310 /* using serial port 0 or 1 as U-Boot console ? */
311 #if defined(CONFIG_UART1_CONSOLE)
312 #define ACTING_UART0_BASE UART1_BASE
313 #define ACTING_UART1_BASE UART0_BASE
314 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
315 defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
316 defined(CONFIG_440SPE)
317 #define UART0_SDR sdr_uart1
318 #define UART1_SDR sdr_uart0
319 #endif /* CONFIG_440GX */
321 #define ACTING_UART0_BASE UART0_BASE
322 #define ACTING_UART1_BASE UART1_BASE
323 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
324 defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
325 defined(CONFIG_440SPE)
326 #define UART0_SDR sdr_uart0
327 #define UART1_SDR sdr_uart1
328 #endif /* CONFIG_440GX */
331 #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
332 #error "External serial clock not supported on AMCC PPC405EP!"
335 #define UART_RBR 0x00
336 #define UART_THR 0x00
337 #define UART_IER 0x01
338 #define UART_IIR 0x02
339 #define UART_FCR 0x02
340 #define UART_LCR 0x03
341 #define UART_MCR 0x04
342 #define UART_LSR 0x05
343 #define UART_MSR 0x06
344 #define UART_SCR 0x07
345 #define UART_DLL 0x00
346 #define UART_DLM 0x01
348 /*-----------------------------------------------------------------------------+
349 | Line Status Register.
350 +-----------------------------------------------------------------------------*/
351 /*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */
352 #define asyncLSRDataReady1 0x01
353 #define asyncLSROverrunError1 0x02
354 #define asyncLSRParityError1 0x04
355 #define asyncLSRFramingError1 0x08
356 #define asyncLSRBreakInterrupt1 0x10
357 #define asyncLSRTxHoldEmpty1 0x20
358 #define asyncLSRTxShiftEmpty1 0x40
359 #define asyncLSRRxFifoError1 0x80
361 /*-----------------------------------------------------------------------------+
362 | Miscellanies defines.
363 +-----------------------------------------------------------------------------*/
364 /*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */
365 /*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */
367 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
368 /*-----------------------------------------------------------------------------+
370 +-----------------------------------------------------------------------------*/
377 volatile static serial_buffer_t buf_info;
380 #if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
381 static void serial_divs (int baudrate, unsigned long *pudiv,
382 unsigned short *pbdiv )
385 unsigned long div; /* total divisor udiv * bdiv */
386 unsigned long umin; /* minimum udiv */
387 unsigned short diff; /* smallest diff */
388 unsigned long udiv; /* best udiv */
390 unsigned short idiff; /* current diff */
391 unsigned short ibdiv; /* current bdiv */
393 unsigned long est; /* current estimate */
395 get_sys_info( &sysinfo );
397 udiv = 32; /* Assume lowest possible serial clk */
398 div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
399 umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
400 diff = 32; /* highest possible */
402 /* i is the test udiv value -- start with the largest
403 * possible (32) to minimize serial clock and constrain
406 for( i = 32; i > umin; i-- ){
409 idiff = (est > div) ? (est-div) : (div-est);
412 break; /* can't do better */
414 else if( idiff < diff ){
415 udiv = i; /* best so far */
416 diff = idiff; /* update lowest diff*/
424 #endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
427 * Minimal serial functions needed to use one of the SMC ports
428 * as serial console interface.
431 #if defined(CONFIG_440)
432 #if defined(CONFIG_SERIAL_MULTI)
433 int serial_init_dev (unsigned long dev_base)
435 int serial_init(void)
438 DECLARE_GLOBAL_DATA_PTR;
444 #ifdef CFG_EXT_SERIAL_CLOCK
448 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
449 defined(CONFIG_440SPE)
450 #if defined(CONFIG_SERIAL_MULTI)
451 if (UART0_BASE == dev_base) {
452 mfsdr(UART0_SDR,reg);
455 mfsdr(UART1_SDR,reg);
459 mfsdr(UART0_SDR,reg);
463 reg = mfdcr(cntrl0) & ~CR0_MASK;
464 #endif /* CONFIG_440GX */
465 #ifdef CFG_EXT_SERIAL_CLOCK
466 reg |= CR0_EXTCLK_ENA;
468 tmp = gd->baudrate * 16;
469 bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
471 /* For 440, the cpu clock is on divider chain A, UART on divider
472 * chain B ... so cpu clock is irrelevant. Get the "optimized"
473 * values that are subject to the 1/2 opb clock constraint
475 serial_divs (gd->baudrate, &udiv, &bdiv);
478 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
479 defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
480 defined(CONFIG_440SPE)
481 reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
482 #if defined(CONFIG_SERIAL_MULTI)
483 if (UART0_BASE == dev_base) {
484 mtsdr (UART0_SDR,reg);
486 mtsdr (UART1_SDR,reg);
489 mtsdr (UART0_SDR,reg);
492 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
496 #if defined(CONFIG_SERIAL_MULTI)
497 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
498 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
499 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
500 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
501 out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
502 out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
503 val = in8 (dev_base + UART_LSR); /* clear line status */
504 val = in8 (dev_base + UART_RBR); /* read receive buffer */
505 out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
506 out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
508 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
509 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
510 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
511 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
512 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
513 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
514 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
515 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
516 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
517 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
522 #else /* !defined(CONFIG_440) */
524 #if defined(CONFIG_SERIAL_MULTI)
525 int serial_init_dev (unsigned long dev_base)
527 int serial_init (void)
530 DECLARE_GLOBAL_DATA_PTR;
540 reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
542 tmp = CFG_BASE_BAUD * 16;
543 udiv = (clk + tmp / 2) / tmp;
544 if (udiv > UDIV_MAX) /* max. n bits for udiv */
546 reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
547 reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
548 mtdcr (cpc0_ucr, reg);
549 #else /* CONFIG_405EP */
550 reg = mfdcr(cntrl0) & ~CR0_MASK;
551 #ifdef CFG_EXT_SERIAL_CLOCK
552 clk = CFG_EXT_SERIAL_CLOCK;
554 reg |= CR0_EXTCLK_ENA;
557 #ifdef CFG_405_UART_ERRATA_59
558 udiv = 31; /* Errata 59: stuck at 31 */
560 tmp = CFG_BASE_BAUD * 16;
561 udiv = (clk + tmp / 2) / tmp;
562 if (udiv > UDIV_MAX) /* max. n bits for udiv */
566 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
568 #endif /* CONFIG_405EP */
570 tmp = gd->baudrate * udiv * 16;
571 bdiv = (clk + tmp / 2) / tmp;
573 #if defined(CONFIG_SERIAL_MULTI)
574 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
575 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
576 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
577 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
578 out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
579 out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
580 val = in8 (dev_base + UART_LSR); /* clear line status */
581 val = in8 (dev_base + UART_RBR); /* read receive buffer */
582 out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
583 out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
585 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
586 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
587 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
588 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
589 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
590 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
591 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
592 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
593 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
594 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
599 #endif /* if defined(CONFIG_440) */
601 #if defined(CONFIG_SERIAL_MULTI)
602 void serial_setbrg_dev (unsigned long dev_base)
604 void serial_setbrg (void)
607 DECLARE_GLOBAL_DATA_PTR;
614 #ifdef CFG_EXT_SERIAL_CLOCK
615 clk = CFG_EXT_SERIAL_CLOCK;
621 udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS);
623 udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
624 #endif /* CONFIG_405EP */
626 #if !defined(CFG_EXT_SERIAL_CLOCK) && \
627 ( defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
628 defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
629 defined(CONFIG_440SPE) )
630 serial_divs (gd->baudrate, &udiv, &bdiv);
631 tmp = udiv << CR0_UDIV_POS; /* set the UART divisor */
632 #if defined(CONFIG_SERIAL_MULTI)
633 if (UART0_BASE == dev_base) {
634 mtsdr (UART0_SDR, tmp);
636 mtsdr (UART1_SDR, tmp);
639 mtsdr (UART0_SDR, tmp);
644 tmp = gd->baudrate * udiv * 16;
645 bdiv = (clk + tmp / 2) / tmp;
646 #endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */
648 #if defined(CONFIG_SERIAL_MULTI)
649 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
650 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
651 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
652 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
654 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
655 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
656 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
657 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
661 #if defined(CONFIG_SERIAL_MULTI)
662 void serial_putc_dev (unsigned long dev_base, const char c)
664 void serial_putc (const char c)
670 #if defined(CONFIG_SERIAL_MULTI)
671 serial_putc_dev (dev_base, '\r');
676 /* check THRE bit, wait for transmiter available */
677 for (i = 1; i < 3500; i++) {
678 #if defined(CONFIG_SERIAL_MULTI)
679 if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20)
681 if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
686 #if defined(CONFIG_SERIAL_MULTI)
687 out8 (dev_base + UART_THR, c); /* put character out */
689 out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */
693 #if defined(CONFIG_SERIAL_MULTI)
694 void serial_puts_dev (unsigned long dev_base, const char *s)
696 void serial_puts (const char *s)
700 #if defined(CONFIG_SERIAL_MULTI)
701 serial_putc_dev (dev_base, *s++);
708 #if defined(CONFIG_SERIAL_MULTI)
709 int serial_getc_dev (unsigned long dev_base)
711 int serial_getc (void)
714 unsigned char status = 0;
717 #if defined(CONFIG_HW_WATCHDOG)
718 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
719 #endif /* CONFIG_HW_WATCHDOG */
720 #if defined(CONFIG_SERIAL_MULTI)
721 status = in8 (dev_base + UART_LSR);
723 status = in8 (ACTING_UART0_BASE + UART_LSR);
725 if ((status & asyncLSRDataReady1) != 0x0) {
728 if ((status & ( asyncLSRFramingError1 |
729 asyncLSROverrunError1 |
730 asyncLSRParityError1 |
731 asyncLSRBreakInterrupt1 )) != 0) {
732 #if defined(CONFIG_SERIAL_MULTI)
733 out8 (dev_base + UART_LSR,
735 out8 (ACTING_UART0_BASE + UART_LSR,
737 asyncLSRFramingError1 |
738 asyncLSROverrunError1 |
739 asyncLSRParityError1 |
740 asyncLSRBreakInterrupt1);
743 #if defined(CONFIG_SERIAL_MULTI)
744 return (0x000000ff & (int) in8 (dev_base));
746 return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
750 #if defined(CONFIG_SERIAL_MULTI)
751 int serial_tstc_dev (unsigned long dev_base)
753 int serial_tstc (void)
756 unsigned char status;
758 #if defined(CONFIG_SERIAL_MULTI)
759 status = in8 (dev_base + UART_LSR);
761 status = in8 (ACTING_UART0_BASE + UART_LSR);
763 if ((status & asyncLSRDataReady1) != 0x0) {
766 if ((status & ( asyncLSRFramingError1 |
767 asyncLSROverrunError1 |
768 asyncLSRParityError1 |
769 asyncLSRBreakInterrupt1 )) != 0) {
770 #if defined(CONFIG_SERIAL_MULTI)
771 out8 (dev_base + UART_LSR,
773 out8 (ACTING_UART0_BASE + UART_LSR,
775 asyncLSRFramingError1 |
776 asyncLSROverrunError1 |
777 asyncLSRParityError1 |
778 asyncLSRBreakInterrupt1);
783 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
785 void serial_isr (void *arg)
789 const int rx_get = buf_info.rx_get;
790 int rx_put = buf_info.rx_put;
792 if (rx_get <= rx_put) {
793 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
795 space = rx_get - rx_put;
797 while (serial_tstc_dev (ACTING_UART0_BASE)) {
798 c = serial_getc_dev (ACTING_UART0_BASE);
800 buf_info.rx_buffer[rx_put++] = c;
803 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
805 if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
806 /* Stop flow by setting RTS inactive */
807 out8 (ACTING_UART0_BASE + UART_MCR,
808 in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
811 buf_info.rx_put = rx_put;
814 void serial_buffered_init (void)
816 serial_puts ("Switching to interrupt driven serial input mode.\n");
817 buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
821 if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
822 serial_puts ("Check CTS signal present on serial port: OK.\n");
824 serial_puts ("WARNING: CTS signal not present on serial port.\n");
827 irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
828 serial_isr /*interrupt_handler_t *handler */ ,
829 (void *) &buf_info /*void *arg */ );
831 /* Enable "RX Data Available" Interrupt on UART */
832 /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */
833 out8 (ACTING_UART0_BASE + UART_IER, 0x01);
835 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01);
836 /* Start flow by setting RTS active */
837 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
838 /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
839 out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
842 void serial_buffered_putc (const char c)
845 #if defined(CONFIG_HW_WATCHDOG)
846 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
849 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
854 void serial_buffered_puts (const char *s)
859 int serial_buffered_getc (void)
863 int rx_get = buf_info.rx_get;
866 #if defined(CONFIG_HW_WATCHDOG)
867 while (rx_get == buf_info.rx_put)
870 while (rx_get == buf_info.rx_put);
872 c = buf_info.rx_buffer[rx_get++];
873 if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
875 buf_info.rx_get = rx_get;
877 rx_put = buf_info.rx_put;
878 if (rx_get <= rx_put) {
879 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
881 space = rx_get - rx_put;
883 if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
884 /* Start flow by setting RTS active */
885 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
891 int serial_buffered_tstc (void)
893 return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
896 #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
898 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
900 AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
902 - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
903 configuration has been already done
904 - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
905 configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
907 #if (CONFIG_KGDB_SER_INDEX & 2)
908 void kgdb_serial_init (void)
910 DECLARE_GLOBAL_DATA_PTR;
913 unsigned short br_reg;
916 br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
919 * Init onboard 16550 UART
921 out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
922 out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
923 out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
924 out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
925 out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
926 out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
927 val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */
928 val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
929 out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
930 out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
933 void putDebugChar (const char c)
938 out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */
940 /* check THRE bit, wait for transfer done */
941 while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
944 void putDebugStr (const char *s)
951 int getDebugChar (void)
953 unsigned char status = 0;
956 status = in8 (ACTING_UART1_BASE + UART_LSR);
957 if ((status & asyncLSRDataReady1) != 0x0) {
960 if ((status & ( asyncLSRFramingError1 |
961 asyncLSROverrunError1 |
962 asyncLSRParityError1 |
963 asyncLSRBreakInterrupt1 )) != 0) {
964 out8 (ACTING_UART1_BASE + UART_LSR,
965 asyncLSRFramingError1 |
966 asyncLSROverrunError1 |
967 asyncLSRParityError1 |
968 asyncLSRBreakInterrupt1);
971 return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
974 void kgdb_interruptible (int yes)
979 #else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
981 void kgdb_serial_init (void)
983 serial_printf ("[on serial] ");
986 void putDebugChar (int c)
991 void putDebugStr (const char *str)
996 int getDebugChar (void)
998 return serial_getc ();
1001 void kgdb_interruptible (int yes)
1005 #endif /* (CONFIG_KGDB_SER_INDEX & 2) */
1006 #endif /* CFG_CMD_KGDB */
1009 #if defined(CONFIG_SERIAL_MULTI)
1010 int serial0_init(void)
1012 return (serial_init_dev(UART0_BASE));
1015 int serial1_init(void)
1017 return (serial_init_dev(UART1_BASE));
1019 void serial0_setbrg (void)
1021 serial_setbrg_dev(UART0_BASE);
1023 void serial1_setbrg (void)
1025 serial_setbrg_dev(UART1_BASE);
1028 void serial0_putc(const char c)
1030 serial_putc_dev(UART0_BASE,c);
1033 void serial1_putc(const char c)
1035 serial_putc_dev(UART1_BASE, c);
1037 void serial0_puts(const char *s)
1039 serial_puts_dev(UART0_BASE, s);
1042 void serial1_puts(const char *s)
1044 serial_puts_dev(UART1_BASE, s);
1047 int serial0_getc(void)
1049 return(serial_getc_dev(UART0_BASE));
1052 int serial1_getc(void)
1054 return(serial_getc_dev(UART1_BASE));
1056 int serial0_tstc(void)
1058 return (serial_tstc_dev(UART0_BASE));
1061 int serial1_tstc(void)
1063 return (serial_tstc_dev(UART1_BASE));
1066 struct serial_device serial0_device =
1078 struct serial_device serial1_device =
1089 #endif /* CONFIG_SERIAL_MULTI */
1091 #endif /* CONFIG_405GP || CONFIG_405CR */