2 * armboot - Startup Code for XScale
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
8 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
9 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
10 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 ldr pc, _undefined_instruction
37 ldr pc, _software_interrupt
38 ldr pc, _prefetch_abort
44 _undefined_instruction: .word undefined_instruction
45 _software_interrupt: .word software_interrupt
46 _prefetch_abort: .word prefetch_abort
47 _data_abort: .word data_abort
48 _not_used: .word not_used
52 .balignl 16,0xdeadbeef
56 * Startup Code (reset vector)
58 * do important init only if we don't start from RAM!
59 * - relocate armboot to ram
61 * - jump to second stage
72 * Note: _armboot_end_data and _armboot_end are defined
73 * by the (board-dependent) linker script.
74 * _armboot_end_data is the first usable FLASH address after armboot
76 .globl _armboot_end_data
78 .word armboot_end_data
84 * This is defined in the board specific linker script
95 /* IRQ stack memory (calculated at run-time) */
96 .globl IRQ_STACK_START
100 /* IRQ stack memory (calculated at run-time) */
101 .globl FIQ_STACK_START
107 /****************************************************************************/
109 /* the actual reset code */
111 /****************************************************************************/
114 mrs r0,cpsr /* set the cpu to SVC32 mode */
115 bic r0,r0,#0x1f /* (superviser mode, M=10011) */
120 * we do sys-critical inits only at reboot,
121 * not when booting from ram!
123 #ifdef CONFIG_INIT_CRITICAL
124 bl cpu_init_crit /* we do sys-critical inits */
127 relocate: /* relocate U-Boot to RAM */
128 adr r0, _start /* r0 <- current position of code */
129 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
130 cmp r0, r1 /* don't reloc during debug */
133 ldr r2, _armboot_start
135 sub r2, r3, r2 /* r2 <- size of armboot */
136 add r2, r0, r2 /* r2 <- source end address */
139 ldmia r0!, {r3-r10} /* copy from source address [r0] */
140 stmia r1!, {r3-r10} /* copy to target address [r1] */
141 cmp r0, r2 /* until source end addreee [r2] */
144 /* Set up the stack */
146 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
147 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
148 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
149 #ifdef CONFIG_USE_IRQ
150 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
152 sub sp, r0, #12 /* leave 3 words for abort-stack */
156 ldr r0, _bss_start /* find start of bss segment */
157 add r0, r0, #4 /* start at first byte of bss */
158 ldr r1, _bss_end /* stop here */
159 mov r2, #0x00000000 /* clear */
161 clbss_l:str r2, [r0] /* clear loop... */
167 ldr pc, _start_armboot
169 _start_armboot: .word start_armboot
172 /****************************************************************************/
174 /* CPU_init_critical registers */
176 /* - setup important registers */
177 /* - setup memory timing */
179 /****************************************************************************/
181 /* Interrupt-Controller base address */
182 IC_BASE: .word 0x40d00000
185 /* Reset-Controller */
186 RST_BASE: .word 0x40f00030
189 /* Operating System Timer */
190 OSTIMER_BASE: .word 0x40a00000
196 /* Clock Manager Registers */
198 CC_BASE: .word 0x41300000
200 cpuspeed: .word CFG_CPUSPEED
202 #error "You have to define CFG_CPUSPEED!!"
221 #if defined(CFG_CPUSPEED)
223 /* set clock speed */
228 mcr p14, 0, r0, c6, c0, 0
234 * before relocating, we have to setup RAM timing
235 * because memory timing is board-dependend, you will
236 * find a memsetup.S in your board directory.
242 /* Memory interfaces are working. Disable MMU and enable I-cache. */
244 ldr r0, =0x2001 /* enable access to all coproc. */
245 mcr p15, 0, r0, c15, c1, 0
248 mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
251 mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
254 mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
257 /* Enable the Icache */
259 mrc p15, 0, r0, c1, c0, 0
261 mcr p15, 0, r0, c1, c0, 0
267 /****************************************************************************/
269 /* Interrupt handling */
271 /****************************************************************************/
273 /* IRQ stack frame */
275 #define S_FRAME_SIZE 72
297 #define MODE_SVC 0x13
299 /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
301 .macro bad_save_user_regs
302 sub sp, sp, #S_FRAME_SIZE
303 stmia sp, {r0 - r12} /* Calling r0-r12 */
307 add r2, r2, #CONFIG_STACKSIZE
309 ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
310 add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
314 stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
319 /* use irq_save_user_regs / irq_restore_user_regs for */
320 /* IRQ/FIQ handling */
322 .macro irq_save_user_regs
323 sub sp, sp, #S_FRAME_SIZE
324 stmia sp, {r0 - r12} /* Calling r0-r12 */
326 stmdb r8, {sp, lr}^ /* Calling SP, LR */
327 str lr, [r8, #0] /* Save calling PC */
329 str r6, [r8, #4] /* Save CPSR */
330 str r0, [r8, #8] /* Save OLD_R0 */
334 .macro irq_restore_user_regs
335 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
337 ldr lr, [sp, #S_PC] @ Get PC
338 add sp, sp, #S_FRAME_SIZE
339 subs pc, lr, #4 @ return & move spsr_svc into cpsr
343 ldr r13, _armboot_end @ setup our mode stack
344 add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
347 str lr, [r13] @ save caller lr / spsr
351 mov r13, #MODE_SVC @ prepare SVC-Mode
357 .macro get_irq_stack @ setup IRQ stack
358 ldr sp, IRQ_STACK_START
361 .macro get_fiq_stack @ setup FIQ stack
362 ldr sp, FIQ_STACK_START
366 /****************************************************************************/
368 /* exception handlers */
370 /****************************************************************************/
373 undefined_instruction:
376 bl do_undefined_instruction
382 bl do_software_interrupt
402 #ifdef CONFIG_USE_IRQ
409 irq_restore_user_regs
414 irq_save_user_regs /* someone ought to write a more */
415 bl do_fiq /* effiction fiq_save_user_regs */
416 irq_restore_user_regs
434 /****************************************************************************/
436 /* Reset function: the PXA250 doesn't have a reset function, so we have to */
437 /* perform a watchdog timeout for a soft reset. */
439 /****************************************************************************/
444 /* FIXME: this code is PXA250 specific. How is this handled on */
445 /* other XScale processors? */
449 /* We set OWE:WME (watchdog enable) and wait until timeout happens */
453 orr r1, r1, #0x0001 /* bit0: WME */
456 /* OS timer does only wrap every 1165 seconds, so we have to set */
457 /* the match register as well. */
459 ldr r1, [r0, #OSCR] /* read OS timer */
460 add r1, r1, #0x800 /* let OSMR3 match after */
461 add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */