4 The SBC8548 is a stand alone single board computer with a 1GHz
5 MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz
6 memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
7 and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC
13 The following possible u-boot configuration targets are available:
16 2) sbc8548_PCI_33_config
17 3) sbc8548_PCI_66_config
18 4) sbc8548_PCI_33_PCIE_config
19 5) sbc8548_PCI_66_PCIE_config
21 Generally speaking, most people should choose to use #5. Details
22 of each choice are listed below.
24 Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot
25 will be left empty (M66EN high), and so the board will operate with
26 a base clock of 66MHz. Note that you need both PCI enabled in u-boot
27 and linux in order to have functional PCI under linux.
29 The second enables PCI support and builds for a 33MHz clock rate. Note
30 that if a 33MHz 32bit card is inserted in the slot, then the whole board
31 will clock down to a 33MHz base clock instead of the default 66MHz. This
32 will change the baud clocks and mess up your serial console output if you
33 were previously running at 66MHz. If you want to use a 33MHz PCI card,
34 then you should build a U-Boot with a _PCI_33_ config and store this
35 to flash prior to powering down the board and inserting the 33MHz PCI
36 card. [The above discussion assumes that the SW2[1-4] has not been changed
37 to reflect a different CCB:SYSCLK ratio]
39 The third option builds PCI support in, and leaves the clocking at the
40 default 66MHz. Options four and five are just repeats of option two
41 and three, but with PCI-e support enabled as well.
43 PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
44 is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with
45 a 33MHz PCI configuration is currently untested.)
48 Scanning PCI devices on bus 0
49 BusDevFun VendorId DeviceId Device Class Sub-Class
50 _____________________________________________________________
51 00.00.00 0x1057 0x0012 Processor 0x20
52 00.01.00 0x8086 0x1026 Network controller 0x00
54 Scanning PCI devices on bus 1
55 BusDevFun VendorId DeviceId Device Class Sub-Class
56 _____________________________________________________________
57 01.00.00 0x1957 0x0012 Processor 0x20
59 Scanning PCI devices on bus 2
60 BusDevFun VendorId DeviceId Device Class Sub-Class
61 _____________________________________________________________
62 02.00.00 0x1148 0x9e00 Network controller 0x00
65 Memory Size and using SPD:
66 ==========================
68 The default configuration uses hard coded memory configuration settings
69 for 256MB of DDR2 @400MHz. It does not by default use the DDR2 SPD
70 EEPROM data to read what memory is installed.
72 There is a hardware errata, which causes the older local bus SDRAM
73 SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so
74 that the SPD data can not be read reliably.
76 If you want to upgrade to larger RAM size, you can simply enable
77 #define CONFIG_SPD_EEPROM
78 #define CONFIG_DDR_SPD
79 in include/configs/sbc8548.h file. (The lines are already there
80 but listed as #undef).
82 Note that you will have to physically remove the LBC 128MB DIMM
83 from the board's socket to resolve the above i2c address overlap
84 issue and allow SPD autodetection of RAM to work.
87 Updating U-boot with U-boot:
88 ============================
90 Note that versions of u-boot up to and including 2009.08 had u-boot stored
91 at 0xfff8_0000 -> 0xffff_ffff (512k). Currently it is being stored from
92 0xfffa_0000 -> 0xffff_ffff (384k). If you use an old macro/script to
93 update u-boot with u-boot and it uses the old address, you will render
94 your board inoperable, and you will require JTAG recovery.
96 The following steps list how to update with the current address:
101 erase fffa0000 ffffffff
102 cp.b 200000 fffa0000 60000
106 The "md" steps in the above are just a precautionary step that allow
107 you to confirm the u-boot version that was downloaded, and then confirm
108 that it was copied to flash.
110 The above assumes that you are using the default board settings which
111 have u-boot in the 8MB flash, tied to /CS0.
113 If you are running the default 8MB /CS0 settings but want to store an
114 image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled,
115 (as a backup, etc) then the steps will become:
120 era eff00000 efffffff
121 cp.b 200000 eff00000 100000
125 Finally, if you are running the alternate 64MB /CS0 settings and want
126 to update the in-use u-boot image, then (again with CONFIG_SYS_ALT_BOOT
127 enabled) the steps will become:
132 era fff00000 ffffffff
133 cp.b 200000 fff00000 100000
141 The following contains some summary information on hardware settings
142 that are relevant to u-boot, based on the board manual. For the
143 most up to date and complete details of the board, please request the
144 reference manual ERG-00327-001.pdf from www.windriver.com
147 intel V28F640Jx, 8192x8 (one device) at 0xff80_0000
150 intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000
151 Note that this address reflects the default setting for
152 the JTAG debugging tools, but since the alignment is
153 rather inconvenient, u-boot puts it at 0xec00_0000.
159 ----------------------------------------------------------------
160 JP12 CS0/CS6 swap see note[*] see note[*]
162 JP13 SODIMM flash write OK writes disabled
165 JP14 HRESET/TRST joined isolated
167 JP15 PWR ON when AC pwr use S1 for on/off
169 JP16 Demo LEDs lit not lit
171 JP19 PCI mode PCI PCI-X
174 [*]JP12, when jumpered parallel to the SODIMM, puts the boot flash
175 onto /CS0 and the SODIMM flash on /CS6 (default). When JP12
176 is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
177 SODIMM flash and /CS6 is for the boot flash. Note that in this
178 alternate setting, you also need to switch SW2.8 to ON.
179 See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting
180 and boot u-boot from the 64MB SODIMM
185 The defaults are marked with a *
188 ------------------------------------------------------------------
189 S1 Pwr toggle n/a n/a
191 SW2.1 CFG_SYS_PLL0 1 0*
192 SW2.2 CFG_SYS_PLL1 1* 0
193 SW2.3 CFG_SYS_PLL2 1* 0
194 SW2.4 CFG_SYS_PLL3 1 0*
195 SW2.5 CFG_CORE_PLL0 1* 0
196 SW2.6 CFG_CORE_PLL1 1 0*
197 SW2.7 CFG_CORE_PLL2 1* 0
198 SW2.8 CFG_ROM_LOC1 1 0*
200 SW3.1 CFG_HOST_AGT0 1* 0
201 SW3.2 CFG_HOST_AGT1 1* 0
202 SW3.3 CFG_HOST_AGT2 1* 0
203 SW3.4 CFG_IO_PORTS0 1* 0
204 SW3.5 CFG_IO_PORTS0 1 0*
205 SW3.6 CFG_IO_PORTS0 1 0*
207 SerDes CLK(MHz) SW5.1 SW5.2
208 ----------------------------------------------
214 SerDes CLK spread SW5.3 SW5.4
215 ----------------------------------------------
221 SW4 settings are readable from the EPLD and are currently not used for
222 any hardware settings (i.e. user configuration switches).
227 ------------------------------------------------------------------
228 D13 PCI/PCI-X PCI-X PCI
229 D14 3.3V PWR 3.3V no power
230 D15 SYSCLK 66MHz 33MHz
235 start end CS<n> width Desc.
236 ----------------------------------------------------------------------
237 0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB)
238 f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB)
239 f800_0000 f8b0_1fff CS5 - EPLD
240 fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) [*]
241 ff80_0000 ffff_ffff CS0 8 Boot flash (8MB)
243 [*] fb80 represents the default programmed by WR JTAG register files,
244 but u-boot places the flash at either ec00 or fc00 based on JP12.
246 The EPLD on CS5 demuxes the following devices at the following offsets:
248 offset size width device
249 --------------------------------------------------------
250 0 1fff 8 7 segment display LED
251 10_0000 1fff 4 user switches
252 30_0000 1fff 4 HW Rev. register
253 b0_0000 1fff 8 8kB EEPROM