2 * Copyright (C) 2010 Freescale Semiconductor, Inc.
3 * Terry Lv <r65388@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * with the reference on libata and ahci drvier in kernel
33 #include <linux/ctype.h>
34 #include <asm/errno.h>
36 #include <linux/bitops.h>
38 #ifdef CONFIG_ARCH_MMU
39 #include <asm/arch/mmu.h>
42 #include "dwc_ahsata.h"
44 struct sata_port_regs {
68 struct sata_host_regs {
97 #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
98 #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
100 #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
102 #ifdef CONFIG_ARCH_MMU
106 extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
108 static inline void mdelay(u32 msec)
111 for (i = 0; i < msec; ++i)
115 static inline void sdelay(u32 sec)
118 for (i = 0; i < sec; ++i)
122 void dprint_buffer(u8 *buf, s32 len)
130 for (i = 0; i < len; ++i) {
131 printf("%02x ", *buf++);
141 static inline u32 ahci_port_base(u32 base, u32 port)
143 return base + 0x100 + (port * 0x80);
147 static void ahci_setup_port(struct ahci_ioports *port, u32 base,
150 base = ahci_port_base(base, port_idx);
153 static int waiting_for_cmd_completed(u8 *offset,
161 ((status = readl(offset)) & sign) && i < timeout_msec;
165 return (i < timeout_msec) ? 0 : -1;
168 static int ahci_setup_oobr(struct ahci_probe_ent *probe_ent,
171 struct sata_host_regs *host_mmio =
172 (struct sata_host_regs *)probe_ent->mmio_base;
174 writel(SATA_HOST_OOBR_WE, &(host_mmio->oobr));
175 writel(0x02060b14, &(host_mmio->oobr));
180 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
182 u32 tmp, cap_save, num_ports;
183 int i, j, timeout = 1000;
184 struct sata_port_regs *port_mmio = NULL;
185 struct sata_host_regs *host_mmio =
186 (struct sata_host_regs *)probe_ent->mmio_base;
187 int clk = mxc_get_clock(MXC_SATA_CLK);
189 cap_save = readl(&(host_mmio->cap));
190 cap_save |= SATA_HOST_CAP_SSS;
192 /* global controller reset */
193 tmp = readl(&(host_mmio->ghc));
194 if ((tmp & SATA_HOST_GHC_HR) == 0)
195 writel_with_flush(tmp | SATA_HOST_GHC_HR, &(host_mmio->ghc));
197 while ((readl(&(host_mmio->ghc)) & SATA_HOST_GHC_HR)
202 debug("controller reset failed (0x%x)\n", tmp);
207 writel(clk / 1000, &(host_mmio->timer1ms));
209 ahci_setup_oobr(probe_ent, 0);
211 writel_with_flush(SATA_HOST_GHC_AE, &(host_mmio->ghc));
212 writel(cap_save, &(host_mmio->cap));
213 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
214 writel_with_flush((1 << num_ports) - 1,
217 /* Determine which Ports are implemented by the DWC_ahsata,
218 * by reading the PI register. This bit map value aids the
219 * software to determine how many Ports are available and
220 * which Port registers need to be initialized. */
221 probe_ent->cap = readl(&(host_mmio->cap));
222 probe_ent->port_map = readl(&(host_mmio->pi));
223 /* Determine how many command slots the HBA supports */
225 (probe_ent->cap & SATA_HOST_CAP_NP_MASK) + 1;
227 debug("cap 0x%x port_map 0x%x n_ports %d\n",
228 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
230 for (i = 0; i < probe_ent->n_ports; i++) {
231 probe_ent->port[i].port_mmio =
232 ahci_port_base((u32)host_mmio, i);
234 (struct sata_port_regs *)probe_ent->port[i].port_mmio;
235 ahci_setup_port(&probe_ent->port[i], (u32)host_mmio, i);
237 /* make sure port is not active */
238 /* Ensure that the DWC_ahsata is in idle state */
239 tmp = readl(&(port_mmio->cmd));
240 /* When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
241 * are all cleared, the Port is in an idle state. */
242 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
243 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
244 /* System software places a Port into the idle state by
245 * clearing P#CMD.ST and waiting for P#CMD.CR to return
248 tmp &= ~SATA_PORT_CMD_ST;
249 writel_with_flush(tmp, &(port_mmio->cmd));
251 /* spec says 500 msecs for each bit, so
252 * this is slightly incorrect.
257 while ((readl(&(port_mmio->cmd)) & SATA_PORT_CMD_CR)
262 debug("port reset failed (0x%x)\n", tmp);
268 tmp = readl(&(port_mmio->cmd));
269 writel((tmp | SATA_PORT_CMD_SUD), &(port_mmio->cmd));
271 /* Wait for spin-up to finish */
273 while (!(readl(&(port_mmio->cmd)) | SATA_PORT_CMD_SUD)
277 debug("Spin-Up can't finish!\n");
281 for (j = 0; j < 100; ++j) {
283 tmp = readl(&(port_mmio->ssts));
284 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
285 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
289 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
291 while (!(readl(&(port_mmio->serr)) | SATA_PORT_SERR_DIAG_X)
295 debug("Can't find DIAG_X set!\n");
299 /* For each implemented Port, clear the P#SERR
300 * register, by writing ones to each implemented\
302 tmp = readl(&(port_mmio->serr));
303 debug("P#SERR 0x%x\n",
305 writel(tmp, &(port_mmio->serr));
307 /* Ack any pending irq events for this port */
308 tmp = readl(&(host_mmio->is));
309 debug("IS 0x%x\n", tmp);
311 writel(tmp, &(host_mmio->is));
313 writel(1 << i, &(host_mmio->is));
315 /* set irq mask (enables interrupts) */
316 writel(DEF_PORT_IRQ, &(port_mmio->ie));
318 /*register linkup ports */
319 tmp = readl(&(port_mmio->ssts));
320 debug("Port %d status: 0x%x\n", i, tmp);
321 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
322 probe_ent->link_port_map |= (0x01 << i);
325 tmp = readl(&(host_mmio->ghc));
326 debug("GHC 0x%x\n", tmp);
327 writel(tmp | SATA_HOST_GHC_IE, &(host_mmio->ghc));
328 tmp = readl(&(host_mmio->ghc));
329 debug("GHC 0x%x\n", tmp);
334 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
336 struct sata_host_regs *host_mmio =
337 (struct sata_host_regs *)probe_ent->mmio_base;
338 u32 vers, cap, impl, speed;
342 vers = readl(&(host_mmio->vs));
343 cap = probe_ent->cap;
344 impl = probe_ent->port_map;
346 speed = (cap & SATA_HOST_CAP_ISS_MASK)
347 >> SATA_HOST_CAP_ISS_OFFSET;
357 printf("AHCI %02x%02x.%02x%02x "
358 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
363 ((cap >> 8) & 0x1f) + 1,
372 cap & (1 << 31) ? "64bit " : "",
373 cap & (1 << 30) ? "ncq " : "",
374 cap & (1 << 28) ? "ilck " : "",
375 cap & (1 << 27) ? "stag " : "",
376 cap & (1 << 26) ? "pm " : "",
377 cap & (1 << 25) ? "led " : "",
378 cap & (1 << 24) ? "clo " : "",
379 cap & (1 << 19) ? "nz " : "",
380 cap & (1 << 18) ? "only " : "",
381 cap & (1 << 17) ? "pmp " : "",
382 cap & (1 << 15) ? "pio " : "",
383 cap & (1 << 14) ? "slum " : "",
384 cap & (1 << 13) ? "part " : "");
387 static int ahci_init_one(int pdev)
390 struct ahci_probe_ent *probe_ent = NULL;
392 probe_ent = malloc(sizeof(struct ahci_probe_ent));
393 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
394 probe_ent->dev = pdev;
396 probe_ent->host_flags = ATA_FLAG_SATA
402 probe_ent->mmio_base = CONFIG_DWC_AHSATA_BASE_ADDR;
404 /* initialize adapter */
405 rc = ahci_host_init(probe_ent);
409 ahci_print_info(probe_ent);
411 #ifdef CONFIG_ARCH_MMU
412 dma_buf = (u8 *)memalign(ATA_MAX_SECTORS * ATA_SECT_SIZE, 4);
413 if (NULL == dma_buf) {
414 printf("Fail to alloc buf for dma access!\n");
419 /* Save the private struct to block device struct */
420 sata_dev_desc[pdev].priv = (void *)probe_ent;
428 static int ahci_fill_sg(struct ahci_probe_ent *probe_ent,
429 u8 port, unsigned char *buf, int buf_len)
431 struct ahci_ioports *pp = &(probe_ent->port[port]);
432 #ifdef CONFIG_ARCH_MMU
433 struct ahci_sg *ahci_sg =
434 (struct ahci_sg *)ioremap_nocache(
435 iomem_to_phys((unsigned long)pp->cmd_tbl_sg),
438 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
440 u32 sg_count, max_bytes;
443 max_bytes = MAX_DATA_BYTES_PER_SG;
444 sg_count = ((buf_len - 1) / max_bytes) + 1;
445 if (sg_count > AHCI_MAX_SG) {
446 printf("Error:Too much sg!\n");
450 for (i = 0; i < sg_count; i++) {
451 #ifdef CONFIG_ARCH_MMU
453 iomem_to_phys(cpu_to_le32((u32)buf + i * max_bytes));
456 cpu_to_le32((u32)buf + i * max_bytes);
458 ahci_sg->addr_hi = 0;
459 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
464 buf_len -= max_bytes;
470 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
472 #ifdef CONFIG_ARCH_MMU
473 struct ahci_cmd_hdr *cmd_hdr =
474 (struct ahci_cmd_hdr *)ioremap_nocache(
475 iomem_to_phys((unsigned long)pp->cmd_slot
476 + AHCI_CMD_SLOT_SZ * cmd_slot), 0);
478 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
479 AHCI_CMD_SLOT_SZ * cmd_slot);
482 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
483 cmd_hdr->opts = cpu_to_le32(opts);
485 #ifdef CONFIG_ARCH_MMU
487 iomem_to_phys(cpu_to_le32(pp->cmd_tbl & 0xffffffff));
489 cmd_hdr->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
491 cmd_hdr->tbl_addr_hi = 0;
494 #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
496 static int ahci_exec_ata_cmd(struct ahci_probe_ent *probe_ent,
497 u8 port, struct sata_fis_h2d *cfis,
498 u8 *buf, u32 buf_len, s32 is_write)
500 struct ahci_ioports *pp = &(probe_ent->port[port]);
501 struct sata_port_regs *port_mmio =
502 (struct sata_port_regs *)pp->port_mmio;
504 int sg_count = 0, cmd_slot = 0;
506 cmd_slot = AHCI_GET_CMD_SLOT(readl(&(port_mmio->ci)));
507 if (32 == cmd_slot) {
508 printf("Can't find empty command slot!\n");
511 /* Check xfer length */
512 if (buf_len > MAX_BYTES_PER_TRANS) {
513 printf("Max transfer length is %dB\n\r",
514 MAX_BYTES_PER_TRANS);
518 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
520 sg_count = ahci_fill_sg(probe_ent, port, buf, buf_len);
521 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
524 ahci_fill_cmd_slot(pp, cmd_slot, opts);
526 writel_with_flush(1 << cmd_slot, &(port_mmio->ci));
528 if (waiting_for_cmd_completed((u8 *)&(port_mmio->ci),
529 10000, 0x1 << cmd_slot)) {
530 printf("timeout exit!\n");
533 debug("ahci_exec_ata_cmd: %d byte transferred.\n",
534 pp->cmd_slot->status);
539 static void ahci_set_feature(u8 dev, u8 port)
541 struct ahci_probe_ent *probe_ent =
542 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
543 struct sata_fis_h2d h2d, *cfis = &h2d;
546 memset(cfis, 0, sizeof(struct sata_fis_h2d));
547 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
548 cfis->pm_port_c = 1 << 7;
549 cfis->command = ATA_CMD_SET_FEATURES;
550 cfis->features = SETFEATURES_XFER;
551 cfis->sector_count = ffs(probe_ent->udma_mask + 1) + 0x3e;
553 ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, READ_CMD);
556 static int ahci_port_start(struct ahci_probe_ent *probe_ent,
559 struct ahci_ioports *pp = &(probe_ent->port[port]);
560 struct sata_port_regs *port_mmio =
561 (struct sata_port_regs *)pp->port_mmio;
566 debug("Enter start port: %d\n", port);
567 port_status = readl(&(port_mmio->ssts));
568 debug("Port %d status: %x\n", port, port_status);
569 if ((port_status & 0xf) != 0x03) {
570 printf("No Link on this port!\n");
574 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
577 printf("No mem for table!\n");
581 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
582 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
585 * First item in chunk of DMA memory: 32-slot command table,
586 * 32 bytes each in size
588 #ifdef CONFIG_ARCH_MMU
590 (struct ahci_cmd_hdr *)ioremap_nocache(iomem_to_phys((ulong)mem),
593 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
595 debug("cmd_slot = 0x%x\n", pp->cmd_slot);
596 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
599 * Second item: Received-FIS area, 256-Byte aligned
601 #ifdef CONFIG_ARCH_MMU
602 pp->rx_fis = (u32)ioremap_nocache(iomem_to_phys((ulong)mem),
607 mem += AHCI_RX_FIS_SZ;
610 * Third item: data area for storing a single command
611 * and its scatter-gather table
613 #ifdef CONFIG_ARCH_MMU
614 pp->cmd_tbl = (u32)ioremap_nocache(iomem_to_phys((ulong)mem),
619 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
621 mem += AHCI_CMD_TBL_HDR;
623 writel_with_flush(0x00004444, &(port_mmio->dmacr));
624 #ifdef CONFIG_ARCH_MMU
626 (struct ahci_sg *)ioremap_nocache(iomem_to_phys((ulong)mem),
628 writel_with_flush(iomem_to_phys((unsigned long)pp->cmd_slot), &port_mmio->clb);
629 writel_with_flush(iomem_to_phys(pp->rx_fis), &port_mmio->fb);
631 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
632 writel_with_flush((u32)pp->cmd_slot, &(port_mmio->clb));
633 writel_with_flush(pp->rx_fis, &(port_mmio->fb));
637 writel_with_flush((SATA_PORT_CMD_FRE | readl(&(port_mmio->cmd))),
640 /* Wait device ready */
641 while ((readl(&(port_mmio->tfd)) & (SATA_PORT_TFD_STS_ERR |
642 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
646 debug("Device not ready for BSY, DRQ and"
651 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
652 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
653 PORT_CMD_START, &(port_mmio->cmd));
655 debug("Exit start port %d\n", port);
660 int init_sata(int dev)
664 struct ahci_probe_ent *probe_ent = NULL;
666 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
667 printf("The sata index %d is out of ranges\n\r", dev);
673 probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
674 linkmap = probe_ent->link_port_map;
677 printf("No port device detected!\n");
681 for (i = 0; i < probe_ent->n_ports; i++) {
682 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
683 if (ahci_port_start(probe_ent, (u8)i)) {
684 printf("Can not start port %d\n", i);
687 /* ahci_set_feature(dev, (u8)i); */
688 probe_ent->hard_port_no = i;
696 static void dwc_ahsata_print_info(int dev)
698 block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
700 printf("SATA Device Info:\n\r");
701 #ifdef CONFIG_SYS_64BIT_LBA
702 printf("S/N: %s\n\rProduct model number: %s\n\r"
703 "Firmware version: %s\n\rCapacity: %lld sectors\n\r",
704 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
706 printf("S/N: %s\n\rProduct model number: %s\n\r"
707 "Firmware version: %s\n\rCapacity: %ld sectors\n\r",
708 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
712 static void dwc_ahsata_identify(int dev, u16 *id)
714 struct ahci_probe_ent *probe_ent =
715 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
716 struct sata_fis_h2d h2d, *cfis = &h2d;
717 u8 port = probe_ent->hard_port_no;
719 memset(cfis, 0, sizeof(struct sata_fis_h2d));
721 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
722 cfis->pm_port_c = 0x80; /* is command */
723 cfis->command = ATA_CMD_ID_ATA;
725 ahci_exec_ata_cmd(probe_ent, port, cfis,
726 (u8 *)id, ATA_ID_WORDS * 2, READ_CMD);
727 ata_swap_buf_le16(id, ATA_ID_WORDS);
730 static void dwc_ahsata_xfer_mode(int dev, u16 *id)
732 struct ahci_probe_ent *probe_ent =
733 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
735 probe_ent->pio_mask = id[ATA_ID_PIO_MODES];
736 probe_ent->udma_mask = id[ATA_ID_UDMA_MODES];
737 debug("pio %04x, udma %04x\n\r",
738 probe_ent->pio_mask, probe_ent->udma_mask);
741 static u32 dwc_ahsata_rw_cmd(int dev, u32 start, u32 blkcnt,
742 u8 *buffer, int is_write)
744 struct ahci_probe_ent *probe_ent =
745 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
746 struct sata_fis_h2d h2d, *cfis = &h2d;
747 u8 port = probe_ent->hard_port_no;
749 #ifdef CONFIG_ARCH_MMU
750 u8 *dma_buf_virt = NULL;
752 dma_buf_virt = (u8 *)ioremap_nocache((ulong)dma_buf, 0);
753 memset(dma_buf_virt, 0, blkcnt * ATA_SECT_SIZE);
758 memset(cfis, 0, sizeof(struct sata_fis_h2d));
760 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
761 cfis->pm_port_c = 0x80; /* is command */
762 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
763 cfis->device = ATA_LBA;
765 cfis->device |= (block >> 24) & 0xf;
766 cfis->lba_high = (block >> 16) & 0xff;
767 cfis->lba_mid = (block >> 8) & 0xff;
768 cfis->lba_low = block & 0xff;
769 cfis->sector_count = (u8)(blkcnt & 0xff);
771 #ifdef CONFIG_ARCH_MMU
773 memcpy(dma_buf_virt, buffer, ATA_SECT_SIZE * blkcnt);
774 if (ahci_exec_ata_cmd(probe_ent, port, cfis, dma_buf_virt,
775 ATA_SECT_SIZE * blkcnt, is_write) > 0) {
777 memcpy(buffer, dma_buf_virt, ATA_SECT_SIZE * blkcnt);
783 if (ahci_exec_ata_cmd(probe_ent, port, cfis,
784 buffer, ATA_SECT_SIZE * blkcnt, is_write) > 0)
791 void dwc_ahsata_flush_cache(int dev)
793 struct ahci_probe_ent *probe_ent =
794 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
795 struct sata_fis_h2d h2d, *cfis = &h2d;
796 u8 port = probe_ent->hard_port_no;
798 memset(cfis, 0, sizeof(struct sata_fis_h2d));
800 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
801 cfis->pm_port_c = 0x80; /* is command */
802 cfis->command = ATA_CMD_FLUSH;
804 ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0);
807 static u32 dwc_ahsata_rw_cmd_ext(int dev, u32 start, lbaint_t blkcnt,
808 u8 *buffer, int is_write)
810 struct ahci_probe_ent *probe_ent =
811 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
812 struct sata_fis_h2d h2d, *cfis = &h2d;
813 u8 port = probe_ent->hard_port_no;
815 #ifdef CONFIG_ARCH_MMU
816 u8 *dma_buf_virt = NULL;
818 dma_buf_virt = (u8 *)ioremap_nocache((ulong)dma_buf, 0);
819 memset(dma_buf_virt, 0, blkcnt * ATA_SECT_SIZE);
824 memset(cfis, 0, sizeof(struct sata_fis_h2d));
826 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
827 cfis->pm_port_c = 0x80; /* is command */
829 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
832 cfis->lba_high_exp = (block >> 40) & 0xff;
833 cfis->lba_mid_exp = (block >> 32) & 0xff;
834 cfis->lba_low_exp = (block >> 24) & 0xff;
835 cfis->lba_high = (block >> 16) & 0xff;
836 cfis->lba_mid = (block >> 8) & 0xff;
837 cfis->lba_low = block & 0xff;
838 cfis->device = ATA_LBA;
839 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
840 cfis->sector_count = blkcnt & 0xff;
842 #ifdef CONFIG_ARCH_MMU
844 memcpy(dma_buf_virt, buffer, ATA_SECT_SIZE * blkcnt);
845 if (ahci_exec_ata_cmd(probe_ent, port, cfis, dma_buf_virt,
846 ATA_SECT_SIZE * blkcnt, is_write) > 0) {
848 memcpy(buffer, dma_buf_virt, ATA_SECT_SIZE * blkcnt);
854 if (ahci_exec_ata_cmd(probe_ent, port, cfis, buffer,
855 ATA_SECT_SIZE * blkcnt, is_write) > 0)
862 u32 dwc_ahsata_rw_ncq_cmd(int dev, u32 start, lbaint_t blkcnt,
863 u8 *buffer, int is_write)
865 struct ahci_probe_ent *probe_ent =
866 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
867 struct sata_fis_h2d h2d, *cfis = &h2d;
868 u8 port = probe_ent->hard_port_no;
873 if (sata_dev_desc[dev].lba48 != 1) {
874 printf("execute FPDMA command on non-LBA48 hard disk\n\r");
880 memset(cfis, 0, sizeof(struct sata_fis_h2d));
882 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
883 cfis->pm_port_c = 0x80; /* is command */
885 cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
886 : ATA_CMD_FPDMA_READ;
888 cfis->lba_high_exp = (block >> 40) & 0xff;
889 cfis->lba_mid_exp = (block >> 32) & 0xff;
890 cfis->lba_low_exp = (block >> 24) & 0xff;
891 cfis->lba_high = (block >> 16) & 0xff;
892 cfis->lba_mid = (block >> 8) & 0xff;
893 cfis->lba_low = block & 0xff;
895 cfis->device = ATA_LBA;
896 cfis->features_exp = (blkcnt >> 8) & 0xff;
897 cfis->features = blkcnt & 0xff;
899 queue_depth = probe_ent->flags & SATA_FLAG_Q_DEP_MASK;
900 if (queue_depth >= DWC_AHSATA_HC_MAX_CMD)
901 ncq_channel = DWC_AHSATA_HC_MAX_CMD - 1;
903 ncq_channel = queue_depth - 1;
905 /* Use the latest queue */
906 ahci_exec_ata_cmd(probe_ent, port, cfis,
907 buffer, ATA_SECT_SIZE * blkcnt, is_write);
912 void dwc_ahsata_flush_cache_ext(int dev)
914 struct ahci_probe_ent *probe_ent =
915 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
916 struct sata_fis_h2d h2d, *cfis = &h2d;
917 u8 port = probe_ent->hard_port_no;
919 memset(cfis, 0, sizeof(struct sata_fis_h2d));
921 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
922 cfis->pm_port_c = 0x80; /* is command */
923 cfis->command = ATA_CMD_FLUSH_EXT;
925 ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0);
928 static void dwc_ahsata_init_wcache(int dev, u16 *id)
930 struct ahci_probe_ent *probe_ent =
931 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
933 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
934 probe_ent->flags |= SATA_FLAG_WCACHE;
935 if (ata_id_has_flush(id))
936 probe_ent->flags |= SATA_FLAG_FLUSH;
937 if (ata_id_has_flush_ext(id))
938 probe_ent->flags |= SATA_FLAG_FLUSH_EXT;
941 u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
942 void *buffer, int is_write)
952 #ifdef CONFIG_ARCH_MMU
953 max_blks = ATA_MAX_SECTORS;
955 max_blks = ATA_MAX_SECTORS_LBA48;
959 if (blks > max_blks) {
960 if (max_blks != dwc_ahsata_rw_cmd_ext(dev, start,
961 max_blks, addr, is_write))
965 addr += ATA_SECT_SIZE * max_blks;
967 if (blks != dwc_ahsata_rw_cmd_ext(dev, start,
968 blks, addr, is_write))
972 addr += ATA_SECT_SIZE * blks;
979 u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt,
980 void *buffer, int is_write)
990 max_blks = ATA_MAX_SECTORS;
992 if (blks > max_blks) {
993 if (max_blks != dwc_ahsata_rw_cmd(dev, start,
994 max_blks, addr, is_write))
998 addr += ATA_SECT_SIZE * max_blks;
1000 if (blks != dwc_ahsata_rw_cmd(dev, start,
1001 blks, addr, is_write))
1005 addr += ATA_SECT_SIZE * blks;
1007 } while (blks != 0);
1013 * SATA interface between low level driver and command layer
1015 ulong sata_read(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer)
1019 if (sata_dev_desc[dev].lba48)
1020 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt,
1023 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt,
1028 ulong sata_write(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer)
1031 struct ahci_probe_ent *probe_ent =
1032 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
1033 u32 flags = probe_ent->flags;
1035 if (sata_dev_desc[dev].lba48) {
1036 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt,
1038 if ((flags & SATA_FLAG_WCACHE) &&
1039 (flags & SATA_FLAG_FLUSH_EXT))
1040 dwc_ahsata_flush_cache_ext(dev);
1042 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt,
1044 if ((flags & SATA_FLAG_WCACHE) &&
1045 (flags & SATA_FLAG_FLUSH))
1046 dwc_ahsata_flush_cache(dev);
1051 int scan_sata(int dev)
1053 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
1054 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
1055 u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
1058 struct ahci_probe_ent *probe_ent =
1059 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
1060 u8 port = probe_ent->hard_port_no;
1061 block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
1063 id = (u16 *)malloc(ATA_ID_WORDS * 2);
1065 printf("id malloc failed\n\r");
1069 /* Identify device to get information */
1070 dwc_ahsata_identify(dev, id);
1073 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
1074 memcpy(pdev->product, serial, sizeof(serial));
1076 /* Firmware version */
1077 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
1078 memcpy(pdev->revision, firmware, sizeof(firmware));
1081 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
1082 memcpy(pdev->vendor, product, sizeof(product));
1084 /* Totoal sectors */
1085 n_sectors = ata_id_n_sectors(id);
1086 pdev->lba = (u32)n_sectors;
1088 pdev->type = DEV_TYPE_HARDDISK;
1089 pdev->blksz = ATA_SECT_SIZE;
1092 /* Check if support LBA48 */
1093 if (ata_id_has_lba48(id)) {
1095 debug("Device support LBA48\n\r");
1098 /* Get the NCQ queue depth from device */
1099 probe_ent->flags &= (~SATA_FLAG_Q_DEP_MASK);
1100 probe_ent->flags |= ata_id_queue_depth(id);
1102 /* Get the xfer mode from device */
1103 dwc_ahsata_xfer_mode(dev, id);
1105 /* Get the write cache status from device */
1106 dwc_ahsata_init_wcache(dev, id);
1108 /* Set the xfer mode to highest speed */
1109 ahci_set_feature(dev, port);
1113 dwc_ahsata_print_info(dev);