2 * Copyright (C) 2008,2010 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
25 #include <asm/fsl_serdes.h>
32 #ifndef CONFIG_SYS_SATA1_FLAGS
33 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
35 #ifndef CONFIG_SYS_SATA2_FLAGS
36 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
39 static struct fsl_sata_info fsl_sata_info[] = {
41 {CONFIG_SYS_SATA1, CONFIG_SYS_SATA1_FLAGS},
46 {CONFIG_SYS_SATA2, CONFIG_SYS_SATA2_FLAGS},
52 static inline void sdelay(unsigned long sec)
55 for (i = 0; i < sec; i++)
59 void dprint_buffer(unsigned char *buf, int len)
67 for (i = 0; i < len; i++) {
68 printf("%02x ", *buf++);
78 static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
80 printf("Status FIS dump:\n\r");
81 printf("fis_type: %02x\n\r", s->fis_type);
82 printf("pm_port_i: %02x\n\r", s->pm_port_i);
83 printf("status: %02x\n\r", s->status);
84 printf("error: %02x\n\r", s->error);
85 printf("lba_low: %02x\n\r", s->lba_low);
86 printf("lba_mid: %02x\n\r", s->lba_mid);
87 printf("lba_high: %02x\n\r", s->lba_high);
88 printf("device: %02x\n\r", s->device);
89 printf("lba_low_exp: %02x\n\r", s->lba_low_exp);
90 printf("lba_mid_exp: %02x\n\r", s->lba_mid_exp);
91 printf("lba_high_exp: %02x\n\r", s->lba_high_exp);
92 printf("res1: %02x\n\r", s->res1);
93 printf("sector_count: %02x\n\r", s->sector_count);
94 printf("sector_count_exp: %02x\n\r", s->sector_count_exp);
97 static int ata_wait_register(volatile unsigned *addr, u32 mask,
98 u32 val, u32 timeout_msec)
103 for (i = 0; (((temp = in_le32(addr)) & mask) != val)
104 && i < timeout_msec; i++)
106 return (i < timeout_msec) ? 0 : -1;
109 int init_sata(int dev)
112 cmd_hdr_tbl_t *cmd_hdr;
120 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
121 printf("the sata index %d is out of ranges\n\r", dev);
125 #ifdef CONFIG_MPC85xx
126 if ((dev == 0) && (!is_serdes_configured(SATA1))) {
127 printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
130 if ((dev == 1) && (!is_serdes_configured(SATA2))) {
131 printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
136 /* Allocate SATA device driver struct */
137 sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
139 printf("alloc the sata device struct failed\n\r");
142 /* Zero all of the device driver struct */
143 memset((void *)sata, 0, sizeof(fsl_sata_t));
145 /* Save the private struct to block device struct */
146 sata_dev_desc[dev].priv = (void *)sata;
148 sprintf(sata->name, "SATA%d", dev);
150 /* Set the controller register base address to device struct */
151 reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base);
152 sata->reg_base = reg;
154 /* Allocate the command header table, 4 bytes aligned */
155 length = sizeof(struct cmd_hdr_tbl);
156 align = SATA_HC_CMD_HDR_TBL_ALIGN;
157 sata->cmd_hdr_tbl_offset = (void *)malloc(length + align);
159 printf("alloc the command header failed\n\r");
163 cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align)
165 sata->cmd_hdr = cmd_hdr;
167 /* Zero all of the command header table */
168 memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align);
170 /* Allocate command descriptor for all command */
171 length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD;
172 align = SATA_HC_CMD_DESC_ALIGN;
173 sata->cmd_desc_offset = (void *)malloc(length + align);
174 if (!sata->cmd_desc_offset) {
175 printf("alloc the command descriptor failed\n\r");
178 sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align)
180 /* Zero all of command descriptor */
181 memset((void *)sata->cmd_desc_offset, 0, length + align);
183 /* Link the command descriptor to command header */
184 for (i = 0; i < SATA_HC_MAX_CMD; i++) {
185 cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i)
186 & ~(CMD_HDR_CDA_ALIGN - 1);
187 cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda);
190 /* To have safe state, force the controller offline */
191 val32 = in_le32(®->hcontrol);
192 val32 &= ~HCONTROL_ONOFF;
193 val32 |= HCONTROL_FORCE_OFFLINE;
194 out_le32(®->hcontrol, val32);
196 /* Wait the controller offline */
197 ata_wait_register(®->hstatus, HSTATUS_ONOFF, 0, 1000);
199 /* Set the command header base address to CHBA register to tell DMA */
200 out_le32(®->chba, (u32)cmd_hdr & ~0x3);
202 /* Snoop for the command header */
203 val32 = in_le32(®->hcontrol);
204 val32 |= HCONTROL_HDR_SNOOP;
205 out_le32(®->hcontrol, val32);
207 /* Disable all of interrupts */
208 val32 = in_le32(®->hcontrol);
209 val32 &= ~HCONTROL_INT_EN_ALL;
210 out_le32(®->hcontrol, val32);
212 /* Clear all of interrupts */
213 val32 = in_le32(®->hstatus);
214 out_le32(®->hstatus, val32);
216 /* Set the ICC, no interrupt coalescing */
217 out_le32(®->icc, 0x01000000);
219 /* No PM attatched, the SATA device direct connect */
220 out_le32(®->cqpmp, 0);
222 /* Clear SError register */
223 val32 = in_le32(®->serror);
224 out_le32(®->serror, val32);
226 /* Clear CER register */
227 val32 = in_le32(®->cer);
228 out_le32(®->cer, val32);
230 /* Clear DER register */
231 val32 = in_le32(®->der);
232 out_le32(®->der, val32);
234 /* No device detection or initialization action requested */
235 out_le32(®->scontrol, 0x00000300);
237 /* Configure the transport layer, default value */
238 out_le32(®->transcfg, 0x08000016);
240 /* Configure the link layer, default value */
241 out_le32(®->linkcfg, 0x0000ff34);
243 /* Bring the controller online */
244 val32 = in_le32(®->hcontrol);
245 val32 |= HCONTROL_ONOFF;
246 out_le32(®->hcontrol, val32);
250 /* print sata device name */
252 printf("%s ", sata->name);
254 printf(" %s ", sata->name);
256 /* Wait PHY RDY signal changed for 500ms */
257 ata_wait_register(®->hstatus, HSTATUS_PHY_RDY,
258 HSTATUS_PHY_RDY, 500);
261 val32 = in_le32(®->hstatus);
262 if (val32 & HSTATUS_PHY_RDY) {
266 printf("(No RDY)\n\r");
270 /* Wait for signature updated, which is 1st D2H */
271 ata_wait_register(®->hstatus, HSTATUS_SIGNATURE,
272 HSTATUS_SIGNATURE, 10000);
274 if (val32 & HSTATUS_SIGNATURE) {
275 sig = in_le32(®->sig);
276 debug("Signature updated, the sig =%08x\n\r", sig);
277 sata->ata_device_type = ata_dev_classify(sig);
280 /* Check the speed */
281 val32 = in_le32(®->sstatus);
282 if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1)
283 printf("(1.5 Gbps)\n\r");
284 else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2)
285 printf("(3 Gbps)\n\r");
290 /* Hardware reset, like Power-on and COMRESET */
291 void fsl_sata_hardware_reset(u32 reg_base)
293 fsl_sata_reg_t *reg = (fsl_sata_reg_t *)reg_base;
296 /* Disable the SATA interface and put PHY offline */
297 scontrol = in_le32(®->scontrol);
298 scontrol = (scontrol & 0x0f0) | 0x304;
299 out_le32(®->scontrol, scontrol);
301 /* No speed strict */
302 scontrol = in_le32(®->scontrol);
303 scontrol = scontrol & ~0x0f0;
304 out_le32(®->scontrol, scontrol);
306 /* Issue PHY wake/reset, Hardware_reset_asserted */
307 scontrol = in_le32(®->scontrol);
308 scontrol = (scontrol & 0x0f0) | 0x301;
309 out_le32(®->scontrol, scontrol);
313 /* Resume PHY, COMRESET negated, the device initialize hardware
314 * and execute diagnostics, send good status-signature to host,
315 * which is D2H register FIS, and then the device enter idle state.
317 scontrol = in_le32(®->scontrol);
318 scontrol = (scontrol & 0x0f0) | 0x300;
319 out_le32(®->scontrol, scontrol);
325 static void fsl_sata_dump_regs(fsl_sata_reg_t *reg)
327 printf("\n\rSATA: %08x\n\r", (u32)reg);
328 printf("CQR: %08x\n\r", in_le32(®->cqr));
329 printf("CAR: %08x\n\r", in_le32(®->car));
330 printf("CCR: %08x\n\r", in_le32(®->ccr));
331 printf("CER: %08x\n\r", in_le32(®->cer));
332 printf("CQR: %08x\n\r", in_le32(®->cqr));
333 printf("DER: %08x\n\r", in_le32(®->der));
334 printf("CHBA: %08x\n\r", in_le32(®->chba));
335 printf("HStatus: %08x\n\r", in_le32(®->hstatus));
336 printf("HControl: %08x\n\r", in_le32(®->hcontrol));
337 printf("CQPMP: %08x\n\r", in_le32(®->cqpmp));
338 printf("SIG: %08x\n\r", in_le32(®->sig));
339 printf("ICC: %08x\n\r", in_le32(®->icc));
340 printf("SStatus: %08x\n\r", in_le32(®->sstatus));
341 printf("SError: %08x\n\r", in_le32(®->serror));
342 printf("SControl: %08x\n\r", in_le32(®->scontrol));
343 printf("SNotification: %08x\n\r", in_le32(®->snotification));
344 printf("TransCfg: %08x\n\r", in_le32(®->transcfg));
345 printf("TransStatus: %08x\n\r", in_le32(®->transstatus));
346 printf("LinkCfg: %08x\n\r", in_le32(®->linkcfg));
347 printf("LinkCfg1: %08x\n\r", in_le32(®->linkcfg1));
348 printf("LinkCfg2: %08x\n\r", in_le32(®->linkcfg2));
349 printf("LinkStatus: %08x\n\r", in_le32(®->linkstatus));
350 printf("LinkStatus1: %08x\n\r", in_le32(®->linkstatus1));
351 printf("PhyCtrlCfg: %08x\n\r", in_le32(®->phyctrlcfg));
352 printf("SYSPR: %08x\n\r", in_be32(®->syspr));
355 static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
356 int is_ncq, int tag, u8 *buffer, u32 len)
358 cmd_hdr_entry_t *cmd_hdr;
359 cmd_desc_t *cmd_desc;
366 fsl_sata_reg_t *reg = sata->reg_base;
369 /* Check xfer length */
370 if (len > SATA_HC_MAX_XFER_LEN) {
371 printf("max transfer length is 64MB\n\r");
375 /* Setup the command descriptor */
376 cmd_desc = sata->cmd_desc + tag;
378 /* Get the pointer cfis of command descriptor */
379 h2d = (sata_fis_h2d_t *)cmd_desc->cfis;
381 /* Zero the cfis of command descriptor */
382 memset((void *)h2d, 0, SATA_HC_CMD_DESC_CFIS_SIZE);
384 /* Copy the cfis from user to command descriptor */
385 h2d->fis_type = cfis->fis_type;
386 h2d->pm_port_c = cfis->pm_port_c;
387 h2d->command = cfis->command;
389 h2d->features = cfis->features;
390 h2d->features_exp = cfis->features_exp;
392 h2d->lba_low = cfis->lba_low;
393 h2d->lba_mid = cfis->lba_mid;
394 h2d->lba_high = cfis->lba_high;
395 h2d->lba_low_exp = cfis->lba_low_exp;
396 h2d->lba_mid_exp = cfis->lba_mid_exp;
397 h2d->lba_high_exp = cfis->lba_high_exp;
400 h2d->sector_count = cfis->sector_count;
401 h2d->sector_count_exp = cfis->sector_count_exp;
403 h2d->sector_count = (u8)(tag << 3);
406 h2d->device = cfis->device;
407 h2d->control = cfis->control;
409 /* Setup the PRD table */
410 prde = (prd_entry_t *)cmd_desc->prdt;
411 memset((void *)prde, 0, sizeof(struct prdt));
415 for (i = 0; i < SATA_HC_MAX_PRD_DIRECT; i++) {
418 prde->dba = cpu_to_le32((u32)buffer & ~0x3);
419 debug("dba = %08x\n\r", (u32)buffer);
421 if (len < PRD_ENTRY_MAX_XFER_SZ) {
422 ext_c_ddc = PRD_ENTRY_DATA_SNOOP | len;
423 debug("ext_c_ddc1 = %08x, len = %08x\n\r", ext_c_ddc, len);
424 prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
429 ext_c_ddc = PRD_ENTRY_DATA_SNOOP; /* 4M bytes */
430 debug("ext_c_ddc2 = %08x, len = %08x\n\r", ext_c_ddc, len);
431 prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
432 buffer += PRD_ENTRY_MAX_XFER_SZ;
433 len -= PRD_ENTRY_MAX_XFER_SZ;
439 /* Setup the command slot of cmd hdr */
440 cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag];
442 cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3);
444 val32 = prde_count << CMD_HDR_PRD_ENTRY_SHIFT;
445 val32 |= sizeof(sata_fis_h2d_t);
446 cmd_hdr->prde_fis_len = cpu_to_le32(val32);
448 cmd_hdr->ttl = cpu_to_le32(ttl);
451 val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP;
453 val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP | CMD_HDR_ATTR_FPDMA;
456 tag &= CMD_HDR_ATTR_TAG;
459 debug("attribute = %08x\n\r", val32);
460 cmd_hdr->attribute = cpu_to_le32(val32);
462 /* Make sure cmd desc and cmd slot valid before commmand issue */
466 val32 = (u32)(h2d->pm_port_c & 0x0f);
467 out_le32(®->cqpmp, val32);
470 if (ata_wait_register(®->car, (1 << tag), 0, 10000))
471 printf("Wait no active time out\n\r");
474 if (!(in_le32(®->cqr) & (1 << tag))) {
476 out_le32(®->cqr, val32);
479 /* Wait command completed for 10s */
480 if (ata_wait_register(®->ccr, (1 << tag), (1 << tag), 10000)) {
482 printf("Non-NCQ command time out\n\r");
484 printf("NCQ command time out\n\r");
487 val32 = in_le32(®->cer);
491 fsl_sata_dump_sfis((struct sata_fis_d2h *)cmd_desc->sfis);
492 printf("CE at device\n\r");
493 fsl_sata_dump_regs(reg);
494 der = in_le32(®->der);
495 out_le32(®->cer, val32);
496 out_le32(®->der, der);
499 /* Clear complete flags */
500 val32 = in_le32(®->ccr);
501 out_le32(®->ccr, val32);
506 static int fsl_ata_exec_reset_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
507 int tag, u8 *buffer, u32 len)
512 static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
513 enum cmd_type command_type, int tag, u8 *buffer, u32 len)
517 if (tag > SATA_HC_MAX_CMD || tag < 0) {
518 printf("tag is out of range, tag=%d\n\r", tag);
522 switch (command_type) {
524 rc = fsl_ata_exec_ata_cmd(sata, cfis, 0, tag, buffer, len);
527 rc = fsl_ata_exec_reset_cmd(sata, cfis, tag, buffer, len);
530 rc = fsl_ata_exec_ata_cmd(sata, cfis, 1, tag, buffer, len);
533 case CMD_VENDOR_BIST:
535 printf("not support now\n\r");
544 static void fsl_sata_identify(int dev, u16 *id)
546 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
547 struct sata_fis_h2d h2d, *cfis = &h2d;
549 memset(cfis, 0, sizeof(struct sata_fis_h2d));
551 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
552 cfis->pm_port_c = 0x80; /* is command */
553 cfis->command = ATA_CMD_ID_ATA;
555 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
556 ata_swap_buf_le16(id, ATA_ID_WORDS);
559 static void fsl_sata_xfer_mode(int dev, u16 *id)
561 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
563 sata->pio = id[ATA_ID_PIO_MODES];
564 sata->mwdma = id[ATA_ID_MWDMA_MODES];
565 sata->udma = id[ATA_ID_UDMA_MODES];
566 debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio, sata->mwdma, sata->udma);
569 static void fsl_sata_set_features(int dev)
571 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
572 struct sata_fis_h2d h2d, *cfis = &h2d;
575 memset(cfis, 0, sizeof(struct sata_fis_h2d));
577 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
578 cfis->pm_port_c = 0x80; /* is command */
579 cfis->command = ATA_CMD_SET_FEATURES;
580 cfis->features = SETFEATURES_XFER;
582 /* First check the device capablity */
583 udma_cap = (u8)(sata->udma & 0xff);
584 debug("udma_cap %02x\n\r", udma_cap);
586 if (udma_cap == ATA_UDMA6)
587 cfis->sector_count = XFER_UDMA_6;
588 if (udma_cap == ATA_UDMA5)
589 cfis->sector_count = XFER_UDMA_5;
590 if (udma_cap == ATA_UDMA4)
591 cfis->sector_count = XFER_UDMA_4;
592 if (udma_cap == ATA_UDMA3)
593 cfis->sector_count = XFER_UDMA_3;
595 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
598 static u32 fsl_sata_rw_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
600 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
601 struct sata_fis_h2d h2d, *cfis = &h2d;
606 memset(cfis, 0, sizeof(struct sata_fis_h2d));
608 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
609 cfis->pm_port_c = 0x80; /* is command */
610 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
611 cfis->device = ATA_LBA;
613 cfis->device |= (block >> 24) & 0xf;
614 cfis->lba_high = (block >> 16) & 0xff;
615 cfis->lba_mid = (block >> 8) & 0xff;
616 cfis->lba_low = block & 0xff;
617 cfis->sector_count = (u8)(blkcnt & 0xff);
619 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
623 void fsl_sata_flush_cache(int dev)
625 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
626 struct sata_fis_h2d h2d, *cfis = &h2d;
628 memset(cfis, 0, sizeof(struct sata_fis_h2d));
630 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
631 cfis->pm_port_c = 0x80; /* is command */
632 cfis->command = ATA_CMD_FLUSH;
634 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
637 static u32 fsl_sata_rw_cmd_ext(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
639 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
640 struct sata_fis_h2d h2d, *cfis = &h2d;
645 memset(cfis, 0, sizeof(struct sata_fis_h2d));
647 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
648 cfis->pm_port_c = 0x80; /* is command */
650 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
653 cfis->lba_high_exp = (block >> 40) & 0xff;
654 cfis->lba_mid_exp = (block >> 32) & 0xff;
655 cfis->lba_low_exp = (block >> 24) & 0xff;
656 cfis->lba_high = (block >> 16) & 0xff;
657 cfis->lba_mid = (block >> 8) & 0xff;
658 cfis->lba_low = block & 0xff;
659 cfis->device = ATA_LBA;
660 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
661 cfis->sector_count = blkcnt & 0xff;
663 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
667 u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
669 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
670 struct sata_fis_h2d h2d, *cfis = &h2d;
674 if (sata->lba48 != 1) {
675 printf("execute FPDMA command on non-LBA48 hard disk\n\r");
681 memset(cfis, 0, sizeof(struct sata_fis_h2d));
683 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
684 cfis->pm_port_c = 0x80; /* is command */
686 cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
687 : ATA_CMD_FPDMA_READ;
689 cfis->lba_high_exp = (block >> 40) & 0xff;
690 cfis->lba_mid_exp = (block >> 32) & 0xff;
691 cfis->lba_low_exp = (block >> 24) & 0xff;
692 cfis->lba_high = (block >> 16) & 0xff;
693 cfis->lba_mid = (block >> 8) & 0xff;
694 cfis->lba_low = block & 0xff;
696 cfis->device = ATA_LBA;
697 cfis->features_exp = (blkcnt >> 8) & 0xff;
698 cfis->features = blkcnt & 0xff;
700 if (sata->queue_depth >= SATA_HC_MAX_CMD)
701 ncq_channel = SATA_HC_MAX_CMD - 1;
703 ncq_channel = sata->queue_depth - 1;
705 /* Use the latest queue */
706 fsl_sata_exec_cmd(sata, cfis, CMD_NCQ, ncq_channel, buffer, ATA_SECT_SIZE * blkcnt);
710 void fsl_sata_flush_cache_ext(int dev)
712 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
713 struct sata_fis_h2d h2d, *cfis = &h2d;
715 memset(cfis, 0, sizeof(struct sata_fis_h2d));
717 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
718 cfis->pm_port_c = 0x80; /* is command */
719 cfis->command = ATA_CMD_FLUSH_EXT;
721 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
724 /* Software reset, set SRST of the Device Control register */
725 void fsl_sata_software_reset(int dev)
730 static void fsl_sata_init_wcache(int dev, u16 *id)
732 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
734 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
736 if (ata_id_has_flush(id))
738 if (ata_id_has_flush_ext(id))
742 static int fsl_sata_get_wcache(int dev)
744 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
748 static int fsl_sata_get_flush(int dev)
750 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
754 static int fsl_sata_get_flush_ext(int dev)
756 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
757 return sata->flush_ext;
760 u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
761 const void *buffer, int is_write)
771 max_blks = ATA_MAX_SECTORS_LBA48;
773 if (blks > max_blks) {
774 if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
775 fsl_sata_rw_cmd_ext(dev, start, max_blks, addr, is_write);
777 fsl_sata_rw_ncq_cmd(dev, start, max_blks, addr, is_write);
780 addr += ATA_SECT_SIZE * max_blks;
782 if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
783 fsl_sata_rw_cmd_ext(dev, start, blks, addr, is_write);
785 fsl_sata_rw_ncq_cmd(dev, start, blks, addr, is_write);
788 addr += ATA_SECT_SIZE * blks;
795 u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt, const void *buffer,
806 max_blks = ATA_MAX_SECTORS;
808 if (blks > max_blks) {
809 fsl_sata_rw_cmd(dev, start, max_blks, addr, is_write);
812 addr += ATA_SECT_SIZE * max_blks;
814 fsl_sata_rw_cmd(dev, start, blks, addr, is_write);
817 addr += ATA_SECT_SIZE * blks;
825 * SATA interface between low level driver and command layer
827 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
830 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
833 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
835 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
839 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
842 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
845 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
846 if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush_ext(dev))
847 fsl_sata_flush_cache_ext(dev);
849 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
850 if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush(dev))
851 fsl_sata_flush_cache(dev);
856 int scan_sata(int dev)
858 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
859 unsigned char serial[ATA_ID_SERNO_LEN + 1];
860 unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
861 unsigned char product[ATA_ID_PROD_LEN + 1];
865 /* if no detected link */
869 id = (u16 *)malloc(ATA_ID_WORDS * 2);
871 printf("id malloc failed\n\r");
875 /* Identify device to get information */
876 fsl_sata_identify(dev, id);
879 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
880 memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
882 /* Firmware version */
883 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
884 memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
887 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
888 memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
891 n_sectors = ata_id_n_sectors(id);
892 sata_dev_desc[dev].lba = (u32)n_sectors;
895 /* Check if support LBA48 */
896 if (ata_id_has_lba48(id)) {
898 debug("Device support LBA48\n\r");
900 debug("Device supports LBA28\n\r");
903 /* Get the NCQ queue depth from device */
904 sata->queue_depth = ata_id_queue_depth(id);
906 /* Get the xfer mode from device */
907 fsl_sata_xfer_mode(dev, id);
909 /* Get the write cache status from device */
910 fsl_sata_init_wcache(dev, id);
912 /* Set the xfer mode to highest speed */
913 fsl_sata_set_features(dev);
915 fsl_sata_identify(dev, id);