drivers/char/drm/mga_drv.h

   1 /* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
   2  * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
   3  *
   4  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All rights reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  25  * OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #ifndef __MGA_DRV_H__
  32 #define __MGA_DRV_H__
  33
  34 /* General customization:
  35  */
  36
  37 #define DRIVER_AUTHOR           "Gareth Hughes, VA Linux Systems Inc."
  38
  39 #define DRIVER_NAME             "mga"
  40 #define DRIVER_DESC             "Matrox G200/G400"
  41 #define DRIVER_DATE             "20021029"
  42
  43 #define DRIVER_MAJOR            3
  44 #define DRIVER_MINOR            1
  45 #define DRIVER_PATCHLEVEL       0
  46
  47 typedef struct drm_mga_primary_buffer {
  48         u8 *start;
  49         u8 *end;
  50         int size;
  51
  52         u32 tail;
  53         int space;
  54         volatile long wrapped;
  55
  56         volatile u32 *status;
  57
  58         u32 last_flush;
  59         u32 last_wrap;
  60
  61         u32 high_mark;
  62 } drm_mga_primary_buffer_t;
  63
  64 typedef struct drm_mga_freelist {
  65         struct drm_mga_freelist *next;
  66         struct drm_mga_freelist *prev;
  67         drm_mga_age_t age;
  68         drm_buf_t *buf;
  69 } drm_mga_freelist_t;
  70
  71 typedef struct {
  72         drm_mga_freelist_t *list_entry;
  73         int discard;
  74         int dispatched;
  75 } drm_mga_buf_priv_t;
  76
  77 typedef struct drm_mga_private {
  78         drm_mga_primary_buffer_t prim;
  79         drm_mga_sarea_t *sarea_priv;
  80
  81         drm_mga_freelist_t *head;
  82         drm_mga_freelist_t *tail;
  83
  84         unsigned int warp_pipe;
  85         unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
  86
  87         int chipset;
  88         int usec_timeout;
  89
  90         u32 clear_cmd;
  91         u32 maccess;
  92
  93         unsigned int fb_cpp;
  94         unsigned int front_offset;
  95         unsigned int front_pitch;
  96         unsigned int back_offset;
  97         unsigned int back_pitch;
  98
  99         unsigned int depth_cpp;
 100         unsigned int depth_offset;
 101         unsigned int depth_pitch;
 102
 103         unsigned int texture_offset;
 104         unsigned int texture_size;
 105
 106         drm_local_map_t *sarea;
 107         drm_local_map_t *mmio;
 108         drm_local_map_t *status;
 109         drm_local_map_t *warp;
 110         drm_local_map_t *primary;
 111         drm_local_map_t *buffers;
 112         drm_local_map_t *agp_textures;
 113 } drm_mga_private_t;
 114
 115                                 /* mga_dma.c */
 116 extern int mga_dma_init( DRM_IOCTL_ARGS );
 117 extern int mga_dma_flush( DRM_IOCTL_ARGS );
 118 extern int mga_dma_reset( DRM_IOCTL_ARGS );
 119 extern int mga_dma_buffers( DRM_IOCTL_ARGS );
 120 extern void mga_driver_pretakedown(drm_device_t *dev);
 121 extern int mga_driver_dma_quiescent(drm_device_t *dev);
 122
 123 extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv );
 124
 125 extern void mga_do_dma_flush( drm_mga_private_t *dev_priv );
 126 extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv );
 127 extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv );
 128
 129 extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf );
 130
 131                                 /* mga_warp.c */
 132 extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv );
 133 extern int mga_warp_init( drm_mga_private_t *dev_priv );
 134
 135 extern int mga_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
 136 extern irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS );
 137 extern void mga_driver_irq_preinstall( drm_device_t *dev );
 138 extern void mga_driver_irq_postinstall( drm_device_t *dev );
 139 extern void mga_driver_irq_uninstall( drm_device_t *dev );
 140 extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
 141                              unsigned long arg);
 142
 143 #define mga_flush_write_combine()       DRM_WRITEMEMORYBARRIER()
 144
 145 #if defined(__linux__) && defined(__alpha__)
 146 #define MGA_BASE( reg )         ((unsigned long)(dev_priv->mmio->handle))
 147 #define MGA_ADDR( reg )         (MGA_BASE(reg) + reg)
 148
 149 #define MGA_DEREF( reg )        *(volatile u32 *)MGA_ADDR( reg )
 150 #define MGA_DEREF8( reg )       *(volatile u8 *)MGA_ADDR( reg )
 151
 152 #define MGA_READ( reg )         (_MGA_READ((u32 *)MGA_ADDR(reg)))
 153 #define MGA_READ8( reg )        (_MGA_READ((u8 *)MGA_ADDR(reg)))
 154 #define MGA_WRITE( reg, val )   do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0)
 155 #define MGA_WRITE8( reg, val )  do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0)
 156
 157 static inline u32 _MGA_READ(u32 *addr)
 158 {
 159         DRM_MEMORYBARRIER();
 160         return *(volatile u32 *)addr;
 161 }
 162 #else
 163 #define MGA_READ8( reg )        DRM_READ8(dev_priv->mmio, (reg))
 164 #define MGA_READ( reg )         DRM_READ32(dev_priv->mmio, (reg))
 165 #define MGA_WRITE8( reg, val )  DRM_WRITE8(dev_priv->mmio, (reg), (val))
 166 #define MGA_WRITE( reg, val )   DRM_WRITE32(dev_priv->mmio, (reg), (val))
 167 #endif
 168
 169 #define DWGREG0         0x1c00
 170 #define DWGREG0_END     0x1dff
 171 #define DWGREG1         0x2c00
 172 #define DWGREG1_END     0x2dff
 173
 174 #define ISREG0(r)       (r >= DWGREG0 && r <= DWGREG0_END)
 175 #define DMAREG0(r)      (u8)((r - DWGREG0) >> 2)
 176 #define DMAREG1(r)      (u8)(((r - DWGREG1) >> 2) | 0x80)
 177 #define DMAREG(r)       (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
 178
 179
 180
 181 /* ================================================================
 182  * Helper macross...
 183  */
 184
 185 #define MGA_EMIT_STATE( dev_priv, dirty )                               \
 186 do {                                                                    \
 187         if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) {                        \
 188                 if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {        \
 189                         mga_g400_emit_state( dev_priv );                \
 190                 } else {                                                \
 191                         mga_g200_emit_state( dev_priv );                \
 192                 }                                                       \
 193         }                                                               \
 194 } while (0)
 195
 196 #define WRAP_TEST_WITH_RETURN( dev_priv )                               \
 197 do {                                                                    \
 198         if ( test_bit( 0, &dev_priv->prim.wrapped ) ) {                 \
 199                 if ( mga_is_idle( dev_priv ) ) {                        \
 200                         mga_do_dma_wrap_end( dev_priv );                \
 201                 } else if ( dev_priv->prim.space <                      \
 202                             dev_priv->prim.high_mark ) {                \
 203                         if ( MGA_DMA_DEBUG )                            \
 204                                 DRM_INFO( "%s: wrap...\n", __FUNCTION__ );      \
 205                         return DRM_ERR(EBUSY);                  \
 206                 }                                                       \
 207         }                                                               \
 208 } while (0)
 209
 210 #define WRAP_WAIT_WITH_RETURN( dev_priv )                               \
 211 do {                                                                    \
 212         if ( test_bit( 0, &dev_priv->prim.wrapped ) ) {                 \
 213                 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) {           \
 214                         if ( MGA_DMA_DEBUG )                            \
 215                                 DRM_INFO( "%s: wrap...\n", __FUNCTION__ );      \
 216                         return DRM_ERR(EBUSY);                  \
 217                 }                                                       \
 218                 mga_do_dma_wrap_end( dev_priv );                        \
 219         }                                                               \
 220 } while (0)
 221
 222
 223 /* ================================================================
 224  * Primary DMA command stream
 225  */
 226
 227 #define MGA_VERBOSE     0
 228
 229 #define DMA_LOCALS      unsigned int write; volatile u8 *prim;
 230
 231 #define DMA_BLOCK_SIZE  (5 * sizeof(u32))
 232
 233 #define BEGIN_DMA( n )                                                  \
 234 do {                                                                    \
 235         if ( MGA_VERBOSE ) {                                            \
 236                 DRM_INFO( "BEGIN_DMA( %d ) in %s\n",                    \
 237                           (n), __FUNCTION__ );                          \
 238                 DRM_INFO( "   space=0x%x req=0x%Zx\n",                  \
 239                           dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \
 240         }                                                               \
 241         prim = dev_priv->prim.start;                                    \
 242         write = dev_priv->prim.tail;                                    \
 243 } while (0)
 244
 245 #define BEGIN_DMA_WRAP()                                                \
 246 do {                                                                    \
 247         if ( MGA_VERBOSE ) {                                            \
 248                 DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ );                \
 249                 DRM_INFO( "   space=0x%x\n", dev_priv->prim.space );    \
 250         }                                                               \
 251         prim = dev_priv->prim.start;                                    \
 252         write = dev_priv->prim.tail;                                    \
 253 } while (0)
 254
 255 #define ADVANCE_DMA()                                                   \
 256 do {                                                                    \
 257         dev_priv->prim.tail = write;                                    \
 258         if ( MGA_VERBOSE ) {                                            \
 259                 DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n",        \
 260                           write, dev_priv->prim.space );                \
 261         }                                                               \
 262 } while (0)
 263
 264 #define FLUSH_DMA()                                                     \
 265 do {                                                                    \
 266         if ( 0 ) {                                                      \
 267                 DRM_INFO( "%s:\n", __FUNCTION__ );                              \
 268                 DRM_INFO( "   tail=0x%06x head=0x%06lx\n",              \
 269                           dev_priv->prim.tail,                          \
 270                           MGA_READ( MGA_PRIMADDRESS ) -                 \
 271                           dev_priv->primary->offset );                  \
 272         }                                                               \
 273         if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) {                \
 274                 if ( dev_priv->prim.space <                             \
 275                      dev_priv->prim.high_mark ) {                       \
 276                         mga_do_dma_wrap_start( dev_priv );              \
 277                 } else {                                                \
 278                         mga_do_dma_flush( dev_priv );                   \
 279                 }                                                       \
 280         }                                                               \
 281 } while (0)
 282
 283 /* Never use this, always use DMA_BLOCK(...) for primary DMA output.
 284  */
 285 #define DMA_WRITE( offset, val )                                        \
 286 do {                                                                    \
 287         if ( MGA_VERBOSE ) {                                            \
 288                 DRM_INFO( "   DMA_WRITE( 0x%08x ) at 0x%04Zx\n",        \
 289                           (u32)(val), write + (offset) * sizeof(u32) ); \
 290         }                                                               \
 291         *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
 292 } while (0)
 293
 294 #define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 )     \
 295 do {                                                                    \
 296         DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) |                          \
 297                        (DMAREG( reg1 ) << 8) |                          \
 298                        (DMAREG( reg2 ) << 16) |                         \
 299                        (DMAREG( reg3 ) << 24)) );                       \
 300         DMA_WRITE( 1, val0 );                                           \
 301         DMA_WRITE( 2, val1 );                                           \
 302         DMA_WRITE( 3, val2 );                                           \
 303         DMA_WRITE( 4, val3 );                                           \
 304         write += DMA_BLOCK_SIZE;                                        \
 305 } while (0)
 306
 307
 308 /* Buffer aging via primary DMA stream head pointer.
 309  */
 310
 311 #define SET_AGE( age, h, w )                                            \
 312 do {                                                                    \
 313         (age)->head = h;                                                \
 314         (age)->wrap = w;                                                \
 315 } while (0)
 316
 317 #define TEST_AGE( age, h, w )           ( (age)->wrap < w ||            \
 318                                           ( (age)->wrap == w &&         \
 319                                             (age)->head < h ) )
 320
 321 #define AGE_BUFFER( buf_priv )                                          \
 322 do {                                                                    \
 323         drm_mga_freelist_t *entry = (buf_priv)->list_entry;             \
 324         if ( (buf_priv)->dispatched ) {                                 \
 325                 entry->age.head = (dev_priv->prim.tail +                \
 326                                    dev_priv->primary->offset);          \
 327                 entry->age.wrap = dev_priv->sarea_priv->last_wrap;      \
 328         } else {                                                        \
 329                 entry->age.head = 0;                                    \
 330                 entry->age.wrap = 0;                                    \
 331         }                                                               \
 332 } while (0)
 333
 334
 335 #define MGA_ENGINE_IDLE_MASK            (MGA_SOFTRAPEN |                \
 336                                          MGA_DWGENGSTS |                \
 337                                          MGA_ENDPRDMASTS)
 338 #define MGA_DMA_IDLE_MASK               (MGA_SOFTRAPEN |                \
 339                                          MGA_ENDPRDMASTS)
 340
 341 #define MGA_DMA_DEBUG                   0
 342
 343
 344
 345 /* A reduced set of the mga registers.
 346  */
 347 #define MGA_CRTC_INDEX                  0x1fd4
 348 #define MGA_CRTC_DATA                   0x1fd5
 349
 350 /* CRTC11 */
 351 #define MGA_VINTCLR                     (1 << 4)
 352 #define MGA_VINTEN                      (1 << 5)
 353
 354 #define MGA_ALPHACTRL                   0x2c7c
 355 #define MGA_AR0                         0x1c60
 356 #define MGA_AR1                         0x1c64
 357 #define MGA_AR2                         0x1c68
 358 #define MGA_AR3                         0x1c6c
 359 #define MGA_AR4                         0x1c70
 360 #define MGA_AR5                         0x1c74
 361 #define MGA_AR6                         0x1c78
 362
 363 #define MGA_CXBNDRY                     0x1c80
 364 #define MGA_CXLEFT                      0x1ca0
 365 #define MGA_CXRIGHT                     0x1ca4
 366
 367 #define MGA_DMAPAD                      0x1c54
 368 #define MGA_DSTORG                      0x2cb8
 369 #define MGA_DWGCTL                      0x1c00
 370 #       define MGA_OPCOD_MASK                   (15 << 0)
 371 #       define MGA_OPCOD_TRAP                   (4 << 0)
 372 #       define MGA_OPCOD_TEXTURE_TRAP           (6 << 0)
 373 #       define MGA_OPCOD_BITBLT                 (8 << 0)
 374 #       define MGA_OPCOD_ILOAD                  (9 << 0)
 375 #       define MGA_ATYPE_MASK                   (7 << 4)
 376 #       define MGA_ATYPE_RPL                    (0 << 4)
 377 #       define MGA_ATYPE_RSTR                   (1 << 4)
 378 #       define MGA_ATYPE_ZI                     (3 << 4)
 379 #       define MGA_ATYPE_BLK                    (4 << 4)
 380 #       define MGA_ATYPE_I                      (7 << 4)
 381 #       define MGA_LINEAR                       (1 << 7)
 382 #       define MGA_ZMODE_MASK                   (7 << 8)
 383 #       define MGA_ZMODE_NOZCMP                 (0 << 8)
 384 #       define MGA_ZMODE_ZE                     (2 << 8)
 385 #       define MGA_ZMODE_ZNE                    (3 << 8)
 386 #       define MGA_ZMODE_ZLT                    (4 << 8)
 387 #       define MGA_ZMODE_ZLTE                   (5 << 8)
 388 #       define MGA_ZMODE_ZGT                    (6 << 8)
 389 #       define MGA_ZMODE_ZGTE                   (7 << 8)
 390 #       define MGA_SOLID                        (1 << 11)
 391 #       define MGA_ARZERO                       (1 << 12)
 392 #       define MGA_SGNZERO                      (1 << 13)
 393 #       define MGA_SHIFTZERO                    (1 << 14)
 394 #       define MGA_BOP_MASK                     (15 << 16)
 395 #       define MGA_BOP_ZERO                     (0 << 16)
 396 #       define MGA_BOP_DST                      (10 << 16)
 397 #       define MGA_BOP_SRC                      (12 << 16)
 398 #       define MGA_BOP_ONE                      (15 << 16)
 399 #       define MGA_TRANS_SHIFT                  20
 400 #       define MGA_TRANS_MASK                   (15 << 20)
 401 #       define MGA_BLTMOD_MASK                  (15 << 25)
 402 #       define MGA_BLTMOD_BMONOLEF              (0 << 25)
 403 #       define MGA_BLTMOD_BMONOWF               (4 << 25)
 404 #       define MGA_BLTMOD_PLAN                  (1 << 25)
 405 #       define MGA_BLTMOD_BFCOL                 (2 << 25)
 406 #       define MGA_BLTMOD_BU32BGR               (3 << 25)
 407 #       define MGA_BLTMOD_BU32RGB               (7 << 25)
 408 #       define MGA_BLTMOD_BU24BGR               (11 << 25)
 409 #       define MGA_BLTMOD_BU24RGB               (15 << 25)
 410 #       define MGA_PATTERN                      (1 << 29)
 411 #       define MGA_TRANSC                       (1 << 30)
 412 #       define MGA_CLIPDIS                      (1 << 31)
 413 #define MGA_DWGSYNC                     0x2c4c
 414
 415 #define MGA_FCOL                        0x1c24
 416 #define MGA_FIFOSTATUS                  0x1e10
 417 #define MGA_FOGCOL                      0x1cf4
 418 #define MGA_FXBNDRY                     0x1c84
 419 #define MGA_FXLEFT                      0x1ca8
 420 #define MGA_FXRIGHT                     0x1cac
 421
 422 #define MGA_ICLEAR                      0x1e18
 423 #       define MGA_SOFTRAPICLR                  (1 << 0)
 424 #       define MGA_VLINEICLR                    (1 << 5)
 425 #define MGA_IEN                         0x1e1c
 426 #       define MGA_SOFTRAPIEN                   (1 << 0)
 427 #       define MGA_VLINEIEN                     (1 << 5)
 428
 429 #define MGA_LEN                         0x1c5c
 430
 431 #define MGA_MACCESS                     0x1c04
 432
 433 #define MGA_PITCH                       0x1c8c
 434 #define MGA_PLNWT                       0x1c1c
 435 #define MGA_PRIMADDRESS                 0x1e58
 436 #       define MGA_DMA_GENERAL                  (0 << 0)
 437 #       define MGA_DMA_BLIT                     (1 << 0)
 438 #       define MGA_DMA_VECTOR                   (2 << 0)
 439 #       define MGA_DMA_VERTEX                   (3 << 0)
 440 #define MGA_PRIMEND                     0x1e5c
 441 #       define MGA_PRIMNOSTART                  (1 << 0)
 442 #       define MGA_PAGPXFER                     (1 << 1)
 443 #define MGA_PRIMPTR                     0x1e50
 444 #       define MGA_PRIMPTREN0                   (1 << 0)
 445 #       define MGA_PRIMPTREN1                   (1 << 1)
 446
 447 #define MGA_RST                         0x1e40
 448 #       define MGA_SOFTRESET                    (1 << 0)
 449 #       define MGA_SOFTEXTRST                   (1 << 1)
 450
 451 #define MGA_SECADDRESS                  0x2c40
 452 #define MGA_SECEND                      0x2c44
 453 #define MGA_SETUPADDRESS                0x2cd0
 454 #define MGA_SETUPEND                    0x2cd4
 455 #define MGA_SGN                         0x1c58
 456 #define MGA_SOFTRAP                     0x2c48
 457 #define MGA_SRCORG                      0x2cb4
 458 #       define MGA_SRMMAP_MASK                  (1 << 0)
 459 #       define MGA_SRCMAP_FB                    (0 << 0)
 460 #       define MGA_SRCMAP_SYSMEM                (1 << 0)
 461 #       define MGA_SRCACC_MASK                  (1 << 1)
 462 #       define MGA_SRCACC_PCI                   (0 << 1)
 463 #       define MGA_SRCACC_AGP                   (1 << 1)
 464 #define MGA_STATUS                      0x1e14
 465 #       define MGA_SOFTRAPEN                    (1 << 0)
 466 #       define MGA_VSYNCPEN                     (1 << 4)
 467 #       define MGA_VLINEPEN                     (1 << 5)
 468 #       define MGA_DWGENGSTS                    (1 << 16)
 469 #       define MGA_ENDPRDMASTS                  (1 << 17)
 470 #define MGA_STENCIL                     0x2cc8
 471 #define MGA_STENCILCTL                  0x2ccc
 472
 473 #define MGA_TDUALSTAGE0                 0x2cf8
 474 #define MGA_TDUALSTAGE1                 0x2cfc
 475 #define MGA_TEXBORDERCOL                0x2c5c
 476 #define MGA_TEXCTL                      0x2c30
 477 #define MGA_TEXCTL2                     0x2c3c
 478 #       define MGA_DUALTEX                      (1 << 7)
 479 #       define MGA_G400_TC2_MAGIC               (1 << 15)
 480 #       define MGA_MAP1_ENABLE                  (1 << 31)
 481 #define MGA_TEXFILTER                   0x2c58
 482 #define MGA_TEXHEIGHT                   0x2c2c
 483 #define MGA_TEXORG                      0x2c24
 484 #       define MGA_TEXORGMAP_MASK               (1 << 0)
 485 #       define MGA_TEXORGMAP_FB                 (0 << 0)
 486 #       define MGA_TEXORGMAP_SYSMEM             (1 << 0)
 487 #       define MGA_TEXORGACC_MASK               (1 << 1)
 488 #       define MGA_TEXORGACC_PCI                (0 << 1)
 489 #       define MGA_TEXORGACC_AGP                (1 << 1)
 490 #define MGA_TEXORG1                     0x2ca4
 491 #define MGA_TEXORG2                     0x2ca8
 492 #define MGA_TEXORG3                     0x2cac
 493 #define MGA_TEXORG4                     0x2cb0
 494 #define MGA_TEXTRANS                    0x2c34
 495 #define MGA_TEXTRANSHIGH                0x2c38
 496 #define MGA_TEXWIDTH                    0x2c28
 497
 498 #define MGA_WACCEPTSEQ                  0x1dd4
 499 #define MGA_WCODEADDR                   0x1e6c
 500 #define MGA_WFLAG                       0x1dc4
 501 #define MGA_WFLAG1                      0x1de0
 502 #define MGA_WFLAGNB                     0x1e64
 503 #define MGA_WFLAGNB1                    0x1e08
 504 #define MGA_WGETMSB                     0x1dc8
 505 #define MGA_WIADDR                      0x1dc0
 506 #define MGA_WIADDR2                     0x1dd8
 507 #       define MGA_WMODE_SUSPEND                (0 << 0)
 508 #       define MGA_WMODE_RESUME                 (1 << 0)
 509 #       define MGA_WMODE_JUMP                   (2 << 0)
 510 #       define MGA_WMODE_START                  (3 << 0)
 511 #       define MGA_WAGP_ENABLE                  (1 << 2)
 512 #define MGA_WMISC                       0x1e70
 513 #       define MGA_WUCODECACHE_ENABLE           (1 << 0)
 514 #       define MGA_WMASTER_ENABLE               (1 << 1)
 515 #       define MGA_WCACHEFLUSH_ENABLE           (1 << 3)
 516 #define MGA_WVRTXSZ                     0x1dcc
 517
 518 #define MGA_YBOT                        0x1c9c
 519 #define MGA_YDST                        0x1c90
 520 #define MGA_YDSTLEN                     0x1c88
 521 #define MGA_YDSTORG                     0x1c94
 522 #define MGA_YTOP                        0x1c98
 523
 524 #define MGA_ZORG                        0x1c0c
 525
 526 /* This finishes the current batch of commands
 527  */
 528 #define MGA_EXEC                        0x0100
 529
 530 /* Warp registers
 531  */
 532 #define MGA_WR0                         0x2d00
 533 #define MGA_WR1                         0x2d04
 534 #define MGA_WR2                         0x2d08
 535 #define MGA_WR3                         0x2d0c
 536 #define MGA_WR4                         0x2d10
 537 #define MGA_WR5                         0x2d14
 538 #define MGA_WR6                         0x2d18
 539 #define MGA_WR7                         0x2d1c
 540 #define MGA_WR8                         0x2d20
 541 #define MGA_WR9                         0x2d24
 542 #define MGA_WR10                        0x2d28
 543 #define MGA_WR11                        0x2d2c
 544 #define MGA_WR12                        0x2d30
 545 #define MGA_WR13                        0x2d34
 546 #define MGA_WR14                        0x2d38
 547 #define MGA_WR15                        0x2d3c
 548 #define MGA_WR16                        0x2d40
 549 #define MGA_WR17                        0x2d44
 550 #define MGA_WR18                        0x2d48
 551 #define MGA_WR19                        0x2d4c
 552 #define MGA_WR20                        0x2d50
 553 #define MGA_WR21                        0x2d54
 554 #define MGA_WR22                        0x2d58
 555 #define MGA_WR23                        0x2d5c
 556 #define MGA_WR24                        0x2d60
 557 #define MGA_WR25                        0x2d64
 558 #define MGA_WR26                        0x2d68
 559 #define MGA_WR27                        0x2d6c
 560 #define MGA_WR28                        0x2d70
 561 #define MGA_WR29                        0x2d74
 562 #define MGA_WR30                        0x2d78
 563 #define MGA_WR31                        0x2d7c
 564 #define MGA_WR32                        0x2d80
 565 #define MGA_WR33                        0x2d84
 566 #define MGA_WR34                        0x2d88
 567 #define MGA_WR35                        0x2d8c
 568 #define MGA_WR36                        0x2d90
 569 #define MGA_WR37                        0x2d94
 570 #define MGA_WR38                        0x2d98
 571 #define MGA_WR39                        0x2d9c
 572 #define MGA_WR40                        0x2da0
 573 #define MGA_WR41                        0x2da4
 574 #define MGA_WR42                        0x2da8
 575 #define MGA_WR43                        0x2dac
 576 #define MGA_WR44                        0x2db0
 577 #define MGA_WR45                        0x2db4
 578 #define MGA_WR46                        0x2db8
 579 #define MGA_WR47                        0x2dbc
 580 #define MGA_WR48                        0x2dc0
 581 #define MGA_WR49                        0x2dc4
 582 #define MGA_WR50                        0x2dc8
 583 #define MGA_WR51                        0x2dcc
 584 #define MGA_WR52                        0x2dd0
 585 #define MGA_WR53                        0x2dd4
 586 #define MGA_WR54                        0x2dd8
 587 #define MGA_WR55                        0x2ddc
 588 #define MGA_WR56                        0x2de0
 589 #define MGA_WR57                        0x2de4
 590 #define MGA_WR58                        0x2de8
 591 #define MGA_WR59                        0x2dec
 592 #define MGA_WR60                        0x2df0
 593 #define MGA_WR61                        0x2df4
 594 #define MGA_WR62                        0x2df8
 595 #define MGA_WR63                        0x2dfc
 596 #       define MGA_G400_WR_MAGIC                (1 << 6)
 597 #       define MGA_G400_WR56_MAGIC              0x46480000      /* 12800.0f */
 598
 599
 600 #define MGA_ILOAD_ALIGN         64
 601 #define MGA_ILOAD_MASK          (MGA_ILOAD_ALIGN - 1)
 602
 603 #define MGA_DWGCTL_FLUSH        (MGA_OPCOD_TEXTURE_TRAP |               \
 604                                  MGA_ATYPE_I |                          \
 605                                  MGA_ZMODE_NOZCMP |                     \
 606                                  MGA_ARZERO |                           \
 607                                  MGA_SGNZERO |                          \
 608                                  MGA_BOP_SRC |                          \
 609                                  (15 << MGA_TRANS_SHIFT))
 610
 611 #define MGA_DWGCTL_CLEAR        (MGA_OPCOD_TRAP |                       \
 612                                  MGA_ZMODE_NOZCMP |                     \
 613                                  MGA_SOLID |                            \
 614                                  MGA_ARZERO |                           \
 615                                  MGA_SGNZERO |                          \
 616                                  MGA_SHIFTZERO |                        \
 617                                  MGA_BOP_SRC |                          \
 618                                  (0 << MGA_TRANS_SHIFT) |               \
 619                                  MGA_BLTMOD_BMONOLEF |                  \
 620                                  MGA_TRANSC |                           \
 621                                  MGA_CLIPDIS)
 622
 623 #define MGA_DWGCTL_COPY         (MGA_OPCOD_BITBLT |                     \
 624                                  MGA_ATYPE_RPL |                        \
 625                                  MGA_SGNZERO |                          \
 626                                  MGA_SHIFTZERO |                        \
 627                                  MGA_BOP_SRC |                          \
 628                                  (0 << MGA_TRANS_SHIFT) |               \
 629                                  MGA_BLTMOD_BFCOL |                     \
 630                                  MGA_CLIPDIS)
 631
 632 /* Simple idle test.
 633  */
 634 static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv )
 635 {
 636         u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
 637         return ( status == MGA_ENDPRDMASTS );
 638 }
 639
 640 #endif