2 * Copyright (C) 2004 IBM Corporation
5 * Leendert van Doorn <leendert@watson.ibm.com>
6 * Dave Safford <safford@watson.ibm.com>
7 * Reiner Sailer <sailer@watson.ibm.com>
8 * Kylene Hall <kjhall@us.ibm.com>
10 * Maintained by: <tpmdd_devel@lists.sourceforge.net>
12 * Device driver for TCG/TCPA TPM (trusted platform module).
13 * Specifications at www.trustedcomputinggroup.org
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation, version 2 of the
24 /* National definitions */
25 #define TPM_NSC_BASE 0x360
26 #define TPM_NSC_IRQ 0x07
28 #define NSC_LDN_INDEX 0x07
29 #define NSC_SID_INDEX 0x20
30 #define NSC_LDC_INDEX 0x30
31 #define NSC_DIO_INDEX 0x60
32 #define NSC_CIO_INDEX 0x62
33 #define NSC_IRQ_INDEX 0x70
34 #define NSC_ITS_INDEX 0x71
36 #define NSC_STATUS 0x01
37 #define NSC_COMMAND 0x01
41 #define NSC_STATUS_OBF 0x01 /* output buffer full */
42 #define NSC_STATUS_IBF 0x02 /* input buffer full */
43 #define NSC_STATUS_F0 0x04 /* F0 */
44 #define NSC_STATUS_A2 0x08 /* A2 */
45 #define NSC_STATUS_RDY 0x10 /* ready to receive command */
46 #define NSC_STATUS_IBR 0x20 /* ready to receive data */
49 #define NSC_COMMAND_NORMAL 0x01 /* normal mode */
50 #define NSC_COMMAND_EOC 0x03
51 #define NSC_COMMAND_CANCEL 0x22
54 * Wait for a certain status to appear
56 static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data)
60 /* status immediately available check */
61 *data = inb(chip->vendor->base + NSC_STATUS);
62 if ((*data & mask) == val)
66 stop = jiffies + 10 * HZ;
69 *data = inb(chip->vendor->base + 1);
70 if ((*data & mask) == val)
73 while (time_before(jiffies, stop));
78 static int nsc_wait_for_ready(struct tpm_chip *chip)
83 /* status immediately available check */
84 status = inb(chip->vendor->base + NSC_STATUS);
85 if (status & NSC_STATUS_OBF)
86 status = inb(chip->vendor->base + NSC_DATA);
87 if (status & NSC_STATUS_RDY)
94 status = inb(chip->vendor->base + NSC_STATUS);
95 if (status & NSC_STATUS_OBF)
96 status = inb(chip->vendor->base + NSC_DATA);
97 if (status & NSC_STATUS_RDY)
100 while (time_before(jiffies, stop));
102 dev_info(&chip->pci_dev->dev, "wait for ready failed\n");
107 static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count)
117 if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) {
118 dev_err(&chip->pci_dev->dev, "F0 timeout\n");
122 inb(chip->vendor->base + NSC_DATA)) != NSC_COMMAND_NORMAL) {
123 dev_err(&chip->pci_dev->dev, "not in normal mode (0x%x)\n",
128 /* read the whole packet */
129 for (p = buffer; p < &buffer[count]; p++) {
131 (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) {
132 dev_err(&chip->pci_dev->dev,
133 "OBF timeout (while reading data)\n");
136 if (data & NSC_STATUS_F0)
138 *p = inb(chip->vendor->base + NSC_DATA);
141 if ((data & NSC_STATUS_F0) == 0) {
142 dev_err(&chip->pci_dev->dev, "F0 not set\n");
145 if ((data = inb(chip->vendor->base + NSC_DATA)) != NSC_COMMAND_EOC) {
146 dev_err(&chip->pci_dev->dev,
147 "expected end of command(0x%x)\n", data);
151 native_size = (__force __be32 *) (buf + 2);
152 size = be32_to_cpu(*native_size);
160 static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count)
166 * If we hit the chip with back to back commands it locks up
167 * and never set IBF. Hitting it with this "hammer" seems to
168 * fix it. Not sure why this is needed, we followed the flow
169 * chart in the manual to the letter.
171 outb(NSC_COMMAND_CANCEL, chip->vendor->base + NSC_COMMAND);
173 if (nsc_wait_for_ready(chip) != 0)
176 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
177 dev_err(&chip->pci_dev->dev, "IBF timeout\n");
181 outb(NSC_COMMAND_NORMAL, chip->vendor->base + NSC_COMMAND);
182 if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) {
183 dev_err(&chip->pci_dev->dev, "IBR timeout\n");
187 for (i = 0; i < count; i++) {
188 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
189 dev_err(&chip->pci_dev->dev,
190 "IBF timeout (while writing data)\n");
193 outb(buf[i], chip->vendor->base + NSC_DATA);
196 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
197 dev_err(&chip->pci_dev->dev, "IBF timeout\n");
200 outb(NSC_COMMAND_EOC, chip->vendor->base + NSC_COMMAND);
205 static void tpm_nsc_cancel(struct tpm_chip *chip)
207 outb(NSC_COMMAND_CANCEL, chip->vendor->base + NSC_COMMAND);
210 static struct file_operations nsc_ops = {
211 .owner = THIS_MODULE,
216 .release = tpm_release,
219 static struct tpm_vendor_specific tpm_nsc = {
220 .recv = tpm_nsc_recv,
221 .send = tpm_nsc_send,
222 .cancel = tpm_nsc_cancel,
223 .req_complete_mask = NSC_STATUS_OBF,
224 .req_complete_val = NSC_STATUS_OBF,
225 .base = TPM_NSC_BASE,
226 .miscdev = { .fops = &nsc_ops, },
230 static int __devinit tpm_nsc_init(struct pci_dev *pci_dev,
231 const struct pci_device_id *pci_id)
235 if (pci_enable_device(pci_dev))
238 if (tpm_lpc_bus_init(pci_dev, TPM_NSC_BASE)) {
243 /* verify that it is a National part (SID) */
244 if (tpm_read_index(NSC_SID_INDEX) != 0xEF) {
249 dev_dbg(&pci_dev->dev, "NSC TPM detected\n");
250 dev_dbg(&pci_dev->dev,
251 "NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
252 tpm_read_index(0x07), tpm_read_index(0x20),
253 tpm_read_index(0x27));
254 dev_dbg(&pci_dev->dev,
255 "NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
256 tpm_read_index(0x21), tpm_read_index(0x25),
257 tpm_read_index(0x26), tpm_read_index(0x28));
258 dev_dbg(&pci_dev->dev, "NSC IO Base0 0x%x\n",
259 (tpm_read_index(0x60) << 8) | tpm_read_index(0x61));
260 dev_dbg(&pci_dev->dev, "NSC IO Base1 0x%x\n",
261 (tpm_read_index(0x62) << 8) | tpm_read_index(0x63));
262 dev_dbg(&pci_dev->dev, "NSC Interrupt number and wakeup 0x%x\n",
263 tpm_read_index(0x70));
264 dev_dbg(&pci_dev->dev, "NSC IRQ type select 0x%x\n",
265 tpm_read_index(0x71));
266 dev_dbg(&pci_dev->dev,
267 "NSC DMA channel select0 0x%x, select1 0x%x\n",
268 tpm_read_index(0x74), tpm_read_index(0x75));
269 dev_dbg(&pci_dev->dev,
271 "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
272 tpm_read_index(0xF0), tpm_read_index(0xF1),
273 tpm_read_index(0xF2), tpm_read_index(0xF3),
274 tpm_read_index(0xF4), tpm_read_index(0xF5),
275 tpm_read_index(0xF6), tpm_read_index(0xF7),
276 tpm_read_index(0xF8), tpm_read_index(0xF9));
278 dev_info(&pci_dev->dev,
279 "NSC PC21100 TPM revision %d\n",
280 tpm_read_index(0x27) & 0x1F);
282 if (tpm_read_index(NSC_LDC_INDEX) == 0)
283 dev_info(&pci_dev->dev, ": NSC TPM not active\n");
285 /* select PM channel 1 */
286 tpm_write_index(NSC_LDN_INDEX, 0x12);
287 tpm_read_index(NSC_LDN_INDEX);
289 /* disable the DPM module */
290 tpm_write_index(NSC_LDC_INDEX, 0);
291 tpm_read_index(NSC_LDC_INDEX);
293 /* set the data register base addresses */
294 tpm_write_index(NSC_DIO_INDEX, TPM_NSC_BASE >> 8);
295 tpm_write_index(NSC_DIO_INDEX + 1, TPM_NSC_BASE);
296 tpm_read_index(NSC_DIO_INDEX);
297 tpm_read_index(NSC_DIO_INDEX + 1);
299 /* set the command register base addresses */
300 tpm_write_index(NSC_CIO_INDEX, (TPM_NSC_BASE + 1) >> 8);
301 tpm_write_index(NSC_CIO_INDEX + 1, (TPM_NSC_BASE + 1));
302 tpm_read_index(NSC_DIO_INDEX);
303 tpm_read_index(NSC_DIO_INDEX + 1);
305 /* set the interrupt number to be used for the host interface */
306 tpm_write_index(NSC_IRQ_INDEX, TPM_NSC_IRQ);
307 tpm_write_index(NSC_ITS_INDEX, 0x00);
308 tpm_read_index(NSC_IRQ_INDEX);
310 /* enable the DPM module */
311 tpm_write_index(NSC_LDC_INDEX, 0x01);
312 tpm_read_index(NSC_LDC_INDEX);
314 if ((rc = tpm_register_hardware(pci_dev, &tpm_nsc)) < 0)
320 pci_disable_device(pci_dev);
324 static struct pci_device_id tpm_pci_tbl[] __devinitdata = {
325 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0)},
326 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12)},
327 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0)},
328 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12)},
329 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0)},
330 {PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_LPC)},
334 MODULE_DEVICE_TABLE(pci, tpm_pci_tbl);
336 static struct pci_driver nsc_pci_driver = {
338 .id_table = tpm_pci_tbl,
339 .probe = tpm_nsc_init,
340 .remove = __devexit_p(tpm_remove),
341 .suspend = tpm_pm_suspend,
342 .resume = tpm_pm_resume,
345 static int __init init_nsc(void)
347 return pci_register_driver(&nsc_pci_driver);
350 static void __exit cleanup_nsc(void)
352 pci_unregister_driver(&nsc_pci_driver);
355 module_init(init_nsc);
356 module_exit(cleanup_nsc);
358 MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
359 MODULE_DESCRIPTION("TPM Driver");
360 MODULE_VERSION("2.0");
361 MODULE_LICENSE("GPL");