drivers/clk/sirf/clk-atlas7.c

   1 /*
   2  * Clock tree for CSR SiRFAtlas7
   3  *
   4  * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/bitops.h>
  10 #include <linux/io.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/delay.h>
  13 #include <linux/of_address.h>
  14 #include <linux/reset-controller.h>
  15 #include <linux/slab.h>
  16
  17 #define SIRFSOC_CLKC_MEMPLL_AB_FREQ          0x0000
  18 #define SIRFSOC_CLKC_MEMPLL_AB_SSC           0x0004
  19 #define SIRFSOC_CLKC_MEMPLL_AB_CTRL0         0x0008
  20 #define SIRFSOC_CLKC_MEMPLL_AB_CTRL1         0x000c
  21 #define SIRFSOC_CLKC_MEMPLL_AB_STATUS        0x0010
  22 #define SIRFSOC_CLKC_MEMPLL_AB_SSRAM_ADDR    0x0014
  23 #define SIRFSOC_CLKC_MEMPLL_AB_SSRAM_DATA    0x0018
  24
  25 #define SIRFSOC_CLKC_CPUPLL_AB_FREQ          0x001c
  26 #define SIRFSOC_CLKC_CPUPLL_AB_SSC           0x0020
  27 #define SIRFSOC_CLKC_CPUPLL_AB_CTRL0         0x0024
  28 #define SIRFSOC_CLKC_CPUPLL_AB_CTRL1         0x0028
  29 #define SIRFSOC_CLKC_CPUPLL_AB_STATUS        0x002c
  30
  31 #define SIRFSOC_CLKC_SYS0PLL_AB_FREQ         0x0030
  32 #define SIRFSOC_CLKC_SYS0PLL_AB_SSC          0x0034
  33 #define SIRFSOC_CLKC_SYS0PLL_AB_CTRL0        0x0038
  34 #define SIRFSOC_CLKC_SYS0PLL_AB_CTRL1        0x003c
  35 #define SIRFSOC_CLKC_SYS0PLL_AB_STATUS       0x0040
  36
  37 #define SIRFSOC_CLKC_SYS1PLL_AB_FREQ         0x0044
  38 #define SIRFSOC_CLKC_SYS1PLL_AB_SSC          0x0048
  39 #define SIRFSOC_CLKC_SYS1PLL_AB_CTRL0        0x004c
  40 #define SIRFSOC_CLKC_SYS1PLL_AB_CTRL1        0x0050
  41 #define SIRFSOC_CLKC_SYS1PLL_AB_STATUS       0x0054
  42
  43 #define SIRFSOC_CLKC_SYS2PLL_AB_FREQ         0x0058
  44 #define SIRFSOC_CLKC_SYS2PLL_AB_SSC          0x005c
  45 #define SIRFSOC_CLKC_SYS2PLL_AB_CTRL0        0x0060
  46 #define SIRFSOC_CLKC_SYS2PLL_AB_CTRL1        0x0064
  47 #define SIRFSOC_CLKC_SYS2PLL_AB_STATUS       0x0068
  48
  49 #define SIRFSOC_CLKC_SYS3PLL_AB_FREQ         0x006c
  50 #define SIRFSOC_CLKC_SYS3PLL_AB_SSC          0x0070
  51 #define SIRFSOC_CLKC_SYS3PLL_AB_CTRL0        0x0074
  52 #define SIRFSOC_CLKC_SYS3PLL_AB_CTRL1        0x0078
  53 #define SIRFSOC_CLKC_SYS3PLL_AB_STATUS       0x007c
  54
  55 #define SIRFSOC_ABPLL_CTRL0_SSEN     0x00001000
  56 #define SIRFSOC_ABPLL_CTRL0_BYPASS   0x00000010
  57 #define SIRFSOC_ABPLL_CTRL0_RESET    0x00000001
  58
  59 #define SIRFSOC_CLKC_AUDIO_DTO_INC           0x0088
  60 #define SIRFSOC_CLKC_DISP0_DTO_INC           0x008c
  61 #define SIRFSOC_CLKC_DISP1_DTO_INC           0x0090
  62
  63 #define SIRFSOC_CLKC_AUDIO_DTO_SRC           0x0094
  64 #define SIRFSOC_CLKC_AUDIO_DTO_ENA           0x0098
  65 #define SIRFSOC_CLKC_AUDIO_DTO_DROFF         0x009c
  66
  67 #define SIRFSOC_CLKC_DISP0_DTO_SRC           0x00a0
  68 #define SIRFSOC_CLKC_DISP0_DTO_ENA           0x00a4
  69 #define SIRFSOC_CLKC_DISP0_DTO_DROFF         0x00a8
  70
  71 #define SIRFSOC_CLKC_DISP1_DTO_SRC           0x00ac
  72 #define SIRFSOC_CLKC_DISP1_DTO_ENA           0x00b0
  73 #define SIRFSOC_CLKC_DISP1_DTO_DROFF         0x00b4
  74
  75 #define SIRFSOC_CLKC_I2S_CLK_SEL             0x00b8
  76 #define SIRFSOC_CLKC_I2S_SEL_STAT            0x00bc
  77
  78 #define SIRFSOC_CLKC_USBPHY_CLKDIV_CFG       0x00c0
  79 #define SIRFSOC_CLKC_USBPHY_CLKDIV_ENA       0x00c4
  80 #define SIRFSOC_CLKC_USBPHY_CLK_SEL          0x00c8
  81 #define SIRFSOC_CLKC_USBPHY_CLK_SEL_STAT     0x00cc
  82
  83 #define SIRFSOC_CLKC_BTSS_CLKDIV_CFG         0x00d0
  84 #define SIRFSOC_CLKC_BTSS_CLKDIV_ENA         0x00d4
  85 #define SIRFSOC_CLKC_BTSS_CLK_SEL            0x00d8
  86 #define SIRFSOC_CLKC_BTSS_CLK_SEL_STAT       0x00dc
  87
  88 #define SIRFSOC_CLKC_RGMII_CLKDIV_CFG        0x00e0
  89 #define SIRFSOC_CLKC_RGMII_CLKDIV_ENA        0x00e4
  90 #define SIRFSOC_CLKC_RGMII_CLK_SEL           0x00e8
  91 #define SIRFSOC_CLKC_RGMII_CLK_SEL_STAT      0x00ec
  92
  93 #define SIRFSOC_CLKC_CPU_CLKDIV_CFG          0x00f0
  94 #define SIRFSOC_CLKC_CPU_CLKDIV_ENA          0x00f4
  95 #define SIRFSOC_CLKC_CPU_CLK_SEL             0x00f8
  96 #define SIRFSOC_CLKC_CPU_CLK_SEL_STAT        0x00fc
  97
  98 #define SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG      0x0100
  99 #define SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA      0x0104
 100 #define SIRFSOC_CLKC_SDPHY01_CLK_SEL         0x0108
 101 #define SIRFSOC_CLKC_SDPHY01_CLK_SEL_STAT    0x010c
 102
 103 #define SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG      0x0110
 104 #define SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA      0x0114
 105 #define SIRFSOC_CLKC_SDPHY23_CLK_SEL         0x0118
 106 #define SIRFSOC_CLKC_SDPHY23_CLK_SEL_STAT    0x011c
 107
 108 #define SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG      0x0120
 109 #define SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA      0x0124
 110 #define SIRFSOC_CLKC_SDPHY45_CLK_SEL         0x0128
 111 #define SIRFSOC_CLKC_SDPHY45_CLK_SEL_STAT    0x012c
 112
 113 #define SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG      0x0130
 114 #define SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA      0x0134
 115 #define SIRFSOC_CLKC_SDPHY67_CLK_SEL         0x0138
 116 #define SIRFSOC_CLKC_SDPHY67_CLK_SEL_STAT    0x013c
 117
 118 #define SIRFSOC_CLKC_CAN_CLKDIV_CFG          0x0140
 119 #define SIRFSOC_CLKC_CAN_CLKDIV_ENA          0x0144
 120 #define SIRFSOC_CLKC_CAN_CLK_SEL             0x0148
 121 #define SIRFSOC_CLKC_CAN_CLK_SEL_STAT        0x014c
 122
 123 #define SIRFSOC_CLKC_DEINT_CLKDIV_CFG        0x0150
 124 #define SIRFSOC_CLKC_DEINT_CLKDIV_ENA        0x0154
 125 #define SIRFSOC_CLKC_DEINT_CLK_SEL           0x0158
 126 #define SIRFSOC_CLKC_DEINT_CLK_SEL_STAT      0x015c
 127
 128 #define SIRFSOC_CLKC_NAND_CLKDIV_CFG         0x0160
 129 #define SIRFSOC_CLKC_NAND_CLKDIV_ENA         0x0164
 130 #define SIRFSOC_CLKC_NAND_CLK_SEL            0x0168
 131 #define SIRFSOC_CLKC_NAND_CLK_SEL_STAT       0x016c
 132
 133 #define SIRFSOC_CLKC_DISP0_CLKDIV_CFG        0x0170
 134 #define SIRFSOC_CLKC_DISP0_CLKDIV_ENA        0x0174
 135 #define SIRFSOC_CLKC_DISP0_CLK_SEL           0x0178
 136 #define SIRFSOC_CLKC_DISP0_CLK_SEL_STAT      0x017c
 137
 138 #define SIRFSOC_CLKC_DISP1_CLKDIV_CFG        0x0180
 139 #define SIRFSOC_CLKC_DISP1_CLKDIV_ENA        0x0184
 140 #define SIRFSOC_CLKC_DISP1_CLK_SEL           0x0188
 141 #define SIRFSOC_CLKC_DISP1_CLK_SEL_STAT      0x018c
 142
 143 #define SIRFSOC_CLKC_GPU_CLKDIV_CFG          0x0190
 144 #define SIRFSOC_CLKC_GPU_CLKDIV_ENA          0x0194
 145 #define SIRFSOC_CLKC_GPU_CLK_SEL             0x0198
 146 #define SIRFSOC_CLKC_GPU_CLK_SEL_STAT        0x019c
 147
 148 #define SIRFSOC_CLKC_GNSS_CLKDIV_CFG         0x01a0
 149 #define SIRFSOC_CLKC_GNSS_CLKDIV_ENA         0x01a4
 150 #define SIRFSOC_CLKC_GNSS_CLK_SEL            0x01a8
 151 #define SIRFSOC_CLKC_GNSS_CLK_SEL_STAT       0x01ac
 152
 153 #define SIRFSOC_CLKC_SHARED_DIVIDER_CFG0     0x01b0
 154 #define SIRFSOC_CLKC_SHARED_DIVIDER_CFG1     0x01b4
 155 #define SIRFSOC_CLKC_SHARED_DIVIDER_ENA      0x01b8
 156
 157 #define SIRFSOC_CLKC_SYS_CLK_SEL             0x01bc
 158 #define SIRFSOC_CLKC_SYS_CLK_SEL_STAT        0x01c0
 159 #define SIRFSOC_CLKC_IO_CLK_SEL              0x01c4
 160 #define SIRFSOC_CLKC_IO_CLK_SEL_STAT         0x01c8
 161 #define SIRFSOC_CLKC_G2D_CLK_SEL             0x01cc
 162 #define SIRFSOC_CLKC_G2D_CLK_SEL_STAT        0x01d0
 163 #define SIRFSOC_CLKC_JPENC_CLK_SEL           0x01d4
 164 #define SIRFSOC_CLKC_JPENC_CLK_SEL_STAT      0x01d8
 165 #define SIRFSOC_CLKC_VDEC_CLK_SEL            0x01dc
 166 #define SIRFSOC_CLKC_VDEC_CLK_SEL_STAT       0x01e0
 167 #define SIRFSOC_CLKC_GMAC_CLK_SEL            0x01e4
 168 #define SIRFSOC_CLKC_GMAC_CLK_SEL_STAT       0x01e8
 169 #define SIRFSOC_CLKC_USB_CLK_SEL             0x01ec
 170 #define SIRFSOC_CLKC_USB_CLK_SEL_STAT        0x01f0
 171 #define SIRFSOC_CLKC_KAS_CLK_SEL             0x01f4
 172 #define SIRFSOC_CLKC_KAS_CLK_SEL_STAT        0x01f8
 173 #define SIRFSOC_CLKC_SEC_CLK_SEL             0x01fc
 174 #define SIRFSOC_CLKC_SEC_CLK_SEL_STAT        0x0200
 175 #define SIRFSOC_CLKC_SDR_CLK_SEL             0x0204
 176 #define SIRFSOC_CLKC_SDR_CLK_SEL_STAT        0x0208
 177 #define SIRFSOC_CLKC_VIP_CLK_SEL             0x020c
 178 #define SIRFSOC_CLKC_VIP_CLK_SEL_STAT        0x0210
 179 #define SIRFSOC_CLKC_NOCD_CLK_SEL            0x0214
 180 #define SIRFSOC_CLKC_NOCD_CLK_SEL_STAT       0x0218
 181 #define SIRFSOC_CLKC_NOCR_CLK_SEL            0x021c
 182 #define SIRFSOC_CLKC_NOCR_CLK_SEL_STAT       0x0220
 183 #define SIRFSOC_CLKC_TPIU_CLK_SEL            0x0224
 184 #define SIRFSOC_CLKC_TPIU_CLK_SEL_STAT       0x0228
 185
 186 #define SIRFSOC_CLKC_ROOT_CLK_EN0_SET        0x022c
 187 #define SIRFSOC_CLKC_ROOT_CLK_EN0_CLR        0x0230
 188 #define SIRFSOC_CLKC_ROOT_CLK_EN0_STAT       0x0234
 189 #define SIRFSOC_CLKC_ROOT_CLK_EN1_SET        0x0238
 190 #define SIRFSOC_CLKC_ROOT_CLK_EN1_CLR        0x023c
 191 #define SIRFSOC_CLKC_ROOT_CLK_EN1_STAT       0x0240
 192
 193 #define SIRFSOC_CLKC_LEAF_CLK_EN0_SET        0x0244
 194 #define SIRFSOC_CLKC_LEAF_CLK_EN0_CLR        0x0248
 195 #define SIRFSOC_CLKC_LEAF_CLK_EN0_STAT       0x024c
 196
 197 #define SIRFSOC_CLKC_RSTC_A7_SW_RST          0x0308
 198
 199 #define SIRFSOC_CLKC_LEAF_CLK_EN1_SET        0x04a0
 200 #define SIRFSOC_CLKC_LEAF_CLK_EN2_SET        0x04b8
 201 #define SIRFSOC_CLKC_LEAF_CLK_EN3_SET        0x04d0
 202 #define SIRFSOC_CLKC_LEAF_CLK_EN4_SET        0x04e8
 203 #define SIRFSOC_CLKC_LEAF_CLK_EN5_SET        0x0500
 204 #define SIRFSOC_CLKC_LEAF_CLK_EN6_SET        0x0518
 205 #define SIRFSOC_CLKC_LEAF_CLK_EN7_SET        0x0530
 206 #define SIRFSOC_CLKC_LEAF_CLK_EN8_SET        0x0548
 207
 208
 209 static void __iomem *sirfsoc_clk_vbase;
 210 static struct clk_onecell_data clk_data;
 211
 212 static const struct clk_div_table pll_div_table[] = {
 213         { .val = 0, .div = 1 },
 214         { .val = 1, .div = 2 },
 215         { .val = 2, .div = 4 },
 216         { .val = 3, .div = 8 },
 217         { .val = 4, .div = 16 },
 218         { .val = 5, .div = 32 },
 219 };
 220
 221 struct clk_pll {
 222         struct clk_hw hw;
 223         u16 regofs;  /* register offset */
 224 };
 225 #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
 226
 227 struct clk_dto {
 228         struct clk_hw hw;
 229         u16 inc_offset;  /* dto increment offset */
 230         u16 src_offset;  /* dto src offset */
 231 };
 232 #define to_dtoclk(_hw) container_of(_hw, struct clk_dto, hw)
 233
 234 struct clk_unit {
 235         struct clk_hw hw;
 236         u16 regofs;
 237         u16 bit;
 238         spinlock_t *lock;
 239 };
 240 #define to_unitclk(_hw) container_of(_hw, struct clk_unit, hw)
 241
 242 struct atlas7_div_init_data {
 243         const char *div_name;
 244         const char *parent_name;
 245         const char *gate_name;
 246         unsigned long flags;
 247         u8 divider_flags;
 248         u8 gate_flags;
 249         u32 div_offset;
 250         u8 shift;
 251         u8 width;
 252         u32 gate_offset;
 253         u8 gate_bit;
 254         spinlock_t *lock;
 255 };
 256
 257 struct atlas7_mux_init_data {
 258         const char *mux_name;
 259         const char * const *parent_names;
 260         u8 parent_num;
 261         unsigned long flags;
 262         u8 mux_flags;
 263         u32 mux_offset;
 264         u8 shift;
 265         u8 width;
 266 };
 267
 268 struct atlas7_unit_init_data {
 269         u32 index;
 270         const char *unit_name;
 271         const char *parent_name;
 272         unsigned long flags;
 273         u32 regofs;
 274         u8 bit;
 275         spinlock_t *lock;
 276 };
 277
 278 struct atlas7_reset_desc {
 279         const char *name;
 280         u32 clk_ofs;
 281         u8  clk_bit;
 282         u32 rst_ofs;
 283         u8  rst_bit;
 284         spinlock_t *lock;
 285 };
 286
 287 static DEFINE_SPINLOCK(cpupll_ctrl1_lock);
 288 static DEFINE_SPINLOCK(mempll_ctrl1_lock);
 289 static DEFINE_SPINLOCK(sys0pll_ctrl1_lock);
 290 static DEFINE_SPINLOCK(sys1pll_ctrl1_lock);
 291 static DEFINE_SPINLOCK(sys2pll_ctrl1_lock);
 292 static DEFINE_SPINLOCK(sys3pll_ctrl1_lock);
 293 static DEFINE_SPINLOCK(usbphy_div_lock);
 294 static DEFINE_SPINLOCK(btss_div_lock);
 295 static DEFINE_SPINLOCK(rgmii_div_lock);
 296 static DEFINE_SPINLOCK(cpu_div_lock);
 297 static DEFINE_SPINLOCK(sdphy01_div_lock);
 298 static DEFINE_SPINLOCK(sdphy23_div_lock);
 299 static DEFINE_SPINLOCK(sdphy45_div_lock);
 300 static DEFINE_SPINLOCK(sdphy67_div_lock);
 301 static DEFINE_SPINLOCK(can_div_lock);
 302 static DEFINE_SPINLOCK(deint_div_lock);
 303 static DEFINE_SPINLOCK(nand_div_lock);
 304 static DEFINE_SPINLOCK(disp0_div_lock);
 305 static DEFINE_SPINLOCK(disp1_div_lock);
 306 static DEFINE_SPINLOCK(gpu_div_lock);
 307 static DEFINE_SPINLOCK(gnss_div_lock);
 308 /* gate register shared */
 309 static DEFINE_SPINLOCK(share_div_lock);
 310 static DEFINE_SPINLOCK(root0_gate_lock);
 311 static DEFINE_SPINLOCK(root1_gate_lock);
 312 static DEFINE_SPINLOCK(leaf0_gate_lock);
 313 static DEFINE_SPINLOCK(leaf1_gate_lock);
 314 static DEFINE_SPINLOCK(leaf2_gate_lock);
 315 static DEFINE_SPINLOCK(leaf3_gate_lock);
 316 static DEFINE_SPINLOCK(leaf4_gate_lock);
 317 static DEFINE_SPINLOCK(leaf5_gate_lock);
 318 static DEFINE_SPINLOCK(leaf6_gate_lock);
 319 static DEFINE_SPINLOCK(leaf7_gate_lock);
 320 static DEFINE_SPINLOCK(leaf8_gate_lock);
 321
 322 static inline unsigned long clkc_readl(unsigned reg)
 323 {
 324         return readl(sirfsoc_clk_vbase + reg);
 325 }
 326
 327 static inline void clkc_writel(u32 val, unsigned reg)
 328 {
 329         writel(val, sirfsoc_clk_vbase + reg);
 330 }
 331
 332 /*
 333 *  ABPLL
 334 *  integer mode: Fvco = Fin * 2 * NF / NR
 335 *  Spread Spectrum mode: Fvco = Fin * SSN / NR
 336 *  SSN = 2^24 / (256 * ((ssdiv >> ssdepth) << ssdepth) + (ssmod << ssdepth))
 337 */
 338 static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
 339         unsigned long parent_rate)
 340 {
 341         unsigned long fin = parent_rate;
 342         struct clk_pll *clk = to_pllclk(hw);
 343         u64 rate;
 344         u32 regctrl0 = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_CTRL0 -
 345                         SIRFSOC_CLKC_MEMPLL_AB_FREQ);
 346         u32 regfreq = clkc_readl(clk->regofs);
 347         u32 regssc = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_SSC -
 348                         SIRFSOC_CLKC_MEMPLL_AB_FREQ);
 349         u32 nr = (regfreq  >> 16 & (BIT(3) - 1)) + 1;
 350         u32 nf = (regfreq & (BIT(9) - 1)) + 1;
 351         u32 ssdiv = regssc >> 8 & (BIT(12) - 1);
 352         u32 ssdepth = regssc >> 20 & (BIT(2) - 1);
 353         u32 ssmod = regssc & (BIT(8) - 1);
 354
 355         if (regctrl0 & SIRFSOC_ABPLL_CTRL0_BYPASS)
 356                 return fin;
 357
 358         if (regctrl0 & SIRFSOC_ABPLL_CTRL0_SSEN) {
 359                 rate = fin;
 360                 rate *= 1 << 24;
 361                 do_div(rate, nr);
 362                 do_div(rate, (256 * ((ssdiv >> ssdepth) << ssdepth)
 363                         + (ssmod << ssdepth)));
 364         } else {
 365                 rate = 2 * fin;
 366                 rate *= nf;
 367                 do_div(rate, nr);
 368         }
 369         return rate;
 370 }
 371
 372 static const struct clk_ops ab_pll_ops = {
 373         .recalc_rate = pll_clk_recalc_rate,
 374 };
 375
 376 static const char * const pll_clk_parents[] = {
 377         "xin",
 378 };
 379
 380 static struct clk_init_data clk_cpupll_init = {
 381         .name = "cpupll_vco",
 382         .ops = &ab_pll_ops,
 383         .parent_names = pll_clk_parents,
 384         .num_parents = ARRAY_SIZE(pll_clk_parents),
 385 };
 386
 387 static struct clk_pll clk_cpupll = {
 388         .regofs = SIRFSOC_CLKC_CPUPLL_AB_FREQ,
 389         .hw = {
 390                 .init = &clk_cpupll_init,
 391         },
 392 };
 393
 394 static struct clk_init_data clk_mempll_init = {
 395         .name = "mempll_vco",
 396         .ops = &ab_pll_ops,
 397         .parent_names = pll_clk_parents,
 398         .num_parents = ARRAY_SIZE(pll_clk_parents),
 399 };
 400
 401 static struct clk_pll clk_mempll = {
 402         .regofs = SIRFSOC_CLKC_MEMPLL_AB_FREQ,
 403         .hw = {
 404                 .init = &clk_mempll_init,
 405         },
 406 };
 407
 408 static struct clk_init_data clk_sys0pll_init = {
 409         .name = "sys0pll_vco",
 410         .ops = &ab_pll_ops,
 411         .parent_names = pll_clk_parents,
 412         .num_parents = ARRAY_SIZE(pll_clk_parents),
 413 };
 414
 415 static struct clk_pll clk_sys0pll = {
 416         .regofs = SIRFSOC_CLKC_SYS0PLL_AB_FREQ,
 417         .hw = {
 418                 .init = &clk_sys0pll_init,
 419         },
 420 };
 421
 422 static struct clk_init_data clk_sys1pll_init = {
 423         .name = "sys1pll_vco",
 424         .ops = &ab_pll_ops,
 425         .parent_names = pll_clk_parents,
 426         .num_parents = ARRAY_SIZE(pll_clk_parents),
 427 };
 428
 429 static struct clk_pll clk_sys1pll = {
 430         .regofs = SIRFSOC_CLKC_SYS1PLL_AB_FREQ,
 431         .hw = {
 432                 .init = &clk_sys1pll_init,
 433         },
 434 };
 435
 436 static struct clk_init_data clk_sys2pll_init = {
 437         .name = "sys2pll_vco",
 438         .ops = &ab_pll_ops,
 439         .parent_names = pll_clk_parents,
 440         .num_parents = ARRAY_SIZE(pll_clk_parents),
 441 };
 442
 443 static struct clk_pll clk_sys2pll = {
 444         .regofs = SIRFSOC_CLKC_SYS2PLL_AB_FREQ,
 445         .hw = {
 446                 .init = &clk_sys2pll_init,
 447         },
 448 };
 449
 450 static struct clk_init_data clk_sys3pll_init = {
 451         .name = "sys3pll_vco",
 452         .ops = &ab_pll_ops,
 453         .parent_names = pll_clk_parents,
 454         .num_parents = ARRAY_SIZE(pll_clk_parents),
 455 };
 456
 457 static struct clk_pll clk_sys3pll = {
 458         .regofs = SIRFSOC_CLKC_SYS3PLL_AB_FREQ,
 459         .hw = {
 460                 .init = &clk_sys3pll_init,
 461         },
 462 };
 463
 464 /*
 465  *  DTO in clkc, default enable double resolution mode
 466  *  double resolution mode:fout = fin * finc / 2^29
 467  *  normal mode:fout = fin * finc / 2^28
 468  */
 469 #define DTO_RESL_DOUBLE (1ULL << 29)
 470 #define DTO_RESL_NORMAL (1ULL << 28)
 471
 472 static int dto_clk_is_enabled(struct clk_hw *hw)
 473 {
 474         struct clk_dto *clk = to_dtoclk(hw);
 475         int reg;
 476
 477         reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC;
 478
 479         return !!(clkc_readl(reg) & BIT(0));
 480 }
 481
 482 static int dto_clk_enable(struct clk_hw *hw)
 483 {
 484         u32 val, reg;
 485         struct clk_dto *clk = to_dtoclk(hw);
 486
 487         reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC;
 488
 489         val = clkc_readl(reg) | BIT(0);
 490         clkc_writel(val, reg);
 491         return 0;
 492 }
 493
 494 static void dto_clk_disable(struct clk_hw *hw)
 495 {
 496         u32 val, reg;
 497         struct clk_dto *clk = to_dtoclk(hw);
 498
 499         reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC;
 500
 501         val = clkc_readl(reg) & ~BIT(0);
 502         clkc_writel(val, reg);
 503 }
 504
 505 static unsigned long dto_clk_recalc_rate(struct clk_hw *hw,
 506         unsigned long parent_rate)
 507 {
 508         u64 rate = parent_rate;
 509         struct clk_dto *clk = to_dtoclk(hw);
 510         u32 finc = clkc_readl(clk->inc_offset);
 511         u32 droff = clkc_readl(clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC);
 512
 513         rate *= finc;
 514         if (droff & BIT(0))
 515                 /* Double resolution off */
 516                 do_div(rate, DTO_RESL_NORMAL);
 517         else
 518                 do_div(rate, DTO_RESL_DOUBLE);
 519
 520         return rate;
 521 }
 522
 523 static long dto_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 524         unsigned long *parent_rate)
 525 {
 526         u64 dividend = rate * DTO_RESL_DOUBLE;
 527
 528         do_div(dividend, *parent_rate);
 529         dividend *= *parent_rate;
 530         do_div(dividend, DTO_RESL_DOUBLE);
 531
 532         return dividend;
 533 }
 534
 535 static int dto_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 536         unsigned long parent_rate)
 537 {
 538         u64 dividend = rate * DTO_RESL_DOUBLE;
 539         struct clk_dto *clk = to_dtoclk(hw);
 540
 541         do_div(dividend, parent_rate);
 542         clkc_writel(0, clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC);
 543         clkc_writel(dividend, clk->inc_offset);
 544
 545         return 0;
 546 }
 547
 548 static u8 dto_clk_get_parent(struct clk_hw *hw)
 549 {
 550         struct clk_dto *clk = to_dtoclk(hw);
 551
 552         return clkc_readl(clk->src_offset);
 553 }
 554
 555 /*
 556  *   dto need CLK_SET_PARENT_GATE
 557  */
 558 static int dto_clk_set_parent(struct clk_hw *hw, u8 index)
 559 {
 560         struct clk_dto *clk = to_dtoclk(hw);
 561
 562         clkc_writel(index, clk->src_offset);
 563         return 0;
 564 }
 565
 566 static const struct clk_ops dto_ops = {
 567         .is_enabled = dto_clk_is_enabled,
 568         .enable = dto_clk_enable,
 569         .disable = dto_clk_disable,
 570         .recalc_rate = dto_clk_recalc_rate,
 571         .round_rate = dto_clk_round_rate,
 572         .set_rate = dto_clk_set_rate,
 573         .get_parent = dto_clk_get_parent,
 574         .set_parent = dto_clk_set_parent,
 575 };
 576
 577 /* dto parent clock as syspllvco/clk1 */
 578 static const char * const audiodto_clk_parents[] = {
 579         "sys0pll_clk1",
 580         "sys1pll_clk1",
 581         "sys3pll_clk1",
 582 };
 583
 584 static struct clk_init_data clk_audiodto_init = {
 585         .name = "audio_dto",
 586         .ops = &dto_ops,
 587         .parent_names = audiodto_clk_parents,
 588         .num_parents = ARRAY_SIZE(audiodto_clk_parents),
 589 };
 590
 591 static struct clk_dto clk_audio_dto = {
 592         .inc_offset = SIRFSOC_CLKC_AUDIO_DTO_INC,
 593         .src_offset = SIRFSOC_CLKC_AUDIO_DTO_SRC,
 594         .hw = {
 595                 .init = &clk_audiodto_init,
 596         },
 597 };
 598
 599 static const char * const disp0dto_clk_parents[] = {
 600         "sys0pll_clk1",
 601         "sys1pll_clk1",
 602         "sys3pll_clk1",
 603 };
 604
 605 static struct clk_init_data clk_disp0dto_init = {
 606         .name = "disp0_dto",
 607         .ops = &dto_ops,
 608         .parent_names = disp0dto_clk_parents,
 609         .num_parents = ARRAY_SIZE(disp0dto_clk_parents),
 610 };
 611
 612 static struct clk_dto clk_disp0_dto = {
 613         .inc_offset = SIRFSOC_CLKC_DISP0_DTO_INC,
 614         .src_offset = SIRFSOC_CLKC_DISP0_DTO_SRC,
 615         .hw = {
 616                 .init = &clk_disp0dto_init,
 617         },
 618 };
 619
 620 static const char * const disp1dto_clk_parents[] = {
 621         "sys0pll_clk1",
 622         "sys1pll_clk1",
 623         "sys3pll_clk1",
 624 };
 625
 626 static struct clk_init_data clk_disp1dto_init = {
 627         .name = "disp1_dto",
 628         .ops = &dto_ops,
 629         .parent_names = disp1dto_clk_parents,
 630         .num_parents = ARRAY_SIZE(disp1dto_clk_parents),
 631 };
 632
 633 static struct clk_dto clk_disp1_dto = {
 634         .inc_offset = SIRFSOC_CLKC_DISP1_DTO_INC,
 635         .src_offset = SIRFSOC_CLKC_DISP1_DTO_SRC,
 636         .hw = {
 637                 .init = &clk_disp1dto_init,
 638         },
 639 };
 640
 641 static struct atlas7_div_init_data divider_list[] __initdata = {
 642         /* div_name, parent_name, gate_name, clk_flag, divider_flag, gate_flag, div_offset, shift, wdith, gate_offset, bit_enable, lock */
 643         { "sys0pll_qa1", "sys0pll_fixdiv", "sys0pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 0, &usbphy_div_lock },
 644         { "sys1pll_qa1", "sys1pll_fixdiv", "sys1pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 4, &usbphy_div_lock },
 645         { "sys2pll_qa1", "sys2pll_fixdiv", "sys2pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 8, &usbphy_div_lock },
 646         { "sys3pll_qa1", "sys3pll_fixdiv", "sys3pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 12, &usbphy_div_lock },
 647         { "sys0pll_qa2", "sys0pll_fixdiv", "sys0pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 0, &btss_div_lock },
 648         { "sys1pll_qa2", "sys1pll_fixdiv", "sys1pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 4, &btss_div_lock },
 649         { "sys2pll_qa2", "sys2pll_fixdiv", "sys2pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 8, &btss_div_lock },
 650         { "sys3pll_qa2", "sys3pll_fixdiv", "sys3pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 12, &btss_div_lock },
 651         { "sys0pll_qa3", "sys0pll_fixdiv", "sys0pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 0, &rgmii_div_lock },
 652         { "sys1pll_qa3", "sys1pll_fixdiv", "sys1pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 4, &rgmii_div_lock },
 653         { "sys2pll_qa3", "sys2pll_fixdiv", "sys2pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 8, &rgmii_div_lock },
 654         { "sys3pll_qa3", "sys3pll_fixdiv", "sys3pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 12, &rgmii_div_lock },
 655         { "sys0pll_qa4", "sys0pll_fixdiv", "sys0pll_a4", 0, 0, 0, SIRFSOC_CLKC_CPU_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_CPU_CLKDIV_ENA, 0, &cpu_div_lock },
 656         { "sys1pll_qa4", "sys1pll_fixdiv", "sys1pll_a4", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_CPU_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_CPU_CLKDIV_ENA, 4, &cpu_div_lock },
 657         { "sys0pll_qa5", "sys0pll_fixdiv", "sys0pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 0, &sdphy01_div_lock },
 658         { "sys1pll_qa5", "sys1pll_fixdiv", "sys1pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 4, &sdphy01_div_lock },
 659         { "sys2pll_qa5", "sys2pll_fixdiv", "sys2pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 8, &sdphy01_div_lock },
 660         { "sys3pll_qa5", "sys3pll_fixdiv", "sys3pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 12, &sdphy01_div_lock },
 661         { "sys0pll_qa6", "sys0pll_fixdiv", "sys0pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 0, &sdphy23_div_lock },
 662         { "sys1pll_qa6", "sys1pll_fixdiv", "sys1pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 4, &sdphy23_div_lock },
 663         { "sys2pll_qa6", "sys2pll_fixdiv", "sys2pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 8, &sdphy23_div_lock },
 664         { "sys3pll_qa6", "sys3pll_fixdiv", "sys3pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 12, &sdphy23_div_lock },
 665         { "sys0pll_qa7", "sys0pll_fixdiv", "sys0pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 0, &sdphy45_div_lock },
 666         { "sys1pll_qa7", "sys1pll_fixdiv", "sys1pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 4, &sdphy45_div_lock },
 667         { "sys2pll_qa7", "sys2pll_fixdiv", "sys2pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 8, &sdphy45_div_lock },
 668         { "sys3pll_qa7", "sys3pll_fixdiv", "sys3pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 12, &sdphy45_div_lock },
 669         { "sys0pll_qa8", "sys0pll_fixdiv", "sys0pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 0, &sdphy67_div_lock },
 670         { "sys1pll_qa8", "sys1pll_fixdiv", "sys1pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 4, &sdphy67_div_lock },
 671         { "sys2pll_qa8", "sys2pll_fixdiv", "sys2pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 8, &sdphy67_div_lock },
 672         { "sys3pll_qa8", "sys3pll_fixdiv", "sys3pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 12, &sdphy67_div_lock },
 673         { "sys0pll_qa9", "sys0pll_fixdiv", "sys0pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 0, &can_div_lock },
 674         { "sys1pll_qa9", "sys1pll_fixdiv", "sys1pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 4, &can_div_lock },
 675         { "sys2pll_qa9", "sys2pll_fixdiv", "sys2pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 8, &can_div_lock },
 676         { "sys3pll_qa9", "sys3pll_fixdiv", "sys3pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 12, &can_div_lock },
 677         { "sys0pll_qa10", "sys0pll_fixdiv", "sys0pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 0, &deint_div_lock },
 678         { "sys1pll_qa10", "sys1pll_fixdiv", "sys1pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 4, &deint_div_lock },
 679         { "sys2pll_qa10", "sys2pll_fixdiv", "sys2pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 8, &deint_div_lock },
 680         { "sys3pll_qa10", "sys3pll_fixdiv", "sys3pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 12, &deint_div_lock },
 681         { "sys0pll_qa11", "sys0pll_fixdiv", "sys0pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 0, &nand_div_lock },
 682         { "sys1pll_qa11", "sys1pll_fixdiv", "sys1pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 4, &nand_div_lock },
 683         { "sys2pll_qa11", "sys2pll_fixdiv", "sys2pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 8, &nand_div_lock },
 684         { "sys3pll_qa11", "sys3pll_fixdiv", "sys3pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 12, &nand_div_lock },
 685         { "sys0pll_qa12", "sys0pll_fixdiv", "sys0pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 0, &disp0_div_lock },
 686         { "sys1pll_qa12", "sys1pll_fixdiv", "sys1pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 4, &disp0_div_lock },
 687         { "sys2pll_qa12", "sys2pll_fixdiv", "sys2pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 8, &disp0_div_lock },
 688         { "sys3pll_qa12", "sys3pll_fixdiv", "sys3pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 12, &disp0_div_lock },
 689         { "sys0pll_qa13", "sys0pll_fixdiv", "sys0pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 0, &disp1_div_lock },
 690         { "sys1pll_qa13", "sys1pll_fixdiv", "sys1pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 4, &disp1_div_lock },
 691         { "sys2pll_qa13", "sys2pll_fixdiv", "sys2pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 8, &disp1_div_lock },
 692         { "sys3pll_qa13", "sys3pll_fixdiv", "sys3pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 12, &disp1_div_lock },
 693         { "sys0pll_qa14", "sys0pll_fixdiv", "sys0pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 0, &gpu_div_lock },
 694         { "sys1pll_qa14", "sys1pll_fixdiv", "sys1pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 4, &gpu_div_lock },
 695         { "sys2pll_qa14", "sys2pll_fixdiv", "sys2pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 8, &gpu_div_lock },
 696         { "sys3pll_qa14", "sys3pll_fixdiv", "sys3pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 12, &gpu_div_lock },
 697         { "sys0pll_qa15", "sys0pll_fixdiv", "sys0pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 0, &gnss_div_lock },
 698         { "sys1pll_qa15", "sys1pll_fixdiv", "sys1pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 4, &gnss_div_lock },
 699         { "sys2pll_qa15", "sys2pll_fixdiv", "sys2pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 8, &gnss_div_lock },
 700         { "sys3pll_qa15", "sys3pll_fixdiv", "sys3pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 12, &gnss_div_lock },
 701         { "sys1pll_qa18", "sys1pll_fixdiv", "sys1pll_a18", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 24, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 12, &share_div_lock },
 702         { "sys1pll_qa19", "sys1pll_fixdiv", "sys1pll_a19", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 16, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 8, &share_div_lock },
 703         { "sys1pll_qa20", "sys1pll_fixdiv", "sys1pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 8, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 4, &share_div_lock },
 704         { "sys2pll_qa20", "sys2pll_fixdiv", "sys2pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 0, &share_div_lock },
 705         { "sys1pll_qa17", "sys1pll_fixdiv", "sys1pll_a17", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 8, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 20, &share_div_lock },
 706         { "sys0pll_qa20", "sys0pll_fixdiv", "sys0pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 16, &share_div_lock },
 707 };
 708
 709 static const char * const i2s_clk_parents[] = {
 710         "xin",
 711         "xinw",
 712         "audio_dto",
 713         /* "pwm_i2s01" */
 714 };
 715
 716 static const char * const usbphy_clk_parents[] = {
 717         "xin",
 718         "xinw",
 719         "sys0pll_a1",
 720         "sys1pll_a1",
 721         "sys2pll_a1",
 722         "sys3pll_a1",
 723 };
 724
 725 static const char * const btss_clk_parents[] = {
 726         "xin",
 727         "xinw",
 728         "sys0pll_a2",
 729         "sys1pll_a2",
 730         "sys2pll_a2",
 731         "sys3pll_a2",
 732 };
 733
 734 static const char * const rgmii_clk_parents[] = {
 735         "xin",
 736         "xinw",
 737         "sys0pll_a3",
 738         "sys1pll_a3",
 739         "sys2pll_a3",
 740         "sys3pll_a3",
 741 };
 742
 743 static const char * const cpu_clk_parents[] = {
 744         "xin",
 745         "xinw",
 746         "sys0pll_a4",
 747         "sys1pll_a4",
 748         "cpupll_clk1",
 749 };
 750
 751 static const char * const sdphy01_clk_parents[] = {
 752         "xin",
 753         "xinw",
 754         "sys0pll_a5",
 755         "sys1pll_a5",
 756         "sys2pll_a5",
 757         "sys3pll_a5",
 758 };
 759
 760 static const char * const sdphy23_clk_parents[] = {
 761         "xin",
 762         "xinw",
 763         "sys0pll_a6",
 764         "sys1pll_a6",
 765         "sys2pll_a6",
 766         "sys3pll_a6",
 767 };
 768
 769 static const char * const sdphy45_clk_parents[] = {
 770         "xin",
 771         "xinw",
 772         "sys0pll_a7",
 773         "sys1pll_a7",
 774         "sys2pll_a7",
 775         "sys3pll_a7",
 776 };
 777
 778 static const char * const sdphy67_clk_parents[] = {
 779         "xin",
 780         "xinw",
 781         "sys0pll_a8",
 782         "sys1pll_a8",
 783         "sys2pll_a8",
 784         "sys3pll_a8",
 785 };
 786
 787 static const char * const can_clk_parents[] = {
 788         "xin",
 789         "xinw",
 790         "sys0pll_a9",
 791         "sys1pll_a9",
 792         "sys2pll_a9",
 793         "sys3pll_a9",
 794 };
 795
 796 static const char * const deint_clk_parents[] = {
 797         "xin",
 798         "xinw",
 799         "sys0pll_a10",
 800         "sys1pll_a10",
 801         "sys2pll_a10",
 802         "sys3pll_a10",
 803 };
 804
 805 static const char * const nand_clk_parents[] = {
 806         "xin",
 807         "xinw",
 808         "sys0pll_a11",
 809         "sys1pll_a11",
 810         "sys2pll_a11",
 811         "sys3pll_a11",
 812 };
 813
 814 static const char * const disp0_clk_parents[] = {
 815         "xin",
 816         "xinw",
 817         "sys0pll_a12",
 818         "sys1pll_a12",
 819         "sys2pll_a12",
 820         "sys3pll_a12",
 821         "disp0_dto",
 822 };
 823
 824 static const char * const disp1_clk_parents[] = {
 825         "xin",
 826         "xinw",
 827         "sys0pll_a13",
 828         "sys1pll_a13",
 829         "sys2pll_a13",
 830         "sys3pll_a13",
 831         "disp1_dto",
 832 };
 833
 834 static const char * const gpu_clk_parents[] = {
 835         "xin",
 836         "xinw",
 837         "sys0pll_a14",
 838         "sys1pll_a14",
 839         "sys2pll_a14",
 840         "sys3pll_a14",
 841 };
 842
 843 static const char * const gnss_clk_parents[] = {
 844         "xin",
 845         "xinw",
 846         "sys0pll_a15",
 847         "sys1pll_a15",
 848         "sys2pll_a15",
 849         "sys3pll_a15",
 850 };
 851
 852 static const char * const sys_clk_parents[] = {
 853         "xin",
 854         "xinw",
 855         "sys2pll_a20",
 856         "sys1pll_a20",
 857         "sys1pll_a19",
 858         "sys1pll_a18",
 859         "sys0pll_a20",
 860         "sys1pll_a17",
 861 };
 862
 863 static const char * const io_clk_parents[] = {
 864         "xin",
 865         "xinw",
 866         "sys2pll_a20",
 867         "sys1pll_a20",
 868         "sys1pll_a19",
 869         "sys1pll_a18",
 870         "sys0pll_a20",
 871         "sys1pll_a17",
 872 };
 873
 874 static const char * const g2d_clk_parents[] = {
 875         "xin",
 876         "xinw",
 877         "sys2pll_a20",
 878         "sys1pll_a20",
 879         "sys1pll_a19",
 880         "sys1pll_a18",
 881         "sys0pll_a20",
 882         "sys1pll_a17",
 883 };
 884
 885 static const char * const jpenc_clk_parents[] = {
 886         "xin",
 887         "xinw",
 888         "sys2pll_a20",
 889         "sys1pll_a20",
 890         "sys1pll_a19",
 891         "sys1pll_a18",
 892         "sys0pll_a20",
 893         "sys1pll_a17",
 894 };
 895
 896 static const char * const vdec_clk_parents[] = {
 897         "xin",
 898         "xinw",
 899         "sys2pll_a20",
 900         "sys1pll_a20",
 901         "sys1pll_a19",
 902         "sys1pll_a18",
 903         "sys0pll_a20",
 904         "sys1pll_a17",
 905 };
 906
 907 static const char * const gmac_clk_parents[] = {
 908         "xin",
 909         "xinw",
 910         "sys2pll_a20",
 911         "sys1pll_a20",
 912         "sys1pll_a19",
 913         "sys1pll_a18",
 914         "sys0pll_a20",
 915         "sys1pll_a17",
 916 };
 917
 918 static const char * const usb_clk_parents[] = {
 919         "xin",
 920         "xinw",
 921         "sys2pll_a20",
 922         "sys1pll_a20",
 923         "sys1pll_a19",
 924         "sys1pll_a18",
 925         "sys0pll_a20",
 926         "sys1pll_a17",
 927 };
 928
 929 static const char * const kas_clk_parents[] = {
 930         "xin",
 931         "xinw",
 932         "sys2pll_a20",
 933         "sys1pll_a20",
 934         "sys1pll_a19",
 935         "sys1pll_a18",
 936         "sys0pll_a20",
 937         "sys1pll_a17",
 938 };
 939
 940 static const char * const sec_clk_parents[] = {
 941         "xin",
 942         "xinw",
 943         "sys2pll_a20",
 944         "sys1pll_a20",
 945         "sys1pll_a19",
 946         "sys1pll_a18",
 947         "sys0pll_a20",
 948         "sys1pll_a17",
 949 };
 950
 951 static const char * const sdr_clk_parents[] = {
 952         "xin",
 953         "xinw",
 954         "sys2pll_a20",
 955         "sys1pll_a20",
 956         "sys1pll_a19",
 957         "sys1pll_a18",
 958         "sys0pll_a20",
 959         "sys1pll_a17",
 960 };
 961
 962 static const char * const vip_clk_parents[] = {
 963         "xin",
 964         "xinw",
 965         "sys2pll_a20",
 966         "sys1pll_a20",
 967         "sys1pll_a19",
 968         "sys1pll_a18",
 969         "sys0pll_a20",
 970         "sys1pll_a17",
 971 };
 972
 973 static const char * const nocd_clk_parents[] = {
 974         "xin",
 975         "xinw",
 976         "sys2pll_a20",
 977         "sys1pll_a20",
 978         "sys1pll_a19",
 979         "sys1pll_a18",
 980         "sys0pll_a20",
 981         "sys1pll_a17",
 982 };
 983
 984 static const char * const nocr_clk_parents[] = {
 985         "xin",
 986         "xinw",
 987         "sys2pll_a20",
 988         "sys1pll_a20",
 989         "sys1pll_a19",
 990         "sys1pll_a18",
 991         "sys0pll_a20",
 992         "sys1pll_a17",
 993 };
 994
 995 static const char * const tpiu_clk_parents[] = {
 996         "xin",
 997         "xinw",
 998         "sys2pll_a20",
 999         "sys1pll_a20",
1000         "sys1pll_a19",
1001         "sys1pll_a18",
1002         "sys0pll_a20",
1003         "sys1pll_a17",
1004 };
1005
1006 static struct atlas7_mux_init_data mux_list[] __initdata = {
1007         /* mux_name, parent_names, parent_num, flags, mux_flags, mux_offset, shift, width */
1008         { "i2s_mux", i2s_clk_parents, ARRAY_SIZE(i2s_clk_parents), 0, 0, SIRFSOC_CLKC_I2S_CLK_SEL, 0, 2 },
1009         { "usbphy_mux", usbphy_clk_parents, ARRAY_SIZE(usbphy_clk_parents), 0, 0, SIRFSOC_CLKC_I2S_CLK_SEL, 0, 3 },
1010         { "btss_mux", btss_clk_parents, ARRAY_SIZE(btss_clk_parents), 0, 0, SIRFSOC_CLKC_BTSS_CLK_SEL, 0, 3 },
1011         { "rgmii_mux", rgmii_clk_parents, ARRAY_SIZE(rgmii_clk_parents), 0, 0, SIRFSOC_CLKC_RGMII_CLK_SEL, 0, 3 },
1012         { "cpu_mux", cpu_clk_parents, ARRAY_SIZE(cpu_clk_parents), 0, 0, SIRFSOC_CLKC_CPU_CLK_SEL, 0, 3 },
1013         { "sdphy01_mux", sdphy01_clk_parents, ARRAY_SIZE(sdphy01_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY01_CLK_SEL, 0, 3 },
1014         { "sdphy23_mux", sdphy23_clk_parents, ARRAY_SIZE(sdphy23_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY23_CLK_SEL, 0, 3 },
1015         { "sdphy45_mux", sdphy45_clk_parents, ARRAY_SIZE(sdphy45_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY45_CLK_SEL, 0, 3 },
1016         { "sdphy67_mux", sdphy67_clk_parents, ARRAY_SIZE(sdphy67_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY67_CLK_SEL, 0, 3 },
1017         { "can_mux", can_clk_parents, ARRAY_SIZE(can_clk_parents), 0, 0, SIRFSOC_CLKC_CAN_CLK_SEL, 0, 3 },
1018         { "deint_mux", deint_clk_parents, ARRAY_SIZE(deint_clk_parents), 0, 0, SIRFSOC_CLKC_DEINT_CLK_SEL, 0, 3 },
1019         { "nand_mux", nand_clk_parents, ARRAY_SIZE(nand_clk_parents), 0, 0, SIRFSOC_CLKC_NAND_CLK_SEL, 0, 3 },
1020         { "disp0_mux", disp0_clk_parents, ARRAY_SIZE(disp0_clk_parents), 0, 0, SIRFSOC_CLKC_DISP0_CLK_SEL, 0, 3 },
1021         { "disp1_mux", disp1_clk_parents, ARRAY_SIZE(disp1_clk_parents), 0, 0, SIRFSOC_CLKC_DISP1_CLK_SEL, 0, 3 },
1022         { "gpu_mux", gpu_clk_parents, ARRAY_SIZE(gpu_clk_parents), 0, 0, SIRFSOC_CLKC_GPU_CLK_SEL, 0, 3 },
1023         { "gnss_mux", gnss_clk_parents, ARRAY_SIZE(gnss_clk_parents), 0, 0, SIRFSOC_CLKC_GNSS_CLK_SEL, 0, 3 },
1024         { "sys_mux", sys_clk_parents, ARRAY_SIZE(sys_clk_parents), 0, 0, SIRFSOC_CLKC_SYS_CLK_SEL, 0, 3 },
1025         { "io_mux", io_clk_parents, ARRAY_SIZE(io_clk_parents), 0, 0, SIRFSOC_CLKC_IO_CLK_SEL, 0, 3 },
1026         { "g2d_mux", g2d_clk_parents, ARRAY_SIZE(g2d_clk_parents), 0, 0, SIRFSOC_CLKC_G2D_CLK_SEL, 0, 3 },
1027         { "jpenc_mux", jpenc_clk_parents, ARRAY_SIZE(jpenc_clk_parents), 0, 0, SIRFSOC_CLKC_JPENC_CLK_SEL, 0, 3 },
1028         { "vdec_mux", vdec_clk_parents, ARRAY_SIZE(vdec_clk_parents), 0, 0, SIRFSOC_CLKC_VDEC_CLK_SEL, 0, 3 },
1029         { "gmac_mux", gmac_clk_parents, ARRAY_SIZE(gmac_clk_parents), 0, 0, SIRFSOC_CLKC_GMAC_CLK_SEL, 0, 3 },
1030         { "usb_mux", usb_clk_parents, ARRAY_SIZE(usb_clk_parents), 0, 0, SIRFSOC_CLKC_USB_CLK_SEL, 0, 3 },
1031         { "kas_mux", kas_clk_parents, ARRAY_SIZE(kas_clk_parents), 0, 0, SIRFSOC_CLKC_KAS_CLK_SEL, 0, 3 },
1032         { "sec_mux", sec_clk_parents, ARRAY_SIZE(sec_clk_parents), 0, 0, SIRFSOC_CLKC_SEC_CLK_SEL, 0, 3 },
1033         { "sdr_mux", sdr_clk_parents, ARRAY_SIZE(sdr_clk_parents), 0, 0, SIRFSOC_CLKC_SDR_CLK_SEL, 0, 3 },
1034         { "vip_mux", vip_clk_parents, ARRAY_SIZE(vip_clk_parents), 0, 0, SIRFSOC_CLKC_VIP_CLK_SEL, 0, 3 },
1035         { "nocd_mux", nocd_clk_parents, ARRAY_SIZE(nocd_clk_parents), 0, 0, SIRFSOC_CLKC_NOCD_CLK_SEL, 0, 3 },
1036         { "nocr_mux", nocr_clk_parents, ARRAY_SIZE(nocr_clk_parents), 0, 0, SIRFSOC_CLKC_NOCR_CLK_SEL, 0, 3 },
1037         { "tpiu_mux", tpiu_clk_parents, ARRAY_SIZE(tpiu_clk_parents), 0, 0, SIRFSOC_CLKC_TPIU_CLK_SEL, 0, 3 },
1038 };
1039
1040         /* new unit should add start from the tail of list */
1041 static struct atlas7_unit_init_data unit_list[] __initdata = {
1042         /* unit_name, parent_name, flags, regofs, bit, lock */
1043         { 0, "audmscm_kas", "kas_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 0, &root0_gate_lock },
1044         { 1, "gnssm_gnss", "gnss_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 1, &root0_gate_lock },
1045         { 2, "gpum_gpu", "gpu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 2, &root0_gate_lock },
1046         { 3, "mediam_g2d", "g2d_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 3, &root0_gate_lock },
1047         { 4, "mediam_jpenc", "jpenc_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 4, &root0_gate_lock },
1048         { 5, "vdifm_disp0", "disp0_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 5, &root0_gate_lock },
1049         { 6, "vdifm_disp1", "disp1_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 6, &root0_gate_lock },
1050         { 7, "audmscm_i2s", "i2s_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 8, &root0_gate_lock },
1051         { 8, "audmscm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 11, &root0_gate_lock },
1052         { 9, "vdifm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 12, &root0_gate_lock },
1053         { 10, "gnssm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 13, &root0_gate_lock },
1054         { 11, "mediam_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 14, &root0_gate_lock },
1055         { 12, "btm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 17, &root0_gate_lock },
1056         { 13, "mediam_sdphy01", "sdphy01_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 18, &root0_gate_lock },
1057         { 14, "vdifm_sdphy23", "sdphy23_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 19, &root0_gate_lock },
1058         { 15, "vdifm_sdphy45", "sdphy45_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 20, &root0_gate_lock },
1059         { 16, "vdifm_sdphy67", "sdphy67_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 21, &root0_gate_lock },
1060         { 17, "audmscm_xin", "xin", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 22, &root0_gate_lock },
1061         { 18, "mediam_nand", "nand_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 27, &root0_gate_lock },
1062         { 19, "gnssm_sec", "sec_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 28, &root0_gate_lock },
1063         { 20, "cpum_cpu", "cpu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 29, &root0_gate_lock },
1064         { 21, "gnssm_xin", "xin", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 30, &root0_gate_lock },
1065         { 22, "vdifm_vip", "vip_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 31, &root0_gate_lock },
1066         { 23, "btm_btss", "btss_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 0, &root1_gate_lock },
1067         { 24, "mediam_usbphy", "usbphy_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 1, &root1_gate_lock },
1068         { 25, "rtcm_kas", "kas_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 2, &root1_gate_lock },
1069         { 26, "audmscm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 3, &root1_gate_lock },
1070         { 27, "vdifm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 4, &root1_gate_lock },
1071         { 28, "gnssm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 5, &root1_gate_lock },
1072         { 29, "mediam_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 6, &root1_gate_lock },
1073         { 30, "cpum_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 8, &root1_gate_lock },
1074         { 31, "gpum_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 9, &root1_gate_lock },
1075         { 32, "audmscm_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 11, &root1_gate_lock },
1076         { 33, "vdifm_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 12, &root1_gate_lock },
1077         { 34, "gnssm_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 13, &root1_gate_lock },
1078         { 35, "mediam_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 14, &root1_gate_lock },
1079         { 36, "ddrm_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 15, &root1_gate_lock },
1080         { 37, "cpum_tpiu", "tpiu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 16, &root1_gate_lock },
1081         { 38, "gpum_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 17, &root1_gate_lock },
1082         { 39, "gnssm_rgmii", "rgmii_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 20, &root1_gate_lock },
1083         { 40, "mediam_vdec", "vdec_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 21, &root1_gate_lock },
1084         { 41, "gpum_sdr", "sdr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 22, &root1_gate_lock },
1085         { 42, "vdifm_deint", "deint_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 23, &root1_gate_lock },
1086         { 43, "gnssm_can", "can_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 26, &root1_gate_lock },
1087         { 44, "mediam_usb", "usb_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 28, &root1_gate_lock },
1088         { 45, "gnssm_gmac", "gmac_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 29, &root1_gate_lock },
1089         { 46, "cvd_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 0, &leaf1_gate_lock },
1090         { 47, "timer_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 1, &leaf1_gate_lock },
1091         { 48, "pulse_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 2, &leaf1_gate_lock },
1092         { 49, "tsc_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 3, &leaf1_gate_lock },
1093         { 50, "tsc_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 21, &leaf1_gate_lock },
1094         { 51, "ioctop_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 4, &leaf1_gate_lock },
1095         { 52, "rsc_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 5, &leaf1_gate_lock },
1096         { 53, "dvm_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 6, &leaf1_gate_lock },
1097         { 54, "lvds_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 7, &leaf1_gate_lock },
1098         { 55, "kas_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 8, &leaf1_gate_lock },
1099         { 56, "ac97_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 9, &leaf1_gate_lock },
1100         { 57, "usp0_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 10, &leaf1_gate_lock },
1101         { 58, "usp1_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 11, &leaf1_gate_lock },
1102         { 59, "usp2_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 12, &leaf1_gate_lock },
1103         { 60, "dmac2_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 13, &leaf1_gate_lock },
1104         { 61, "dmac3_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 14, &leaf1_gate_lock },
1105         { 62, "audioif_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 15, &leaf1_gate_lock },
1106         { 63, "i2s1_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 17, &leaf1_gate_lock },
1107         { 64, "thaudmscm_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 22, &leaf1_gate_lock },
1108         { 65, "analogtest_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 23, &leaf1_gate_lock },
1109         { 66, "sys2pci_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 0, &leaf2_gate_lock },
1110         { 67, "pciarb_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 1, &leaf2_gate_lock },
1111         { 68, "pcicopy_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 2, &leaf2_gate_lock },
1112         { 69, "rom_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 3, &leaf2_gate_lock },
1113         { 70, "sdio23_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 4, &leaf2_gate_lock },
1114         { 71, "sdio45_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 5, &leaf2_gate_lock },
1115         { 72, "sdio67_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 6, &leaf2_gate_lock },
1116         { 73, "vip1_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 7, &leaf2_gate_lock },
1117         { 74, "vip1_vip", "vdifm_vip", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 16, &leaf2_gate_lock },
1118         { 75, "sdio23_sdphy23", "vdifm_sdphy23", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 8, &leaf2_gate_lock },
1119         { 76, "sdio45_sdphy45", "vdifm_sdphy45", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 9, &leaf2_gate_lock },
1120         { 77, "sdio67_sdphy67", "vdifm_sdphy67", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 10, &leaf2_gate_lock },
1121         { 78, "vpp0_disp0", "vdifm_disp0", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 11, &leaf2_gate_lock },
1122         { 79, "lcd0_disp0", "vdifm_disp0", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 12, &leaf2_gate_lock },
1123         { 80, "vpp1_disp1", "vdifm_disp1", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 13, &leaf2_gate_lock },
1124         { 81, "lcd1_disp1", "vdifm_disp1", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 14, &leaf2_gate_lock },
1125         { 82, "dcu_deint", "vdifm_deint", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 15, &leaf2_gate_lock },
1126         { 83, "vdifm_dapa_r_nocr", "vdifm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 17, &leaf2_gate_lock },
1127         { 84, "gpio1_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 18, &leaf2_gate_lock },
1128         { 85, "thvdifm_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 19, &leaf2_gate_lock },
1129         { 86, "gmac_rgmii", "gnssm_rgmii", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 0, &leaf3_gate_lock },
1130         { 87, "gmac_gmac", "gnssm_gmac", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 1, &leaf3_gate_lock },
1131         { 88, "uart1_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 2, &leaf3_gate_lock },
1132         { 89, "dmac0_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 3, &leaf3_gate_lock },
1133         { 90, "uart0_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 4, &leaf3_gate_lock },
1134         { 91, "uart2_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 5, &leaf3_gate_lock },
1135         { 92, "uart3_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 6, &leaf3_gate_lock },
1136         { 93, "uart4_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 7, &leaf3_gate_lock },
1137         { 94, "uart5_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 8, &leaf3_gate_lock },
1138         { 95, "spi1_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 9, &leaf3_gate_lock },
1139         { 96, "gnss_gnss", "gnssm_gnss", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 10, &leaf3_gate_lock },
1140         { 97, "canbus1_can", "gnssm_can", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 12, &leaf3_gate_lock },
1141         { 98, "ccsec_sec", "gnssm_sec", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 15, &leaf3_gate_lock },
1142         { 99,  "ccpub_sec", "gnssm_sec", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 16, &leaf3_gate_lock },
1143         { 100, "gnssm_dapa_r_nocr", "gnssm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 13, &leaf3_gate_lock },
1144         { 101, "thgnssm_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 14, &leaf3_gate_lock },
1145         { 102, "media_vdec", "mediam_vdec", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 0, &leaf4_gate_lock },
1146         { 103, "media_jpenc", "mediam_jpenc", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 1, &leaf4_gate_lock },
1147         { 104, "g2d_g2d", "mediam_g2d", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 2, &leaf4_gate_lock },
1148         { 105, "i2c0_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 3, &leaf4_gate_lock },
1149         { 106, "i2c1_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 4, &leaf4_gate_lock },
1150         { 107, "gpio0_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 5, &leaf4_gate_lock },
1151         { 108, "nand_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 6, &leaf4_gate_lock },
1152         { 109, "sdio01_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 7, &leaf4_gate_lock },
1153         { 110, "sys2pci2_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 8, &leaf4_gate_lock },
1154         { 111, "sdio01_sdphy01", "mediam_sdphy01", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 9, &leaf4_gate_lock },
1155         { 112, "nand_nand", "mediam_nand", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 10, &leaf4_gate_lock },
1156         { 113, "usb0_usb", "mediam_usb", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 11, &leaf4_gate_lock },
1157         { 114, "usb1_usb", "mediam_usb", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 12, &leaf4_gate_lock },
1158         { 115, "usbphy0_usbphy", "mediam_usbphy", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 13, &leaf4_gate_lock },
1159         { 116, "usbphy1_usbphy", "mediam_usbphy", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 14, &leaf4_gate_lock },
1160         { 117, "thmediam_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 15, &leaf4_gate_lock },
1161         { 118, "memc_mem", "mempll_clk1", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 0, &leaf5_gate_lock },
1162         { 119, "dapa_mem", "mempll_clk1", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 1, &leaf5_gate_lock },
1163         { 120, "nocddrm_nocr", "ddrm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 2, &leaf5_gate_lock },
1164         { 121, "thddrm_nocr", "ddrm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 3, &leaf5_gate_lock },
1165         { 122, "spram1_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 0, &leaf6_gate_lock },
1166         { 123, "spram2_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 1, &leaf6_gate_lock },
1167         { 124, "coresight_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 2, &leaf6_gate_lock },
1168         { 125, "coresight_tpiu", "cpum_tpiu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 3, &leaf6_gate_lock },
1169         { 126, "graphic_gpu", "gpum_gpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 0, &leaf7_gate_lock },
1170         { 127, "vss_sdr", "gpum_sdr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 1, &leaf7_gate_lock },
1171         { 128, "thgpum_nocr", "gpum_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 2, &leaf7_gate_lock },
1172         { 129, "a7ca_btss", "btm_btss", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 1, &leaf8_gate_lock },
1173         { 130, "dmac4_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 2, &leaf8_gate_lock },
1174         { 131, "uart6_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 3, &leaf8_gate_lock },
1175         { 132, "usp3_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 4, &leaf8_gate_lock },
1176         { 133, "a7ca_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 5, &leaf8_gate_lock },
1177         { 134, "noc_btm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 6, &leaf8_gate_lock },
1178         { 135, "thbtm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 7, &leaf8_gate_lock },
1179         { 136, "btslow", "xinw_fixdiv_btslow", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 25, &root1_gate_lock },
1180         { 137, "a7ca_btslow", "btslow", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 0, &leaf8_gate_lock },
1181         { 138, "pwm_io", "io_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 0, &leaf0_gate_lock },
1182         { 139, "pwm_xin", "xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 1, &leaf0_gate_lock },
1183         { 140, "pwm_xinw", "xinw", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 2, &leaf0_gate_lock },
1184         { 141, "thcgum_sys", "sys_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 3, &leaf0_gate_lock },
1185 };
1186
1187 static struct clk *atlas7_clks[ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list)];
1188
1189 static int unit_clk_is_enabled(struct clk_hw *hw)
1190 {
1191         struct clk_unit *clk = to_unitclk(hw);
1192         u32 reg;
1193
1194         reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_STAT - SIRFSOC_CLKC_ROOT_CLK_EN0_SET;
1195
1196         return !!(clkc_readl(reg) & BIT(clk->bit));
1197 }
1198
1199 static int unit_clk_enable(struct clk_hw *hw)
1200 {
1201         u32 reg;
1202         struct clk_unit *clk = to_unitclk(hw);
1203         unsigned long flags;
1204
1205         reg = clk->regofs;
1206
1207         spin_lock_irqsave(clk->lock, flags);
1208         clkc_writel(BIT(clk->bit), reg);
1209         spin_unlock_irqrestore(clk->lock, flags);
1210         return 0;
1211 }
1212
1213 static void unit_clk_disable(struct clk_hw *hw)
1214 {
1215         u32  reg;
1216         struct clk_unit *clk = to_unitclk(hw);
1217         unsigned long flags;
1218
1219         reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_CLR - SIRFSOC_CLKC_ROOT_CLK_EN0_SET;
1220
1221         spin_lock_irqsave(clk->lock, flags);
1222         clkc_writel(BIT(clk->bit), reg);
1223         spin_unlock_irqrestore(clk->lock, flags);
1224 }
1225
1226 static const struct clk_ops unit_clk_ops = {
1227         .is_enabled = unit_clk_is_enabled,
1228         .enable = unit_clk_enable,
1229         .disable = unit_clk_disable,
1230 };
1231
1232 static struct clk * __init
1233 atlas7_unit_clk_register(struct device *dev, const char *name,
1234                  const char * const parent_name, unsigned long flags,
1235                  u32 regofs, u8 bit, spinlock_t *lock)
1236 {
1237         struct clk *clk;
1238         struct clk_unit *unit;
1239         struct clk_init_data init;
1240
1241         unit = kzalloc(sizeof(*unit), GFP_KERNEL);
1242         if (!unit)
1243                 return ERR_PTR(-ENOMEM);
1244
1245         init.name = name;
1246         init.parent_names = &parent_name;
1247         init.num_parents = 1;
1248         init.ops = &unit_clk_ops;
1249         init.flags = flags;
1250
1251         unit->hw.init = &init;
1252         unit->regofs = regofs;
1253         unit->bit = bit;
1254         unit->lock = lock;
1255
1256         clk = clk_register(dev, &unit->hw);
1257         if (IS_ERR(clk))
1258                 kfree(unit);
1259
1260         return clk;
1261 }
1262
1263 static struct atlas7_reset_desc atlas7_reset_unit[] = {
1264         { "PWM", 0x0244, 0, 0x0320, 0, &leaf0_gate_lock }, /* 0-5 */
1265         { "THCGUM", 0x0244, 3, 0x0320, 1, &leaf0_gate_lock },
1266         { "CVD", 0x04A0, 0, 0x032C, 0, &leaf1_gate_lock },
1267         { "TIMER", 0x04A0, 1, 0x032C, 1, &leaf1_gate_lock },
1268         { "PULSEC", 0x04A0, 2, 0x032C, 2, &leaf1_gate_lock },
1269         { "TSC", 0x04A0, 3, 0x032C, 3, &leaf1_gate_lock },
1270         { "IOCTOP", 0x04A0, 4, 0x032C, 4, &leaf1_gate_lock }, /* 6-10 */
1271         { "RSC", 0x04A0, 5, 0x032C, 5, &leaf1_gate_lock },
1272         { "DVM", 0x04A0, 6, 0x032C, 6, &leaf1_gate_lock },
1273         { "LVDS", 0x04A0, 7, 0x032C, 7, &leaf1_gate_lock },
1274         { "KAS", 0x04A0, 8, 0x032C, 8, &leaf1_gate_lock },
1275         { "AC97", 0x04A0, 9, 0x032C, 9, &leaf1_gate_lock }, /* 11-15 */
1276         { "USP0", 0x04A0, 10, 0x032C, 10, &leaf1_gate_lock },
1277         { "USP1", 0x04A0, 11, 0x032C, 11, &leaf1_gate_lock },
1278         { "USP2", 0x04A0, 12, 0x032C, 12, &leaf1_gate_lock },
1279         { "DMAC2", 0x04A0, 13, 0x032C, 13, &leaf1_gate_lock },
1280         { "DMAC3", 0x04A0, 14, 0x032C, 14, &leaf1_gate_lock }, /* 16-20 */
1281         { "AUDIO", 0x04A0, 15, 0x032C, 15, &leaf1_gate_lock },
1282         { "I2S1", 0x04A0, 17, 0x032C, 16, &leaf1_gate_lock },
1283         { "PMU_AUDIO", 0x04A0, 22, 0x032C, 17, &leaf1_gate_lock },
1284         { "THAUDMSCM", 0x04A0, 23, 0x032C, 18, &leaf1_gate_lock },
1285         { "SYS2PCI", 0x04B8, 0, 0x0338, 0, &leaf2_gate_lock }, /* 21-25 */
1286         { "PCIARB", 0x04B8, 1, 0x0338, 1, &leaf2_gate_lock },
1287         { "PCICOPY", 0x04B8, 2, 0x0338, 2, &leaf2_gate_lock },
1288         { "ROM", 0x04B8, 3, 0x0338, 3, &leaf2_gate_lock },
1289         { "SDIO23", 0x04B8, 4, 0x0338, 4, &leaf2_gate_lock },
1290         { "SDIO45", 0x04B8, 5, 0x0338, 5, &leaf2_gate_lock }, /* 26-30 */
1291         { "SDIO67", 0x04B8, 6, 0x0338, 6, &leaf2_gate_lock },
1292         { "VIP1", 0x04B8, 7, 0x0338, 7, &leaf2_gate_lock },
1293         { "VPP0", 0x04B8, 11, 0x0338, 8, &leaf2_gate_lock },
1294         { "LCD0", 0x04B8, 12, 0x0338, 9, &leaf2_gate_lock },
1295         { "VPP1", 0x04B8, 13, 0x0338, 10, &leaf2_gate_lock }, /* 31-35 */
1296         { "LCD1", 0x04B8, 14, 0x0338, 11, &leaf2_gate_lock },
1297         { "DCU", 0x04B8, 15, 0x0338, 12, &leaf2_gate_lock },
1298         { "GPIO", 0x04B8, 18, 0x0338, 13, &leaf2_gate_lock },
1299         { "DAPA_VDIFM", 0x04B8, 17, 0x0338, 15, &leaf2_gate_lock },
1300         { "THVDIFM", 0x04B8, 19, 0x0338, 16, &leaf2_gate_lock }, /* 36-40 */
1301         { "RGMII", 0x04D0, 0, 0x0344, 0, &leaf3_gate_lock },
1302         { "GMAC", 0x04D0, 1, 0x0344, 1, &leaf3_gate_lock },
1303         { "UART1", 0x04D0, 2, 0x0344, 2, &leaf3_gate_lock },
1304         { "DMAC0", 0x04D0, 3, 0x0344, 3, &leaf3_gate_lock },
1305         { "UART0", 0x04D0, 4, 0x0344, 4, &leaf3_gate_lock }, /* 41-45 */
1306         { "UART2", 0x04D0, 5, 0x0344, 5, &leaf3_gate_lock },
1307         { "UART3", 0x04D0, 6, 0x0344, 6, &leaf3_gate_lock },
1308         { "UART4", 0x04D0, 7, 0x0344, 7, &leaf3_gate_lock },
1309         { "UART5", 0x04D0, 8, 0x0344, 8, &leaf3_gate_lock },
1310         { "SPI1", 0x04D0, 9, 0x0344, 9, &leaf3_gate_lock }, /* 46-50 */
1311         { "GNSS_SYS_M0", 0x04D0, 10, 0x0344, 10, &leaf3_gate_lock },
1312         { "CANBUS1", 0x04D0, 12, 0x0344, 11, &leaf3_gate_lock },
1313         { "CCSEC", 0x04D0, 15, 0x0344, 12, &leaf3_gate_lock },
1314         { "CCPUB", 0x04D0, 16, 0x0344, 13, &leaf3_gate_lock },
1315         { "DAPA_GNSSM", 0x04D0, 13, 0x0344, 14, &leaf3_gate_lock }, /* 51-55 */
1316         { "THGNSSM", 0x04D0, 14, 0x0344, 15, &leaf3_gate_lock },
1317         { "VDEC", 0x04E8, 0, 0x0350, 0, &leaf4_gate_lock },
1318         { "JPENC", 0x04E8, 1, 0x0350, 1, &leaf4_gate_lock },
1319         { "G2D", 0x04E8, 2, 0x0350, 2, &leaf4_gate_lock },
1320         { "I2C0", 0x04E8, 3, 0x0350, 3, &leaf4_gate_lock }, /* 56-60 */
1321         { "I2C1", 0x04E8, 4, 0x0350, 4, &leaf4_gate_lock },
1322         { "GPIO0", 0x04E8, 5, 0x0350, 5, &leaf4_gate_lock },
1323         { "NAND", 0x04E8, 6, 0x0350, 6, &leaf4_gate_lock },
1324         { "SDIO01", 0x04E8, 7, 0x0350, 7, &leaf4_gate_lock },
1325         { "SYS2PCI2", 0x04E8, 8, 0x0350, 8, &leaf4_gate_lock }, /* 61-65 */
1326         { "USB0", 0x04E8, 11, 0x0350, 9, &leaf4_gate_lock },
1327         { "USB1", 0x04E8, 12, 0x0350, 10, &leaf4_gate_lock },
1328         { "THMEDIAM", 0x04E8, 15, 0x0350, 11, &leaf4_gate_lock },
1329         { "MEMC_DDRPHY", 0x0500, 0, 0x035C, 0, &leaf5_gate_lock },
1330         { "MEMC_UPCTL", 0x0500, 0, 0x035C, 1, &leaf5_gate_lock }, /* 66-70 */
1331         { "DAPA_MEM", 0x0500, 1, 0x035C, 2, &leaf5_gate_lock },
1332         { "MEMC_MEMDIV", 0x0500, 0, 0x035C, 3, &leaf5_gate_lock },
1333         { "THDDRM", 0x0500, 3, 0x035C, 4, &leaf5_gate_lock },
1334         { "CORESIGHT", 0x0518, 3, 0x0368, 13, &leaf6_gate_lock },
1335         { "THCPUM", 0x0518, 4, 0x0368, 17, &leaf6_gate_lock }, /* 71-75 */
1336         { "GRAPHIC", 0x0530, 0, 0x0374, 0, &leaf7_gate_lock },
1337         { "VSS_SDR", 0x0530, 1, 0x0374, 1, &leaf7_gate_lock },
1338         { "THGPUM", 0x0530, 2, 0x0374, 2, &leaf7_gate_lock },
1339         { "DMAC4", 0x0548, 2, 0x0380, 1, &leaf8_gate_lock },
1340         { "UART6", 0x0548, 3, 0x0380, 2, &leaf8_gate_lock }, /* 76- */
1341         { "USP3", 0x0548, 4, 0x0380, 3, &leaf8_gate_lock },
1342         { "THBTM", 0x0548, 5, 0x0380, 5, &leaf8_gate_lock },
1343         { "A7CA", 0x0548, 1, 0x0380, 0, &leaf8_gate_lock },
1344         { "A7CA_APB", 0x0548, 5, 0x0380, 4, &leaf8_gate_lock },
1345 };
1346
1347 static int atlas7_reset_module(struct reset_controller_dev *rcdev,
1348                                         unsigned long reset_idx)
1349 {
1350         struct atlas7_reset_desc *reset = &atlas7_reset_unit[reset_idx];
1351         unsigned long flags;
1352
1353         /*
1354          * HW suggest unit reset sequence:
1355          * assert sw reset (0)
1356          * setting sw clk_en to if the clock was disabled before reset
1357          * delay 16 clocks
1358          * disable clock (sw clk_en = 0)
1359          * de-assert reset (1)
1360          * after this sequence, restore clock or not is decided by SW
1361          */
1362
1363         spin_lock_irqsave(reset->lock, flags);
1364         /* clock enable or not */
1365         if (clkc_readl(reset->clk_ofs + 8) & (1 << reset->clk_bit)) {
1366                 clkc_writel(1 << reset->rst_bit, reset->rst_ofs + 4);
1367                 udelay(2);
1368                 clkc_writel(1 << reset->clk_bit, reset->clk_ofs + 4);
1369                 clkc_writel(1 << reset->rst_bit, reset->rst_ofs);
1370                 /* restore clock enable */
1371                 clkc_writel(1 << reset->clk_bit, reset->clk_ofs);
1372         } else {
1373                 clkc_writel(1 << reset->rst_bit, reset->rst_ofs + 4);
1374                 clkc_writel(1 << reset->clk_bit, reset->clk_ofs);
1375                 udelay(2);
1376                 clkc_writel(1 << reset->clk_bit, reset->clk_ofs + 4);
1377                 clkc_writel(1 << reset->rst_bit, reset->rst_ofs);
1378         }
1379         spin_unlock_irqrestore(reset->lock, flags);
1380
1381         return 0;
1382 }
1383
1384 static struct reset_control_ops atlas7_rst_ops = {
1385         .reset = atlas7_reset_module,
1386 };
1387
1388 static struct reset_controller_dev atlas7_rst_ctlr = {
1389         .ops = &atlas7_rst_ops,
1390         .owner = THIS_MODULE,
1391         .of_reset_n_cells = 1,
1392 };
1393
1394 static void __init atlas7_clk_init(struct device_node *np)
1395 {
1396         struct clk *clk;
1397         struct atlas7_div_init_data *div;
1398         struct atlas7_mux_init_data *mux;
1399         struct atlas7_unit_init_data *unit;
1400         int i;
1401         int ret;
1402
1403         sirfsoc_clk_vbase = of_iomap(np, 0);
1404         if (!sirfsoc_clk_vbase)
1405                 panic("unable to map clkc registers\n");
1406
1407         of_node_put(np);
1408
1409         clk = clk_register(NULL, &clk_cpupll.hw);
1410         BUG_ON(!clk);
1411         clk = clk_register(NULL, &clk_mempll.hw);
1412         BUG_ON(!clk);
1413         clk = clk_register(NULL, &clk_sys0pll.hw);
1414         BUG_ON(!clk);
1415         clk = clk_register(NULL, &clk_sys1pll.hw);
1416         BUG_ON(!clk);
1417         clk = clk_register(NULL, &clk_sys2pll.hw);
1418         BUG_ON(!clk);
1419         clk = clk_register(NULL, &clk_sys3pll.hw);
1420         BUG_ON(!clk);
1421
1422         clk = clk_register_divider_table(NULL, "cpupll_div1", "cpupll_vco", 0,
1423                          sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 0, 3, 0,
1424                          pll_div_table, &cpupll_ctrl1_lock);
1425         BUG_ON(!clk);
1426         clk = clk_register_divider_table(NULL, "cpupll_div2", "cpupll_vco", 0,
1427                          sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 4, 3, 0,
1428                          pll_div_table, &cpupll_ctrl1_lock);
1429         BUG_ON(!clk);
1430         clk = clk_register_divider_table(NULL, "cpupll_div3", "cpupll_vco", 0,
1431                          sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 8, 3, 0,
1432                          pll_div_table, &cpupll_ctrl1_lock);
1433         BUG_ON(!clk);
1434
1435         clk = clk_register_divider_table(NULL, "mempll_div1", "mempll_vco", 0,
1436                          sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 0, 3, 0,
1437                          pll_div_table, &mempll_ctrl1_lock);
1438         BUG_ON(!clk);
1439         clk = clk_register_divider_table(NULL, "mempll_div2", "mempll_vco", 0,
1440                          sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 4, 3, 0,
1441                          pll_div_table, &mempll_ctrl1_lock);
1442         BUG_ON(!clk);
1443         clk = clk_register_divider_table(NULL, "mempll_div3", "mempll_vco", 0,
1444                          sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 8, 3, 0,
1445                          pll_div_table, &mempll_ctrl1_lock);
1446         BUG_ON(!clk);
1447
1448         clk = clk_register_divider_table(NULL, "sys0pll_div1", "sys0pll_vco", 0,
1449                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 0, 3, 0,
1450                          pll_div_table, &sys0pll_ctrl1_lock);
1451         BUG_ON(!clk);
1452         clk = clk_register_divider_table(NULL, "sys0pll_div2", "sys0pll_vco", 0,
1453                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 4, 3, 0,
1454                          pll_div_table, &sys0pll_ctrl1_lock);
1455         BUG_ON(!clk);
1456         clk = clk_register_divider_table(NULL, "sys0pll_div3", "sys0pll_vco", 0,
1457                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 8, 3, 0,
1458                          pll_div_table, &sys0pll_ctrl1_lock);
1459         BUG_ON(!clk);
1460         clk = clk_register_fixed_factor(NULL, "sys0pll_fixdiv", "sys0pll_vco",
1461                                         CLK_SET_RATE_PARENT, 1, 2);
1462
1463         clk = clk_register_divider_table(NULL, "sys1pll_div1", "sys1pll_vco", 0,
1464                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 0, 3, 0,
1465                          pll_div_table, &sys1pll_ctrl1_lock);
1466         BUG_ON(!clk);
1467         clk = clk_register_divider_table(NULL, "sys1pll_div2", "sys1pll_vco", 0,
1468                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 4, 3, 0,
1469                          pll_div_table, &sys1pll_ctrl1_lock);
1470         BUG_ON(!clk);
1471         clk = clk_register_divider_table(NULL, "sys1pll_div3", "sys1pll_vco", 0,
1472                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 8, 3, 0,
1473                          pll_div_table, &sys1pll_ctrl1_lock);
1474         BUG_ON(!clk);
1475         clk = clk_register_fixed_factor(NULL, "sys1pll_fixdiv", "sys1pll_vco",
1476                                         CLK_SET_RATE_PARENT, 1, 2);
1477
1478         clk = clk_register_divider_table(NULL, "sys2pll_div1", "sys2pll_vco", 0,
1479                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 0, 3, 0,
1480                          pll_div_table, &sys2pll_ctrl1_lock);
1481         BUG_ON(!clk);
1482         clk = clk_register_divider_table(NULL, "sys2pll_div2", "sys2pll_vco", 0,
1483                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 4, 3, 0,
1484                          pll_div_table, &sys2pll_ctrl1_lock);
1485         BUG_ON(!clk);
1486         clk = clk_register_divider_table(NULL, "sys2pll_div3", "sys2pll_vco", 0,
1487                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 8, 3, 0,
1488                          pll_div_table, &sys2pll_ctrl1_lock);
1489         BUG_ON(!clk);
1490         clk = clk_register_fixed_factor(NULL, "sys2pll_fixdiv", "sys2pll_vco",
1491                                         CLK_SET_RATE_PARENT, 1, 2);
1492
1493         clk = clk_register_divider_table(NULL, "sys3pll_div1", "sys3pll_vco", 0,
1494                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 0, 3, 0,
1495                          pll_div_table, &sys3pll_ctrl1_lock);
1496         BUG_ON(!clk);
1497         clk = clk_register_divider_table(NULL, "sys3pll_div2", "sys3pll_vco", 0,
1498                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 4, 3, 0,
1499                          pll_div_table, &sys3pll_ctrl1_lock);
1500         BUG_ON(!clk);
1501         clk = clk_register_divider_table(NULL, "sys3pll_div3", "sys3pll_vco", 0,
1502                          sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 8, 3, 0,
1503                          pll_div_table, &sys3pll_ctrl1_lock);
1504         BUG_ON(!clk);
1505         clk = clk_register_fixed_factor(NULL, "sys3pll_fixdiv", "sys3pll_vco",
1506                                         CLK_SET_RATE_PARENT, 1, 2);
1507
1508         BUG_ON(!clk);
1509         clk = clk_register_fixed_factor(NULL, "xinw_fixdiv_btslow", "xinw",
1510                                         CLK_SET_RATE_PARENT, 1, 4);
1511
1512         BUG_ON(!clk);
1513         clk = clk_register_gate(NULL, "cpupll_clk1", "cpupll_div1",
1514                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1,
1515                                 12, 0, &cpupll_ctrl1_lock);
1516         BUG_ON(!clk);
1517         clk = clk_register_gate(NULL, "cpupll_clk2", "cpupll_div2",
1518                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1,
1519                                 13, 0, &cpupll_ctrl1_lock);
1520         BUG_ON(!clk);
1521         clk = clk_register_gate(NULL, "cpupll_clk3", "cpupll_div3",
1522                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1,
1523                                 14, 0, &cpupll_ctrl1_lock);
1524         BUG_ON(!clk);
1525
1526         clk = clk_register_gate(NULL, "mempll_clk1", "mempll_div1",
1527                 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1528                 sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1,
1529                 12, 0, &mempll_ctrl1_lock);
1530         BUG_ON(!clk);
1531         clk = clk_register_gate(NULL, "mempll_clk2", "mempll_div2",
1532                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1,
1533                                 13, 0, &mempll_ctrl1_lock);
1534         BUG_ON(!clk);
1535         clk = clk_register_gate(NULL, "mempll_clk3", "mempll_div3",
1536                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1,
1537                                 14, 0, &mempll_ctrl1_lock);
1538         BUG_ON(!clk);
1539
1540         clk = clk_register_gate(NULL, "sys0pll_clk1", "sys0pll_div1",
1541                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1,
1542                                 12, 0, &sys0pll_ctrl1_lock);
1543         BUG_ON(!clk);
1544         clk = clk_register_gate(NULL, "sys0pll_clk2", "sys0pll_div2",
1545                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1,
1546                                 13, 0, &sys0pll_ctrl1_lock);
1547         BUG_ON(!clk);
1548         clk = clk_register_gate(NULL, "sys0pll_clk3", "sys0pll_div3",
1549                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1,
1550                                 14, 0, &sys0pll_ctrl1_lock);
1551         BUG_ON(!clk);
1552
1553         clk = clk_register_gate(NULL, "sys1pll_clk1", "sys1pll_div1",
1554                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1,
1555                                 12, 0, &sys1pll_ctrl1_lock);
1556         BUG_ON(!clk);
1557         clk = clk_register_gate(NULL, "sys1pll_clk2", "sys1pll_div2",
1558                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1,
1559                                 13, 0, &sys1pll_ctrl1_lock);
1560         BUG_ON(!clk);
1561         clk = clk_register_gate(NULL, "sys1pll_clk3", "sys1pll_div3",
1562                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1,
1563                                 14, 0, &sys1pll_ctrl1_lock);
1564         BUG_ON(!clk);
1565
1566         clk = clk_register_gate(NULL, "sys2pll_clk1", "sys2pll_div1",
1567                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1,
1568                                 12, 0, &sys2pll_ctrl1_lock);
1569         BUG_ON(!clk);
1570         clk = clk_register_gate(NULL, "sys2pll_clk2", "sys2pll_div2",
1571                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1,
1572                                 13, 0, &sys2pll_ctrl1_lock);
1573         BUG_ON(!clk);
1574         clk = clk_register_gate(NULL, "sys2pll_clk3", "sys2pll_div3",
1575                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1,
1576                                 14, 0, &sys2pll_ctrl1_lock);
1577         BUG_ON(!clk);
1578
1579         clk = clk_register_gate(NULL, "sys3pll_clk1", "sys3pll_div1",
1580                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1,
1581                                 12, 0, &sys3pll_ctrl1_lock);
1582         BUG_ON(!clk);
1583         clk = clk_register_gate(NULL, "sys3pll_clk2", "sys3pll_div2",
1584                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1,
1585                                 13, 0, &sys3pll_ctrl1_lock);
1586         BUG_ON(!clk);
1587         clk = clk_register_gate(NULL, "sys3pll_clk3", "sys3pll_div3",
1588                 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1,
1589                                 14, 0, &sys3pll_ctrl1_lock);
1590         BUG_ON(!clk);
1591
1592         clk = clk_register(NULL, &clk_audio_dto.hw);
1593         BUG_ON(!clk);
1594
1595         clk = clk_register(NULL, &clk_disp0_dto.hw);
1596         BUG_ON(!clk);
1597
1598         clk = clk_register(NULL, &clk_disp1_dto.hw);
1599         BUG_ON(!clk);
1600
1601         for (i = 0; i < ARRAY_SIZE(divider_list); i++) {
1602                 div = &divider_list[i];
1603                 clk = clk_register_divider(NULL, div->div_name,
1604                         div->parent_name, div->divider_flags, sirfsoc_clk_vbase + div->div_offset,
1605                         div->shift, div->width, 0, div->lock);
1606                 BUG_ON(!clk);
1607                 clk = clk_register_gate(NULL, div->gate_name, div->div_name,
1608                         div->gate_flags, sirfsoc_clk_vbase + div->gate_offset,
1609                                 div->gate_bit, 0, div->lock);
1610                 BUG_ON(!clk);
1611         }
1612         /* ignore selector status register check */
1613         for (i = 0; i < ARRAY_SIZE(mux_list); i++) {
1614                 mux = &mux_list[i];
1615                 clk = clk_register_mux(NULL, mux->mux_name, mux->parent_names,
1616                                mux->parent_num, mux->flags,
1617                                sirfsoc_clk_vbase + mux->mux_offset,
1618                                mux->shift, mux->width,
1619                                mux->mux_flags, NULL);
1620                 atlas7_clks[ARRAY_SIZE(unit_list) + i] = clk;
1621                 BUG_ON(!clk);
1622         }
1623
1624         for (i = 0; i < ARRAY_SIZE(unit_list); i++) {
1625                 unit = &unit_list[i];
1626                 atlas7_clks[i] = atlas7_unit_clk_register(NULL, unit->unit_name, unit->parent_name,
1627                                 unit->flags, unit->regofs, unit->bit, unit->lock);
1628                 BUG_ON(!atlas7_clks[i]);
1629         }
1630
1631         clk_data.clks = atlas7_clks;
1632         clk_data.clk_num = ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list);
1633
1634         ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1635         BUG_ON(ret);
1636
1637         atlas7_rst_ctlr.of_node = np;
1638         atlas7_rst_ctlr.nr_resets = ARRAY_SIZE(atlas7_reset_unit);
1639         reset_controller_register(&atlas7_rst_ctlr);
1640 }
1641 CLK_OF_DECLARE(atlas7_clk, "sirf,atlas7-car", atlas7_clk_init);