2 * Copyright 2013 Emilio López
4 * Emilio López <emilio@elopez.com.ar>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clkdev.h>
20 #include <linux/of_address.h>
22 #include "clk-factors.h"
24 static DEFINE_SPINLOCK(clk_lock);
26 /* Maximum number of parents our clocks have */
27 #define SUNXI_MAX_PARENTS 5
30 * sun4i_osc_clk_setup() - Setup function for gatable oscillator
33 #define SUNXI_OSC24M_GATE 0
35 static void __init sun4i_osc_clk_setup(struct device_node *node)
38 struct clk_fixed_rate *fixed;
39 struct clk_gate *gate;
40 const char *clk_name = node->name;
43 if (of_property_read_u32(node, "clock-frequency", &rate))
46 /* allocate fixed-rate and gate clock structs */
47 fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
50 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
54 /* set up gate and fixed rate properties */
55 gate->reg = of_iomap(node, 0);
56 gate->bit_idx = SUNXI_OSC24M_GATE;
57 gate->lock = &clk_lock;
58 fixed->fixed_rate = rate;
60 clk = clk_register_composite(NULL, clk_name,
63 &fixed->hw, &clk_fixed_rate_ops,
64 &gate->hw, &clk_gate_ops,
70 of_clk_add_provider(node, of_clk_src_simple_get, clk);
71 clk_register_clkdev(clk, clk_name, NULL);
80 CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup);
85 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
86 * PLL1 rate is calculated as follows
87 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
88 * parent_rate is always 24Mhz
91 static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
92 u8 *n, u8 *k, u8 *m, u8 *p)
96 /* Normalize value to a 6M multiple */
97 div = *freq / 6000000;
98 *freq = 6000000 * div;
100 /* we were called to round the frequency, we can now return */
104 /* m is always zero for pll1 */
107 /* k is 1 only on these cases */
108 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
113 /* p will be 3 for divs under 10 */
117 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
118 else if (div < 20 || (div < 32 && (div & 1)))
121 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
122 * of divs between 40-62 */
123 else if (div < 40 || (div < 64 && (div & 2)))
126 /* any other entries have p = 0 */
130 /* calculate a suitable n based on k and p */
137 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
138 * PLL1 rate is calculated as follows
139 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
140 * parent_rate should always be 24MHz
142 static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
143 u8 *n, u8 *k, u8 *m, u8 *p)
146 * We can operate only on MHz, this will make our life easier
149 u32 freq_mhz = *freq / 1000000;
150 u32 parent_freq_mhz = parent_rate / 1000000;
153 * Round down the frequency to the closest multiple of either
156 u32 round_freq_6 = round_down(freq_mhz, 6);
157 u32 round_freq_16 = round_down(freq_mhz, 16);
159 if (round_freq_6 > round_freq_16)
160 freq_mhz = round_freq_6;
162 freq_mhz = round_freq_16;
164 *freq = freq_mhz * 1000000;
167 * If the factors pointer are null, we were just called to
168 * round down the frequency.
174 /* If the frequency is a multiple of 32 MHz, k is always 3 */
175 if (!(freq_mhz % 32))
177 /* If the frequency is a multiple of 9 MHz, k is always 2 */
178 else if (!(freq_mhz % 9))
180 /* If the frequency is a multiple of 8 MHz, k is always 1 */
181 else if (!(freq_mhz % 8))
183 /* Otherwise, we don't use the k factor */
188 * If the frequency is a multiple of 2 but not a multiple of
189 * 3, m is 3. This is the first time we use 6 here, yet we
190 * will use it on several other places.
191 * We use this number because it's the lowest frequency we can
192 * generate (with n = 0, k = 0, m = 3), so every other frequency
193 * somehow relates to this frequency.
195 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
198 * If the frequency is a multiple of 6MHz, but the factor is
201 else if ((freq_mhz / 6) & 1)
203 /* Otherwise, we end up with m = 1 */
207 /* Calculate n thanks to the above factors we already got */
208 *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
211 * If n end up being outbound, and that we can still decrease
214 if ((*n + 1) > 31 && (*m + 1) > 1) {
215 *n = (*n + 1) / 2 - 1;
216 *m = (*m + 1) / 2 - 1;
221 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
222 * PLL5 rate is calculated as follows
223 * rate = parent_rate * n * (k + 1)
224 * parent_rate is always 24Mhz
227 static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
228 u8 *n, u8 *k, u8 *m, u8 *p)
232 /* Normalize value to a parent_rate multiple (24M) */
233 div = *freq / parent_rate;
234 *freq = parent_rate * div;
236 /* we were called to round the frequency, we can now return */
242 else if (div / 2 < 31)
244 else if (div / 3 < 31)
249 *n = DIV_ROUND_UP(div, (*k+1));
255 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
256 * APB1 rate is calculated as follows
257 * rate = (parent_rate >> p) / (m + 1);
260 static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
261 u8 *n, u8 *k, u8 *m, u8 *p)
265 if (parent_rate < *freq)
268 parent_rate = (parent_rate + (*freq - 1)) / *freq;
271 if (parent_rate > 32)
274 if (parent_rate <= 4)
276 else if (parent_rate <= 8)
278 else if (parent_rate <= 16)
283 calcm = (parent_rate >> calcp) - 1;
285 *freq = (parent_rate >> calcp) / (calcm + 1);
287 /* we were called to round the frequency, we can now return */
298 * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
299 * MMC rate is calculated as follows
300 * rate = (parent_rate >> p) / (m + 1);
303 static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
304 u8 *n, u8 *k, u8 *m, u8 *p)
306 u8 div, calcm, calcp;
308 /* These clocks can only divide, so we will never be able to achieve
309 * frequencies higher than the parent frequency */
310 if (*freq > parent_rate)
313 div = parent_rate / *freq;
317 else if (div / 2 < 16)
319 else if (div / 4 < 16)
324 calcm = DIV_ROUND_UP(div, 1 << calcp);
326 *freq = (parent_rate >> calcp) / calcm;
328 /* we were called to round the frequency, we can now return */
339 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
340 * CLK_OUT rate is calculated as follows
341 * rate = (parent_rate >> p) / (m + 1);
344 static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
345 u8 *n, u8 *k, u8 *m, u8 *p)
347 u8 div, calcm, calcp;
349 /* These clocks can only divide, so we will never be able to achieve
350 * frequencies higher than the parent frequency */
351 if (*freq > parent_rate)
354 div = parent_rate / *freq;
358 else if (div / 2 < 32)
360 else if (div / 4 < 32)
365 calcm = DIV_ROUND_UP(div, 1 << calcp);
367 *freq = (parent_rate >> calcp) / calcm;
369 /* we were called to round the frequency, we can now return */
380 * sunxi_factors_clk_setup() - Setup function for factor clocks
383 #define SUNXI_FACTORS_MUX_MASK 0x3
385 struct factors_data {
388 struct clk_factors_config *table;
389 void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
392 static struct clk_factors_config sun4i_pll1_config = {
403 static struct clk_factors_config sun6i_a31_pll1_config = {
412 static struct clk_factors_config sun4i_pll5_config = {
419 static struct clk_factors_config sun4i_apb1_config = {
426 /* user manual says "n" but it's really "p" */
427 static struct clk_factors_config sun4i_mod0_config = {
434 /* user manual says "n" but it's really "p" */
435 static struct clk_factors_config sun7i_a20_out_config = {
442 static const struct factors_data sun4i_pll1_data __initconst = {
444 .table = &sun4i_pll1_config,
445 .getter = sun4i_get_pll1_factors,
448 static const struct factors_data sun6i_a31_pll1_data __initconst = {
450 .table = &sun6i_a31_pll1_config,
451 .getter = sun6i_a31_get_pll1_factors,
454 static const struct factors_data sun4i_pll5_data __initconst = {
456 .table = &sun4i_pll5_config,
457 .getter = sun4i_get_pll5_factors,
460 static const struct factors_data sun4i_apb1_data __initconst = {
461 .table = &sun4i_apb1_config,
462 .getter = sun4i_get_apb1_factors,
465 static const struct factors_data sun4i_mod0_data __initconst = {
468 .table = &sun4i_mod0_config,
469 .getter = sun4i_get_mod0_factors,
472 static const struct factors_data sun7i_a20_out_data __initconst = {
475 .table = &sun7i_a20_out_config,
476 .getter = sun7i_a20_get_out_factors,
479 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
480 const struct factors_data *data)
483 struct clk_factors *factors;
484 struct clk_gate *gate = NULL;
485 struct clk_mux *mux = NULL;
486 struct clk_hw *gate_hw = NULL;
487 struct clk_hw *mux_hw = NULL;
488 const char *clk_name = node->name;
489 const char *parents[SUNXI_MAX_PARENTS];
493 reg = of_iomap(node, 0);
495 /* if we have a mux, we will have >1 parents */
496 while (i < SUNXI_MAX_PARENTS &&
497 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
500 /* Nodes should be providing the name via clock-output-names
501 * but originally our dts didn't, and so we used node->name.
502 * The new, better nodes look like clk@deadbeef, so we pull the
503 * name just in this case */
504 if (!strcmp("clk", clk_name)) {
505 of_property_read_string_index(node, "clock-output-names",
509 factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
513 /* Add a gate if this factor clock can be gated */
515 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
521 /* set up gate properties */
523 gate->bit_idx = data->enable;
524 gate->lock = &clk_lock;
528 /* Add a mux if this factor clock can be muxed */
530 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
537 /* set up gate properties */
539 mux->shift = data->mux;
540 mux->mask = SUNXI_FACTORS_MUX_MASK;
541 mux->lock = &clk_lock;
545 /* set up factors properties */
547 factors->config = data->table;
548 factors->get_factors = data->getter;
549 factors->lock = &clk_lock;
551 clk = clk_register_composite(NULL, clk_name,
553 mux_hw, &clk_mux_ops,
554 &factors->hw, &clk_factors_ops,
555 gate_hw, &clk_gate_ops, 0);
558 of_clk_add_provider(node, of_clk_src_simple_get, clk);
559 clk_register_clkdev(clk, clk_name, NULL);
568 * sunxi_mux_clk_setup() - Setup function for muxes
571 #define SUNXI_MUX_GATE_WIDTH 2
577 static const struct mux_data sun4i_cpu_mux_data __initconst = {
581 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
585 static const struct mux_data sun4i_apb1_mux_data __initconst = {
589 static void __init sunxi_mux_clk_setup(struct device_node *node,
590 struct mux_data *data)
593 const char *clk_name = node->name;
594 const char *parents[SUNXI_MAX_PARENTS];
598 reg = of_iomap(node, 0);
600 while (i < SUNXI_MAX_PARENTS &&
601 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
604 clk = clk_register_mux(NULL, clk_name, parents, i,
605 CLK_SET_RATE_NO_REPARENT, reg,
606 data->shift, SUNXI_MUX_GATE_WIDTH,
610 of_clk_add_provider(node, of_clk_src_simple_get, clk);
611 clk_register_clkdev(clk, clk_name, NULL);
618 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
627 static const struct div_data sun4i_axi_data __initconst = {
633 static const struct div_data sun4i_ahb_data __initconst = {
639 static const struct div_data sun4i_apb0_data __initconst = {
645 static const struct div_data sun6i_a31_apb2_div_data __initconst = {
651 static void __init sunxi_divider_clk_setup(struct device_node *node,
652 struct div_data *data)
655 const char *clk_name = node->name;
656 const char *clk_parent;
659 reg = of_iomap(node, 0);
661 clk_parent = of_clk_get_parent_name(node, 0);
663 clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
664 reg, data->shift, data->width,
665 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
668 of_clk_add_provider(node, of_clk_src_simple_get, clk);
669 clk_register_clkdev(clk, clk_name, NULL);
676 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
679 #define SUNXI_GATES_MAX_SIZE 64
682 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
685 static const struct gates_data sun4i_axi_gates_data __initconst = {
689 static const struct gates_data sun4i_ahb_gates_data __initconst = {
690 .mask = {0x7F77FFF, 0x14FB3F},
693 static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
694 .mask = {0x147667e7, 0x185915},
697 static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
698 .mask = {0x107067e7, 0x185111},
701 static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
702 .mask = {0xEDFE7F62, 0x794F931},
705 static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
706 .mask = { 0x12f77fff, 0x16ff3f },
709 static const struct gates_data sun4i_apb0_gates_data __initconst = {
713 static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
717 static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
721 static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
725 static const struct gates_data sun4i_apb1_gates_data __initconst = {
729 static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
733 static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
737 static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
741 static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
745 static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
746 .mask = { 0xff80ff },
749 static void __init sunxi_gates_clk_setup(struct device_node *node,
750 struct gates_data *data)
752 struct clk_onecell_data *clk_data;
753 const char *clk_parent;
754 const char *clk_name;
761 reg = of_iomap(node, 0);
763 clk_parent = of_clk_get_parent_name(node, 0);
765 /* Worst-case size approximation and memory allocation */
766 qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
767 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
770 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
771 if (!clk_data->clks) {
776 for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
777 of_property_read_string_index(node, "clock-output-names",
780 /* No driver claims this clock, but it should remain gated */
781 ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
783 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
785 reg + 4 * (i/32), i % 32,
787 WARN_ON(IS_ERR(clk_data->clks[i]));
792 /* Adjust to the real max */
793 clk_data->clk_num = i;
795 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
801 * sunxi_divs_clk_setup() helper data
804 #define SUNXI_DIVS_MAX_QTY 2
805 #define SUNXI_DIVISOR_WIDTH 2
808 const struct factors_data *factors; /* data for the factor clock */
810 u8 fixed; /* is it a fixed divisor? if not... */
811 struct clk_div_table *table; /* is it a table based divisor? */
812 u8 shift; /* otherwise it's a normal divisor with this shift */
813 u8 pow; /* is it power-of-two based? */
814 u8 gate; /* is it independently gateable? */
815 } div[SUNXI_DIVS_MAX_QTY];
818 static struct clk_div_table pll6_sata_tbl[] = {
819 { .val = 0, .div = 6, },
820 { .val = 1, .div = 12, },
821 { .val = 2, .div = 18, },
822 { .val = 3, .div = 24, },
826 static const struct divs_data pll5_divs_data __initconst = {
827 .factors = &sun4i_pll5_data,
829 { .shift = 0, .pow = 0, }, /* M, DDR */
830 { .shift = 16, .pow = 1, }, /* P, other */
834 static const struct divs_data pll6_divs_data __initconst = {
835 .factors = &sun4i_pll5_data,
837 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
838 { .fixed = 2 }, /* P, other */
843 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
845 * These clocks look something like this
846 * ________________________
847 * | ___divisor 1---|----> to consumer
848 * parent >--| pll___/___divisor 2---|----> to consumer
849 * | \_______________|____> to consumer
850 * |________________________|
853 static void __init sunxi_divs_clk_setup(struct device_node *node,
854 struct divs_data *data)
856 struct clk_onecell_data *clk_data;
857 const char *parent = node->name;
858 const char *clk_name;
859 struct clk **clks, *pclk;
860 struct clk_hw *gate_hw, *rate_hw;
861 const struct clk_ops *rate_ops;
862 struct clk_gate *gate = NULL;
863 struct clk_fixed_factor *fix_factor;
864 struct clk_divider *divider;
869 /* Set up factor clock that we will be dividing */
870 pclk = sunxi_factors_clk_setup(node, data->factors);
872 reg = of_iomap(node, 0);
874 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
878 clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL);
882 clk_data->clks = clks;
884 /* It's not a good idea to have automatic reparenting changing
886 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
888 for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
889 if (of_property_read_string_index(node, "clock-output-names",
897 /* If this leaf clock can be gated, create a gate */
898 if (data->div[i].gate) {
899 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
904 gate->bit_idx = data->div[i].gate;
905 gate->lock = &clk_lock;
910 /* Leaves can be fixed or configurable divisors */
911 if (data->div[i].fixed) {
912 fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
916 fix_factor->mult = 1;
917 fix_factor->div = data->div[i].fixed;
919 rate_hw = &fix_factor->hw;
920 rate_ops = &clk_fixed_factor_ops;
922 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
926 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
929 divider->shift = data->div[i].shift;
930 divider->width = SUNXI_DIVISOR_WIDTH;
931 divider->flags = flags;
932 divider->lock = &clk_lock;
933 divider->table = data->div[i].table;
935 rate_hw = ÷r->hw;
936 rate_ops = &clk_divider_ops;
939 /* Wrap the (potential) gate and the divisor on a composite
940 * clock to unify them */
941 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
944 gate_hw, &clk_gate_ops,
947 WARN_ON(IS_ERR(clk_data->clks[i]));
948 clk_register_clkdev(clks[i], clk_name, NULL);
951 /* The last clock available on the getter is the parent */
954 /* Adjust to the real max */
955 clk_data->clk_num = i;
957 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
971 /* Matches for factors clocks */
972 static const struct of_device_id clk_factors_match[] __initconst = {
973 {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
974 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
975 {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
976 {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
977 {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
981 /* Matches for divider clocks */
982 static const struct of_device_id clk_div_match[] __initconst = {
983 {.compatible = "allwinner,sun4i-axi-clk", .data = &sun4i_axi_data,},
984 {.compatible = "allwinner,sun4i-ahb-clk", .data = &sun4i_ahb_data,},
985 {.compatible = "allwinner,sun4i-apb0-clk", .data = &sun4i_apb0_data,},
986 {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
990 /* Matches for divided outputs */
991 static const struct of_device_id clk_divs_match[] __initconst = {
992 {.compatible = "allwinner,sun4i-pll5-clk", .data = &pll5_divs_data,},
993 {.compatible = "allwinner,sun4i-pll6-clk", .data = &pll6_divs_data,},
997 /* Matches for mux clocks */
998 static const struct of_device_id clk_mux_match[] __initconst = {
999 {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
1000 {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
1001 {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
1005 /* Matches for gate clocks */
1006 static const struct of_device_id clk_gates_match[] __initconst = {
1007 {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
1008 {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
1009 {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
1010 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
1011 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
1012 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
1013 {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
1014 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
1015 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
1016 {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
1017 {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
1018 {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
1019 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
1020 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
1021 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
1022 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
1026 static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
1029 struct device_node *np;
1030 const struct div_data *data;
1031 const struct of_device_id *match;
1032 void (*setup_function)(struct device_node *, const void *) = function;
1034 for_each_matching_node(np, clk_match) {
1035 match = of_match_node(clk_match, np);
1037 setup_function(np, data);
1042 * System clock protection
1044 * By enabling these critical clocks, we prevent their accidental gating
1047 static void __init sunxi_clock_protect(void)
1051 /* memory bus clock - sun5i+ */
1052 clk = clk_get(NULL, "mbus");
1054 clk_prepare_enable(clk);
1058 /* DDR clock - sun4i+ */
1059 clk = clk_get(NULL, "pll5_ddr");
1061 clk_prepare_enable(clk);
1066 static void __init sunxi_init_clocks(void)
1068 /* Register factor clocks */
1069 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
1071 /* Register divider clocks */
1072 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
1074 /* Register divided output clocks */
1075 of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1077 /* Register mux clocks */
1078 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
1080 /* Register gate clocks */
1081 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
1083 /* Enable core system clocks */
1084 sunxi_clock_protect();
1086 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks);
1087 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks);
1088 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sunxi_init_clocks);
1089 CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sunxi_init_clocks);
1090 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sunxi_init_clocks);