2 * Copyright 2013 Emilio López
4 * Emilio López <emilio@elopez.com.ar>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/clkdev.h>
21 #include <linux/of_address.h>
22 #include <linux/reset-controller.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/log2.h>
27 #include "clk-factors.h"
29 static DEFINE_SPINLOCK(clk_lock);
31 /* Maximum number of parents our clocks have */
32 #define SUNXI_MAX_PARENTS 5
35 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
36 * PLL1 rate is calculated as follows
37 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
38 * parent_rate is always 24Mhz
41 static void sun4i_get_pll1_factors(struct factors_request *req)
45 /* Normalize value to a 6M multiple */
46 div = req->rate / 6000000;
47 req->rate = 6000000 * div;
49 /* m is always zero for pll1 */
52 /* k is 1 only on these cases */
53 if (req->rate >= 768000000 || req->rate == 42000000 ||
54 req->rate == 54000000)
59 /* p will be 3 for divs under 10 */
63 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
64 else if (div < 20 || (div < 32 && (div & 1)))
67 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
68 * of divs between 40-62 */
69 else if (div < 40 || (div < 64 && (div & 2)))
72 /* any other entries have p = 0 */
76 /* calculate a suitable n based on k and p */
83 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
84 * PLL1 rate is calculated as follows
85 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
86 * parent_rate should always be 24MHz
88 static void sun6i_a31_get_pll1_factors(struct factors_request *req)
91 * We can operate only on MHz, this will make our life easier
94 u32 freq_mhz = req->rate / 1000000;
95 u32 parent_freq_mhz = req->parent_rate / 1000000;
98 * Round down the frequency to the closest multiple of either
101 u32 round_freq_6 = round_down(freq_mhz, 6);
102 u32 round_freq_16 = round_down(freq_mhz, 16);
104 if (round_freq_6 > round_freq_16)
105 freq_mhz = round_freq_6;
107 freq_mhz = round_freq_16;
109 req->rate = freq_mhz * 1000000;
111 /* If the frequency is a multiple of 32 MHz, k is always 3 */
112 if (!(freq_mhz % 32))
114 /* If the frequency is a multiple of 9 MHz, k is always 2 */
115 else if (!(freq_mhz % 9))
117 /* If the frequency is a multiple of 8 MHz, k is always 1 */
118 else if (!(freq_mhz % 8))
120 /* Otherwise, we don't use the k factor */
125 * If the frequency is a multiple of 2 but not a multiple of
126 * 3, m is 3. This is the first time we use 6 here, yet we
127 * will use it on several other places.
128 * We use this number because it's the lowest frequency we can
129 * generate (with n = 0, k = 0, m = 3), so every other frequency
130 * somehow relates to this frequency.
132 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
135 * If the frequency is a multiple of 6MHz, but the factor is
138 else if ((freq_mhz / 6) & 1)
140 /* Otherwise, we end up with m = 1 */
144 /* Calculate n thanks to the above factors we already got */
145 req->n = freq_mhz * (req->m + 1) / ((req->k + 1) * parent_freq_mhz)
149 * If n end up being outbound, and that we can still decrease
152 if ((req->n + 1) > 31 && (req->m + 1) > 1) {
153 req->n = (req->n + 1) / 2 - 1;
154 req->m = (req->m + 1) / 2 - 1;
159 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
160 * PLL1 rate is calculated as follows
161 * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
162 * parent_rate is always 24Mhz
165 static void sun8i_a23_get_pll1_factors(struct factors_request *req)
169 /* Normalize value to a 6M multiple */
170 div = req->rate / 6000000;
171 req->rate = 6000000 * div;
173 /* m is always zero for pll1 */
176 /* k is 1 only on these cases */
177 if (req->rate >= 768000000 || req->rate == 42000000 ||
178 req->rate == 54000000)
183 /* p will be 2 for divs under 20 and odd divs under 32 */
184 if (div < 20 || (div < 32 && (div & 1)))
187 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
188 * of divs between 40-62 */
189 else if (div < 40 || (div < 64 && (div & 2)))
192 /* any other entries have p = 0 */
196 /* calculate a suitable n based on k and p */
199 req->n = div / 4 - 1;
203 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
204 * PLL5 rate is calculated as follows
205 * rate = parent_rate * n * (k + 1)
206 * parent_rate is always 24Mhz
209 static void sun4i_get_pll5_factors(struct factors_request *req)
213 /* Normalize value to a parent_rate multiple (24M) */
214 div = req->rate / req->parent_rate;
215 req->rate = req->parent_rate * div;
219 else if (div / 2 < 31)
221 else if (div / 3 < 31)
226 req->n = DIV_ROUND_UP(div, (req->k + 1));
230 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
231 * PLL6 rate is calculated as follows
232 * rate = parent_rate * (n + 1) * (k + 1) / 2
233 * parent_rate is always 24Mhz
236 static void sun6i_a31_get_pll6_factors(struct factors_request *req)
240 /* Normalize value to a parent_rate multiple (24M) */
241 div = req->rate / (req->parent_rate / 2);
242 req->rate = (req->parent_rate / 2) * div;
248 req->n = DIV_ROUND_UP(div, (req->k + 1)) - 1;
251 static void sun6i_a31_pll6_recalc(struct factors_request *req)
253 req->rate = req->parent_rate;
255 req->rate *= req->n + 1;
256 req->rate *= req->k + 1;
261 * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
262 * AHB rate is calculated as follows
263 * rate = parent_rate >> p
266 static void sun5i_a13_get_ahb_factors(struct factors_request *req)
271 if (req->parent_rate < req->rate)
272 req->rate = req->parent_rate;
275 * user manual says valid speed is 8k ~ 276M, but tests show it
276 * can work at speeds up to 300M, just after reparenting to pll6
278 if (req->rate < 8000)
280 if (req->rate > 300000000)
281 req->rate = 300000000;
283 div = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate));
289 req->rate = req->parent_rate >> div;
294 #define SUN6I_AHB1_PARENT_PLL6 3
297 * sun6i_a31_get_ahb_factors() - calculates m, p factors for AHB
298 * AHB rate is calculated as follows
299 * rate = parent_rate >> p
301 * if parent is pll6, then
302 * parent_rate = pll6 rate / (m + 1)
305 static void sun6i_get_ahb1_factors(struct factors_request *req)
307 u8 div, calcp, calcm = 1;
310 * clock can only divide, so we will never be able to achieve
311 * frequencies higher than the parent frequency
313 if (req->parent_rate && req->rate > req->parent_rate)
314 req->rate = req->parent_rate;
316 div = DIV_ROUND_UP(req->parent_rate, req->rate);
318 /* calculate pre-divider if parent is pll6 */
319 if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) {
322 else if (div / 2 < 4)
324 else if (div / 4 < 4)
329 calcm = DIV_ROUND_UP(div, 1 << calcp);
331 calcp = __roundup_pow_of_two(div);
332 calcp = calcp > 3 ? 3 : calcp;
335 req->rate = (req->parent_rate / calcm) >> calcp;
341 * sun6i_ahb1_recalc() - calculates AHB clock rate from m, p factors and
344 static void sun6i_ahb1_recalc(struct factors_request *req)
346 req->rate = req->parent_rate;
348 /* apply pre-divider first if parent is pll6 */
349 if (req->parent_index == SUN6I_AHB1_PARENT_PLL6)
350 req->rate /= req->m + 1;
353 req->rate >>= req->p;
357 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
358 * APB1 rate is calculated as follows
359 * rate = (parent_rate >> p) / (m + 1);
362 static void sun4i_get_apb1_factors(struct factors_request *req)
367 if (req->parent_rate < req->rate)
368 req->rate = req->parent_rate;
370 div = DIV_ROUND_UP(req->parent_rate, req->rate);
385 calcm = (req->parent_rate >> calcp) - 1;
387 req->rate = (req->parent_rate >> calcp) / (calcm + 1);
396 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
397 * CLK_OUT rate is calculated as follows
398 * rate = (parent_rate >> p) / (m + 1);
401 static void sun7i_a20_get_out_factors(struct factors_request *req)
403 u8 div, calcm, calcp;
405 /* These clocks can only divide, so we will never be able to achieve
406 * frequencies higher than the parent frequency */
407 if (req->rate > req->parent_rate)
408 req->rate = req->parent_rate;
410 div = DIV_ROUND_UP(req->parent_rate, req->rate);
414 else if (div / 2 < 32)
416 else if (div / 4 < 32)
421 calcm = DIV_ROUND_UP(div, 1 << calcp);
423 req->rate = (req->parent_rate >> calcp) / calcm;
429 * sunxi_factors_clk_setup() - Setup function for factor clocks
432 static const struct clk_factors_config sun4i_pll1_config = {
443 static const struct clk_factors_config sun6i_a31_pll1_config = {
453 static const struct clk_factors_config sun8i_a23_pll1_config = {
465 static const struct clk_factors_config sun4i_pll5_config = {
472 static const struct clk_factors_config sun6i_a31_pll6_config = {
480 static const struct clk_factors_config sun5i_a13_ahb_config = {
485 static const struct clk_factors_config sun6i_ahb1_config = {
492 static const struct clk_factors_config sun4i_apb1_config = {
499 /* user manual says "n" but it's really "p" */
500 static const struct clk_factors_config sun7i_a20_out_config = {
507 static const struct factors_data sun4i_pll1_data __initconst = {
509 .table = &sun4i_pll1_config,
510 .getter = sun4i_get_pll1_factors,
513 static const struct factors_data sun6i_a31_pll1_data __initconst = {
515 .table = &sun6i_a31_pll1_config,
516 .getter = sun6i_a31_get_pll1_factors,
519 static const struct factors_data sun8i_a23_pll1_data __initconst = {
521 .table = &sun8i_a23_pll1_config,
522 .getter = sun8i_a23_get_pll1_factors,
525 static const struct factors_data sun7i_a20_pll4_data __initconst = {
527 .table = &sun4i_pll5_config,
528 .getter = sun4i_get_pll5_factors,
531 static const struct factors_data sun4i_pll5_data __initconst = {
533 .table = &sun4i_pll5_config,
534 .getter = sun4i_get_pll5_factors,
538 static const struct factors_data sun4i_pll6_data __initconst = {
540 .table = &sun4i_pll5_config,
541 .getter = sun4i_get_pll5_factors,
545 static const struct factors_data sun6i_a31_pll6_data __initconst = {
547 .table = &sun6i_a31_pll6_config,
548 .getter = sun6i_a31_get_pll6_factors,
549 .recalc = sun6i_a31_pll6_recalc,
552 static const struct factors_data sun5i_a13_ahb_data __initconst = {
554 .muxmask = BIT(1) | BIT(0),
555 .table = &sun5i_a13_ahb_config,
556 .getter = sun5i_a13_get_ahb_factors,
559 static const struct factors_data sun6i_ahb1_data __initconst = {
561 .muxmask = BIT(1) | BIT(0),
562 .table = &sun6i_ahb1_config,
563 .getter = sun6i_get_ahb1_factors,
564 .recalc = sun6i_ahb1_recalc,
567 static const struct factors_data sun4i_apb1_data __initconst = {
569 .muxmask = BIT(1) | BIT(0),
570 .table = &sun4i_apb1_config,
571 .getter = sun4i_get_apb1_factors,
574 static const struct factors_data sun7i_a20_out_data __initconst = {
577 .muxmask = BIT(1) | BIT(0),
578 .table = &sun7i_a20_out_config,
579 .getter = sun7i_a20_get_out_factors,
582 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
583 const struct factors_data *data)
587 reg = of_iomap(node, 0);
589 pr_err("Could not get registers for factors-clk: %s\n",
594 return sunxi_factors_register(node, data, &clk_lock, reg);
597 static void __init sun4i_pll1_clk_setup(struct device_node *node)
599 sunxi_factors_clk_setup(node, &sun4i_pll1_data);
601 CLK_OF_DECLARE(sun4i_pll1, "allwinner,sun4i-a10-pll1-clk",
602 sun4i_pll1_clk_setup);
604 static void __init sun6i_pll1_clk_setup(struct device_node *node)
606 sunxi_factors_clk_setup(node, &sun6i_a31_pll1_data);
608 CLK_OF_DECLARE(sun6i_pll1, "allwinner,sun6i-a31-pll1-clk",
609 sun6i_pll1_clk_setup);
611 static void __init sun8i_pll1_clk_setup(struct device_node *node)
613 sunxi_factors_clk_setup(node, &sun8i_a23_pll1_data);
615 CLK_OF_DECLARE(sun8i_pll1, "allwinner,sun8i-a23-pll1-clk",
616 sun8i_pll1_clk_setup);
618 static void __init sun7i_pll4_clk_setup(struct device_node *node)
620 sunxi_factors_clk_setup(node, &sun7i_a20_pll4_data);
622 CLK_OF_DECLARE(sun7i_pll4, "allwinner,sun7i-a20-pll4-clk",
623 sun7i_pll4_clk_setup);
625 static void __init sun6i_pll6_clk_setup(struct device_node *node)
627 sunxi_factors_clk_setup(node, &sun6i_a31_pll6_data);
629 CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk",
630 sun6i_pll6_clk_setup);
632 static void __init sun5i_ahb_clk_setup(struct device_node *node)
634 sunxi_factors_clk_setup(node, &sun5i_a13_ahb_data);
636 CLK_OF_DECLARE(sun5i_ahb, "allwinner,sun5i-a13-ahb-clk",
637 sun5i_ahb_clk_setup);
639 static void __init sun6i_ahb1_clk_setup(struct device_node *node)
641 sunxi_factors_clk_setup(node, &sun6i_ahb1_data);
643 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
644 sun6i_ahb1_clk_setup);
646 static void __init sun4i_apb1_clk_setup(struct device_node *node)
648 sunxi_factors_clk_setup(node, &sun4i_apb1_data);
650 CLK_OF_DECLARE(sun4i_apb1, "allwinner,sun4i-a10-apb1-clk",
651 sun4i_apb1_clk_setup);
653 static void __init sun7i_out_clk_setup(struct device_node *node)
655 sunxi_factors_clk_setup(node, &sun7i_a20_out_data);
657 CLK_OF_DECLARE(sun7i_out, "allwinner,sun7i-a20-out-clk",
658 sun7i_out_clk_setup);
662 * sunxi_mux_clk_setup() - Setup function for muxes
665 #define SUNXI_MUX_GATE_WIDTH 2
671 static const struct mux_data sun4i_cpu_mux_data __initconst = {
675 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
679 static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
683 static struct clk * __init sunxi_mux_clk_setup(struct device_node *node,
684 const struct mux_data *data)
687 const char *clk_name = node->name;
688 const char *parents[SUNXI_MAX_PARENTS];
692 reg = of_iomap(node, 0);
694 i = of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS);
695 if (of_property_read_string(node, "clock-output-names", &clk_name)) {
696 pr_warn("%s: could not read clock-output-names for \"%s\"\n",
701 clk = clk_register_mux(NULL, clk_name, parents, i,
702 CLK_SET_RATE_PARENT, reg,
703 data->shift, SUNXI_MUX_GATE_WIDTH,
707 pr_warn("%s: failed to register mux clock %s: %ld\n", __func__,
708 clk_name, PTR_ERR(clk));
712 of_clk_add_provider(node, of_clk_src_simple_get, clk);
721 static void __init sun4i_cpu_clk_setup(struct device_node *node)
725 clk = sunxi_mux_clk_setup(node, &sun4i_cpu_mux_data);
729 /* Protect CPU clock */
731 clk_prepare_enable(clk);
733 CLK_OF_DECLARE(sun4i_cpu, "allwinner,sun4i-a10-cpu-clk",
734 sun4i_cpu_clk_setup);
736 static void __init sun6i_ahb1_mux_clk_setup(struct device_node *node)
738 sunxi_mux_clk_setup(node, &sun6i_a31_ahb1_mux_data);
740 CLK_OF_DECLARE(sun6i_ahb1_mux, "allwinner,sun6i-a31-ahb1-mux-clk",
741 sun6i_ahb1_mux_clk_setup);
743 static void __init sun8i_ahb2_clk_setup(struct device_node *node)
745 sunxi_mux_clk_setup(node, &sun8i_h3_ahb2_mux_data);
747 CLK_OF_DECLARE(sun8i_ahb2, "allwinner,sun8i-h3-ahb2-clk",
748 sun8i_ahb2_clk_setup);
752 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
759 const struct clk_div_table *table;
762 static const struct div_data sun4i_axi_data __initconst = {
768 static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
769 { .val = 0, .div = 1 },
770 { .val = 1, .div = 2 },
771 { .val = 2, .div = 3 },
772 { .val = 3, .div = 4 },
773 { .val = 4, .div = 4 },
774 { .val = 5, .div = 4 },
775 { .val = 6, .div = 4 },
776 { .val = 7, .div = 4 },
780 static const struct div_data sun8i_a23_axi_data __initconst = {
782 .table = sun8i_a23_axi_table,
785 static const struct div_data sun4i_ahb_data __initconst = {
791 static const struct clk_div_table sun4i_apb0_table[] __initconst = {
792 { .val = 0, .div = 2 },
793 { .val = 1, .div = 2 },
794 { .val = 2, .div = 4 },
795 { .val = 3, .div = 8 },
799 static const struct div_data sun4i_apb0_data __initconst = {
803 .table = sun4i_apb0_table,
806 static void __init sunxi_divider_clk_setup(struct device_node *node,
807 const struct div_data *data)
810 const char *clk_name = node->name;
811 const char *clk_parent;
814 reg = of_iomap(node, 0);
816 clk_parent = of_clk_get_parent_name(node, 0);
818 of_property_read_string(node, "clock-output-names", &clk_name);
820 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
821 reg, data->shift, data->width,
822 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
823 data->table, &clk_lock);
825 of_clk_add_provider(node, of_clk_src_simple_get, clk);
828 static void __init sun4i_ahb_clk_setup(struct device_node *node)
830 sunxi_divider_clk_setup(node, &sun4i_ahb_data);
832 CLK_OF_DECLARE(sun4i_ahb, "allwinner,sun4i-a10-ahb-clk",
833 sun4i_ahb_clk_setup);
835 static void __init sun4i_apb0_clk_setup(struct device_node *node)
837 sunxi_divider_clk_setup(node, &sun4i_apb0_data);
839 CLK_OF_DECLARE(sun4i_apb0, "allwinner,sun4i-a10-apb0-clk",
840 sun4i_apb0_clk_setup);
842 static void __init sun4i_axi_clk_setup(struct device_node *node)
844 sunxi_divider_clk_setup(node, &sun4i_axi_data);
846 CLK_OF_DECLARE(sun4i_axi, "allwinner,sun4i-a10-axi-clk",
847 sun4i_axi_clk_setup);
849 static void __init sun8i_axi_clk_setup(struct device_node *node)
851 sunxi_divider_clk_setup(node, &sun8i_a23_axi_data);
853 CLK_OF_DECLARE(sun8i_axi, "allwinner,sun8i-a23-axi-clk",
854 sun8i_axi_clk_setup);
859 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
862 #define SUNXI_GATES_MAX_SIZE 64
865 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
869 * sunxi_divs_clk_setup() helper data
872 #define SUNXI_DIVS_MAX_QTY 4
873 #define SUNXI_DIVISOR_WIDTH 2
876 const struct factors_data *factors; /* data for the factor clock */
877 int ndivs; /* number of outputs */
879 * List of outputs. Refer to the diagram for sunxi_divs_clk_setup():
880 * self or base factor clock refers to the output from the pll
881 * itself. The remaining refer to fixed or configurable divider
885 u8 self; /* is it the base factor clock? (only one) */
886 u8 fixed; /* is it a fixed divisor? if not... */
887 struct clk_div_table *table; /* is it a table based divisor? */
888 u8 shift; /* otherwise it's a normal divisor with this shift */
889 u8 pow; /* is it power-of-two based? */
890 u8 gate; /* is it independently gateable? */
891 } div[SUNXI_DIVS_MAX_QTY];
894 static struct clk_div_table pll6_sata_tbl[] = {
895 { .val = 0, .div = 6, },
896 { .val = 1, .div = 12, },
897 { .val = 2, .div = 18, },
898 { .val = 3, .div = 24, },
902 static const struct divs_data pll5_divs_data __initconst = {
903 .factors = &sun4i_pll5_data,
906 { .shift = 0, .pow = 0, }, /* M, DDR */
907 { .shift = 16, .pow = 1, }, /* P, other */
908 /* No output for the base factor clock */
912 static const struct divs_data pll6_divs_data __initconst = {
913 .factors = &sun4i_pll6_data,
916 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
917 { .fixed = 2 }, /* P, other */
918 { .self = 1 }, /* base factor clock, 2x */
919 { .fixed = 4 }, /* pll6 / 4, used as ahb input */
924 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
926 * These clocks look something like this
927 * ________________________
928 * | ___divisor 1---|----> to consumer
929 * parent >--| pll___/___divisor 2---|----> to consumer
930 * | \_______________|____> to consumer
931 * |________________________|
934 static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
935 const struct divs_data *data)
937 struct clk_onecell_data *clk_data;
939 const char *clk_name;
940 struct clk **clks, *pclk;
941 struct clk_hw *gate_hw, *rate_hw;
942 const struct clk_ops *rate_ops;
943 struct clk_gate *gate = NULL;
944 struct clk_fixed_factor *fix_factor;
945 struct clk_divider *divider;
947 int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
950 /* if number of children known, use it */
954 /* Set up factor clock that we will be dividing */
955 pclk = sunxi_factors_clk_setup(node, data->factors);
956 parent = __clk_get_name(pclk);
958 reg = of_iomap(node, 0);
960 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
964 clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL);
968 clk_data->clks = clks;
970 /* It's not a good idea to have automatic reparenting changing
972 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
974 for (i = 0; i < ndivs; i++) {
975 if (of_property_read_string_index(node, "clock-output-names",
979 /* If this is the base factor clock, only update clks */
980 if (data->div[i].self) {
981 clk_data->clks[i] = pclk;
989 /* If this leaf clock can be gated, create a gate */
990 if (data->div[i].gate) {
991 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
996 gate->bit_idx = data->div[i].gate;
997 gate->lock = &clk_lock;
1002 /* Leaves can be fixed or configurable divisors */
1003 if (data->div[i].fixed) {
1004 fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1008 fix_factor->mult = 1;
1009 fix_factor->div = data->div[i].fixed;
1011 rate_hw = &fix_factor->hw;
1012 rate_ops = &clk_fixed_factor_ops;
1014 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1018 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1021 divider->shift = data->div[i].shift;
1022 divider->width = SUNXI_DIVISOR_WIDTH;
1023 divider->flags = flags;
1024 divider->lock = &clk_lock;
1025 divider->table = data->div[i].table;
1027 rate_hw = ÷r->hw;
1028 rate_ops = &clk_divider_ops;
1031 /* Wrap the (potential) gate and the divisor on a composite
1032 * clock to unify them */
1033 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1036 gate_hw, &clk_gate_ops,
1039 WARN_ON(IS_ERR(clk_data->clks[i]));
1042 /* Adjust to the real max */
1043 clk_data->clk_num = i;
1045 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1058 static void __init sun4i_pll5_clk_setup(struct device_node *node)
1062 clks = sunxi_divs_clk_setup(node, &pll5_divs_data);
1066 /* Protect PLL5_DDR */
1068 clk_prepare_enable(clks[0]);
1070 CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
1071 sun4i_pll5_clk_setup);
1073 static void __init sun4i_pll6_clk_setup(struct device_node *node)
1075 sunxi_divs_clk_setup(node, &pll6_divs_data);
1077 CLK_OF_DECLARE(sun4i_pll6, "allwinner,sun4i-a10-pll6-clk",
1078 sun4i_pll6_clk_setup);