2 * linux/drivers/clocksource/arm_arch_timer.c
4 * Copyright (C) 2011 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/device.h>
14 #include <linux/smp.h>
15 #include <linux/cpu.h>
16 #include <linux/clockchips.h>
17 #include <linux/interrupt.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_address.h>
21 #include <linux/slab.h>
23 #include <asm/arch_timer.h>
26 #include <clocksource/arm_arch_timer.h>
29 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
31 #define CNTVCT_LO 0x08
32 #define CNTVCT_HI 0x0c
34 #define CNTP_TVAL 0x28
36 #define CNTV_TVAL 0x38
39 #define ARCH_CP15_TIMER BIT(0)
40 #define ARCH_MEM_TIMER BIT(1)
41 static unsigned arch_timers_present __initdata;
43 static void __iomem *arch_counter_base;
47 struct clock_event_device evt;
50 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
52 static u32 arch_timer_rate;
62 static int arch_timer_ppi[MAX_TIMER_PPI];
64 static struct clock_event_device __percpu *arch_timer_evt;
66 static bool arch_timer_use_virtual = true;
67 static bool arch_timer_mem_use_virtual;
70 * Architected system timer support.
73 static __always_inline
74 void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
75 struct clock_event_device *clk)
77 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
78 struct arch_timer *timer = to_arch_timer(clk);
80 case ARCH_TIMER_REG_CTRL:
81 writel_relaxed(val, timer->base + CNTP_CTL);
83 case ARCH_TIMER_REG_TVAL:
84 writel_relaxed(val, timer->base + CNTP_TVAL);
87 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
88 struct arch_timer *timer = to_arch_timer(clk);
90 case ARCH_TIMER_REG_CTRL:
91 writel_relaxed(val, timer->base + CNTV_CTL);
93 case ARCH_TIMER_REG_TVAL:
94 writel_relaxed(val, timer->base + CNTV_TVAL);
98 arch_timer_reg_write_cp15(access, reg, val);
102 static __always_inline
103 u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
104 struct clock_event_device *clk)
108 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
109 struct arch_timer *timer = to_arch_timer(clk);
111 case ARCH_TIMER_REG_CTRL:
112 val = readl_relaxed(timer->base + CNTP_CTL);
114 case ARCH_TIMER_REG_TVAL:
115 val = readl_relaxed(timer->base + CNTP_TVAL);
118 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
119 struct arch_timer *timer = to_arch_timer(clk);
121 case ARCH_TIMER_REG_CTRL:
122 val = readl_relaxed(timer->base + CNTV_CTL);
124 case ARCH_TIMER_REG_TVAL:
125 val = readl_relaxed(timer->base + CNTV_TVAL);
129 val = arch_timer_reg_read_cp15(access, reg);
135 static __always_inline irqreturn_t timer_handler(const int access,
136 struct clock_event_device *evt)
140 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
141 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
142 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
143 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
144 evt->event_handler(evt);
151 static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
153 struct clock_event_device *evt = dev_id;
155 return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
158 static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
160 struct clock_event_device *evt = dev_id;
162 return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
165 static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
167 struct clock_event_device *evt = dev_id;
169 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
172 static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
174 struct clock_event_device *evt = dev_id;
176 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
179 static __always_inline void timer_set_mode(const int access, int mode,
180 struct clock_event_device *clk)
184 case CLOCK_EVT_MODE_UNUSED:
185 case CLOCK_EVT_MODE_SHUTDOWN:
186 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
187 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
188 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
195 static void arch_timer_set_mode_virt(enum clock_event_mode mode,
196 struct clock_event_device *clk)
198 timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode, clk);
201 static void arch_timer_set_mode_phys(enum clock_event_mode mode,
202 struct clock_event_device *clk)
204 timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode, clk);
207 static void arch_timer_set_mode_virt_mem(enum clock_event_mode mode,
208 struct clock_event_device *clk)
210 timer_set_mode(ARCH_TIMER_MEM_VIRT_ACCESS, mode, clk);
213 static void arch_timer_set_mode_phys_mem(enum clock_event_mode mode,
214 struct clock_event_device *clk)
216 timer_set_mode(ARCH_TIMER_MEM_PHYS_ACCESS, mode, clk);
219 static __always_inline void set_next_event(const int access, unsigned long evt,
220 struct clock_event_device *clk)
223 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
224 ctrl |= ARCH_TIMER_CTRL_ENABLE;
225 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
226 arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
227 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
230 static int arch_timer_set_next_event_virt(unsigned long evt,
231 struct clock_event_device *clk)
233 set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
237 static int arch_timer_set_next_event_phys(unsigned long evt,
238 struct clock_event_device *clk)
240 set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
244 static int arch_timer_set_next_event_virt_mem(unsigned long evt,
245 struct clock_event_device *clk)
247 set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
251 static int arch_timer_set_next_event_phys_mem(unsigned long evt,
252 struct clock_event_device *clk)
254 set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
258 static void __arch_timer_setup(unsigned type,
259 struct clock_event_device *clk)
261 clk->features = CLOCK_EVT_FEAT_ONESHOT;
263 if (type == ARCH_CP15_TIMER) {
264 clk->features |= CLOCK_EVT_FEAT_C3STOP;
265 clk->name = "arch_sys_timer";
267 clk->cpumask = cpumask_of(smp_processor_id());
268 if (arch_timer_use_virtual) {
269 clk->irq = arch_timer_ppi[VIRT_PPI];
270 clk->set_mode = arch_timer_set_mode_virt;
271 clk->set_next_event = arch_timer_set_next_event_virt;
273 clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
274 clk->set_mode = arch_timer_set_mode_phys;
275 clk->set_next_event = arch_timer_set_next_event_phys;
278 clk->name = "arch_mem_timer";
280 clk->cpumask = cpu_all_mask;
281 if (arch_timer_mem_use_virtual) {
282 clk->set_mode = arch_timer_set_mode_virt_mem;
283 clk->set_next_event =
284 arch_timer_set_next_event_virt_mem;
286 clk->set_mode = arch_timer_set_mode_phys_mem;
287 clk->set_next_event =
288 arch_timer_set_next_event_phys_mem;
292 clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, clk);
294 clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
297 static int arch_timer_setup(struct clock_event_device *clk)
299 __arch_timer_setup(ARCH_CP15_TIMER, clk);
301 if (arch_timer_use_virtual)
302 enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
304 enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
305 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
306 enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
309 arch_counter_set_user_access();
315 arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
317 /* Who has more than one independent system counter? */
321 /* Try to determine the frequency from the device tree or CNTFRQ */
322 if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
324 arch_timer_rate = readl_relaxed(cntbase + CNTFRQ);
326 arch_timer_rate = arch_timer_get_cntfrq();
329 /* Check the timer frequency. */
330 if (arch_timer_rate == 0)
331 pr_warn("Architected timer frequency not available\n");
334 static void arch_timer_banner(unsigned type)
336 pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
337 type & ARCH_CP15_TIMER ? "cp15" : "",
338 type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "",
339 type & ARCH_MEM_TIMER ? "mmio" : "",
340 (unsigned long)arch_timer_rate / 1000000,
341 (unsigned long)(arch_timer_rate / 10000) % 100,
342 type & ARCH_CP15_TIMER ?
343 arch_timer_use_virtual ? "virt" : "phys" :
345 type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "",
346 type & ARCH_MEM_TIMER ?
347 arch_timer_mem_use_virtual ? "virt" : "phys" :
351 u32 arch_timer_get_rate(void)
353 return arch_timer_rate;
356 static u64 arch_counter_get_cntvct_mem(void)
358 u32 vct_lo, vct_hi, tmp_hi;
361 vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
362 vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
363 tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
364 } while (vct_hi != tmp_hi);
366 return ((u64) vct_hi << 32) | vct_lo;
370 * Default to cp15 based access because arm64 uses this function for
371 * sched_clock() before DT is probed and the cp15 method is guaranteed
372 * to exist on arm64. arm doesn't use this before DT is probed so even
373 * if we don't have the cp15 accessors we won't have a problem.
375 u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
377 static cycle_t arch_counter_read(struct clocksource *cs)
379 return arch_timer_read_counter();
382 static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
384 return arch_timer_read_counter();
387 static struct clocksource clocksource_counter = {
388 .name = "arch_sys_counter",
390 .read = arch_counter_read,
391 .mask = CLOCKSOURCE_MASK(56),
392 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
395 static struct cyclecounter cyclecounter = {
396 .read = arch_counter_read_cc,
397 .mask = CLOCKSOURCE_MASK(56),
400 static struct timecounter timecounter;
402 struct timecounter *arch_timer_get_timecounter(void)
407 static void __init arch_counter_register(unsigned type)
411 /* Register the CP15 based counter if we have one */
412 if (type & ARCH_CP15_TIMER)
413 arch_timer_read_counter = arch_counter_get_cntvct;
415 arch_timer_read_counter = arch_counter_get_cntvct_mem;
417 start_count = arch_timer_read_counter();
418 clocksource_register_hz(&clocksource_counter, arch_timer_rate);
419 cyclecounter.mult = clocksource_counter.mult;
420 cyclecounter.shift = clocksource_counter.shift;
421 timecounter_init(&timecounter, &cyclecounter, start_count);
424 static void arch_timer_stop(struct clock_event_device *clk)
426 pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
427 clk->irq, smp_processor_id());
429 if (arch_timer_use_virtual)
430 disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
432 disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
433 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
434 disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
437 clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
440 static int arch_timer_cpu_notify(struct notifier_block *self,
441 unsigned long action, void *hcpu)
444 * Grab cpu pointer in each case to avoid spurious
445 * preemptible warnings
447 switch (action & ~CPU_TASKS_FROZEN) {
449 arch_timer_setup(this_cpu_ptr(arch_timer_evt));
452 arch_timer_stop(this_cpu_ptr(arch_timer_evt));
459 static struct notifier_block arch_timer_cpu_nb = {
460 .notifier_call = arch_timer_cpu_notify,
463 static int __init arch_timer_register(void)
468 arch_timer_evt = alloc_percpu(struct clock_event_device);
469 if (!arch_timer_evt) {
474 if (arch_timer_use_virtual) {
475 ppi = arch_timer_ppi[VIRT_PPI];
476 err = request_percpu_irq(ppi, arch_timer_handler_virt,
477 "arch_timer", arch_timer_evt);
479 ppi = arch_timer_ppi[PHYS_SECURE_PPI];
480 err = request_percpu_irq(ppi, arch_timer_handler_phys,
481 "arch_timer", arch_timer_evt);
482 if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
483 ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
484 err = request_percpu_irq(ppi, arch_timer_handler_phys,
485 "arch_timer", arch_timer_evt);
487 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
493 pr_err("arch_timer: can't register interrupt %d (%d)\n",
498 err = register_cpu_notifier(&arch_timer_cpu_nb);
502 /* Immediately configure the timer on the boot CPU */
503 arch_timer_setup(this_cpu_ptr(arch_timer_evt));
508 if (arch_timer_use_virtual)
509 free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
511 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
513 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
514 free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
519 free_percpu(arch_timer_evt);
524 static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
528 struct arch_timer *t;
530 t = kzalloc(sizeof(*t), GFP_KERNEL);
536 __arch_timer_setup(ARCH_MEM_TIMER, &t->evt);
538 if (arch_timer_mem_use_virtual)
539 func = arch_timer_handler_virt_mem;
541 func = arch_timer_handler_phys_mem;
543 ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
545 pr_err("arch_timer: Failed to request mem timer irq\n");
552 static const struct of_device_id arch_timer_of_match[] __initconst = {
553 { .compatible = "arm,armv7-timer", },
554 { .compatible = "arm,armv8-timer", },
558 static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
559 { .compatible = "arm,armv7-timer-mem", },
563 static void __init arch_timer_common_init(void)
565 unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER;
567 /* Wait until both nodes are probed if we have two timers */
568 if ((arch_timers_present & mask) != mask) {
569 if (of_find_matching_node(NULL, arch_timer_mem_of_match) &&
570 !(arch_timers_present & ARCH_MEM_TIMER))
572 if (of_find_matching_node(NULL, arch_timer_of_match) &&
573 !(arch_timers_present & ARCH_CP15_TIMER))
577 arch_timer_banner(arch_timers_present);
578 arch_counter_register(arch_timers_present);
579 arch_timer_arch_init();
582 static void __init arch_timer_init(struct device_node *np)
586 if (arch_timers_present & ARCH_CP15_TIMER) {
587 pr_warn("arch_timer: multiple nodes in dt, skipping\n");
591 arch_timers_present |= ARCH_CP15_TIMER;
592 for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
593 arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
594 arch_timer_detect_rate(NULL, np);
597 * If HYP mode is available, we know that the physical timer
598 * has been configured to be accessible from PL1. Use it, so
599 * that a guest can use the virtual timer instead.
601 * If no interrupt provided for virtual timer, we'll have to
602 * stick to the physical timer. It'd better be accessible...
604 if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
605 arch_timer_use_virtual = false;
607 if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
608 !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
609 pr_warn("arch_timer: No interrupt available, giving up\n");
614 arch_timer_register();
615 arch_timer_common_init();
617 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init);
618 CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init);
620 static void __init arch_timer_mem_init(struct device_node *np)
622 struct device_node *frame, *best_frame = NULL;
623 void __iomem *cntctlbase, *base;
627 arch_timers_present |= ARCH_MEM_TIMER;
628 cntctlbase = of_iomap(np, 0);
630 pr_err("arch_timer: Can't find CNTCTLBase\n");
634 cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
638 * Try to find a virtual capable frame. Otherwise fall back to a
639 * physical capable frame.
641 for_each_available_child_of_node(np, frame) {
644 if (of_property_read_u32(frame, "frame-number", &n)) {
645 pr_err("arch_timer: Missing frame-number\n");
646 of_node_put(best_frame);
651 if (cnttidr & CNTTIDR_VIRT(n)) {
652 of_node_put(best_frame);
654 arch_timer_mem_use_virtual = true;
657 of_node_put(best_frame);
658 best_frame = of_node_get(frame);
661 base = arch_counter_base = of_iomap(best_frame, 0);
663 pr_err("arch_timer: Can't map frame's registers\n");
664 of_node_put(best_frame);
668 if (arch_timer_mem_use_virtual)
669 irq = irq_of_parse_and_map(best_frame, 1);
671 irq = irq_of_parse_and_map(best_frame, 0);
672 of_node_put(best_frame);
674 pr_err("arch_timer: Frame missing %s irq",
675 arch_timer_mem_use_virtual ? "virt" : "phys");
679 arch_timer_detect_rate(base, np);
680 arch_timer_mem_register(base, irq);
681 arch_timer_common_init();
683 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
684 arch_timer_mem_init);