drivers/clocksource/cadence_ttc_timer.c

   1 /*
   2  * This file contains driver for the Cadence Triple Timer Counter Rev 06
   3  *
   4  *  Copyright (C) 2011-2013 Xilinx
   5  *
   6  * based on arch/mips/kernel/time.c timer driver
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/clockchips.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/slab.h>
  24 #include <linux/sched_clock.h>
  25
  26 /*
  27  * This driver configures the 2 16/32-bit count-up timers as follows:
  28  *
  29  * T1: Timer 1, clocksource for generic timekeeping
  30  * T2: Timer 2, clockevent source for hrtimers
  31  * T3: Timer 3, <unused>
  32  *
  33  * The input frequency to the timer module for emulation is 2.5MHz which is
  34  * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
  35  * the timers are clocked at 78.125KHz (12.8 us resolution).
  36
  37  * The input frequency to the timer module in silicon is configurable and
  38  * obtained from device tree. The pre-scaler of 32 is used.
  39  */
  40
  41 /*
  42  * Timer Register Offset Definitions of Timer 1, Increment base address by 4
  43  * and use same offsets for Timer 2
  44  */
  45 #define TTC_CLK_CNTRL_OFFSET            0x00 /* Clock Control Reg, RW */
  46 #define TTC_CNT_CNTRL_OFFSET            0x0C /* Counter Control Reg, RW */
  47 #define TTC_COUNT_VAL_OFFSET            0x18 /* Counter Value Reg, RO */
  48 #define TTC_INTR_VAL_OFFSET             0x24 /* Interval Count Reg, RW */
  49 #define TTC_ISR_OFFSET          0x54 /* Interrupt Status Reg, RO */
  50 #define TTC_IER_OFFSET          0x60 /* Interrupt Enable Reg, RW */
  51
  52 #define TTC_CNT_CNTRL_DISABLE_MASK      0x1
  53
  54 #define TTC_CLK_CNTRL_CSRC_MASK         (1 << 5)        /* clock source */
  55 #define TTC_CLK_CNTRL_PSV_MASK          0x1e
  56 #define TTC_CLK_CNTRL_PSV_SHIFT         1
  57
  58 /*
  59  * Setup the timers to use pre-scaling, using a fixed value for now that will
  60  * work across most input frequency, but it may need to be more dynamic
  61  */
  62 #define PRESCALE_EXPONENT       11      /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
  63 #define PRESCALE                2048    /* The exponent must match this */
  64 #define CLK_CNTRL_PRESCALE      ((PRESCALE_EXPONENT - 1) << 1)
  65 #define CLK_CNTRL_PRESCALE_EN   1
  66 #define CNT_CNTRL_RESET         (1 << 4)
  67
  68 #define MAX_F_ERR 50
  69
  70 /**
  71  * struct ttc_timer - This definition defines local timer structure
  72  *
  73  * @base_addr:  Base address of timer
  74  * @freq:       Timer input clock frequency
  75  * @clk:        Associated clock source
  76  * @clk_rate_change_nb  Notifier block for clock rate changes
  77  */
  78 struct ttc_timer {
  79         void __iomem *base_addr;
  80         unsigned long freq;
  81         struct clk *clk;
  82         struct notifier_block clk_rate_change_nb;
  83 };
  84
  85 #define to_ttc_timer(x) \
  86                 container_of(x, struct ttc_timer, clk_rate_change_nb)
  87
  88 struct ttc_timer_clocksource {
  89         u32                     scale_clk_ctrl_reg_old;
  90         u32                     scale_clk_ctrl_reg_new;
  91         struct ttc_timer        ttc;
  92         struct clocksource      cs;
  93 };
  94
  95 #define to_ttc_timer_clksrc(x) \
  96                 container_of(x, struct ttc_timer_clocksource, cs)
  97
  98 struct ttc_timer_clockevent {
  99         struct ttc_timer                ttc;
 100         struct clock_event_device       ce;
 101 };
 102
 103 #define to_ttc_timer_clkevent(x) \
 104                 container_of(x, struct ttc_timer_clockevent, ce)
 105
 106 static void __iomem *ttc_sched_clock_val_reg;
 107
 108 /**
 109  * ttc_set_interval - Set the timer interval value
 110  *
 111  * @timer:      Pointer to the timer instance
 112  * @cycles:     Timer interval ticks
 113  **/
 114 static void ttc_set_interval(struct ttc_timer *timer,
 115                                         unsigned long cycles)
 116 {
 117         u32 ctrl_reg;
 118
 119         /* Disable the counter, set the counter value  and re-enable counter */
 120         ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 121         ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
 122         writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 123
 124         writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
 125
 126         /*
 127          * Reset the counter (0x10) so that it starts from 0, one-shot
 128          * mode makes this needed for timing to be right.
 129          */
 130         ctrl_reg |= CNT_CNTRL_RESET;
 131         ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
 132         writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 133 }
 134
 135 /**
 136  * ttc_clock_event_interrupt - Clock event timer interrupt handler
 137  *
 138  * @irq:        IRQ number of the Timer
 139  * @dev_id:     void pointer to the ttc_timer instance
 140  *
 141  * returns: Always IRQ_HANDLED - success
 142  **/
 143 static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
 144 {
 145         struct ttc_timer_clockevent *ttce = dev_id;
 146         struct ttc_timer *timer = &ttce->ttc;
 147
 148         /* Acknowledge the interrupt and call event handler */
 149         readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
 150
 151         ttce->ce.event_handler(&ttce->ce);
 152
 153         return IRQ_HANDLED;
 154 }
 155
 156 /**
 157  * __ttc_clocksource_read - Reads the timer counter register
 158  *
 159  * returns: Current timer counter register value
 160  **/
 161 static cycle_t __ttc_clocksource_read(struct clocksource *cs)
 162 {
 163         struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
 164
 165         return (cycle_t)readl_relaxed(timer->base_addr +
 166                                 TTC_COUNT_VAL_OFFSET);
 167 }
 168
 169 static u64 notrace ttc_sched_clock_read(void)
 170 {
 171         return readl_relaxed(ttc_sched_clock_val_reg);
 172 }
 173
 174 /**
 175  * ttc_set_next_event - Sets the time interval for next event
 176  *
 177  * @cycles:     Timer interval ticks
 178  * @evt:        Address of clock event instance
 179  *
 180  * returns: Always 0 - success
 181  **/
 182 static int ttc_set_next_event(unsigned long cycles,
 183                                         struct clock_event_device *evt)
 184 {
 185         struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
 186         struct ttc_timer *timer = &ttce->ttc;
 187
 188         ttc_set_interval(timer, cycles);
 189         return 0;
 190 }
 191
 192 /**
 193  * ttc_set_mode - Sets the mode of timer
 194  *
 195  * @mode:       Mode to be set
 196  * @evt:        Address of clock event instance
 197  **/
 198 static void ttc_set_mode(enum clock_event_mode mode,
 199                                         struct clock_event_device *evt)
 200 {
 201         struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
 202         struct ttc_timer *timer = &ttce->ttc;
 203         u32 ctrl_reg;
 204
 205         switch (mode) {
 206         case CLOCK_EVT_MODE_PERIODIC:
 207                 ttc_set_interval(timer, DIV_ROUND_CLOSEST(ttce->ttc.freq,
 208                                                 PRESCALE * HZ));
 209                 break;
 210         case CLOCK_EVT_MODE_ONESHOT:
 211         case CLOCK_EVT_MODE_UNUSED:
 212         case CLOCK_EVT_MODE_SHUTDOWN:
 213                 ctrl_reg = readl_relaxed(timer->base_addr +
 214                                         TTC_CNT_CNTRL_OFFSET);
 215                 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
 216                 writel_relaxed(ctrl_reg,
 217                                 timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 218                 break;
 219         case CLOCK_EVT_MODE_RESUME:
 220                 ctrl_reg = readl_relaxed(timer->base_addr +
 221                                         TTC_CNT_CNTRL_OFFSET);
 222                 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
 223                 writel_relaxed(ctrl_reg,
 224                                 timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 225                 break;
 226         }
 227 }
 228
 229 static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
 230                 unsigned long event, void *data)
 231 {
 232         struct clk_notifier_data *ndata = data;
 233         struct ttc_timer *ttc = to_ttc_timer(nb);
 234         struct ttc_timer_clocksource *ttccs = container_of(ttc,
 235                         struct ttc_timer_clocksource, ttc);
 236
 237         switch (event) {
 238         case PRE_RATE_CHANGE:
 239         {
 240                 u32 psv;
 241                 unsigned long factor, rate_low, rate_high;
 242
 243                 if (ndata->new_rate > ndata->old_rate) {
 244                         factor = DIV_ROUND_CLOSEST(ndata->new_rate,
 245                                         ndata->old_rate);
 246                         rate_low = ndata->old_rate;
 247                         rate_high = ndata->new_rate;
 248                 } else {
 249                         factor = DIV_ROUND_CLOSEST(ndata->old_rate,
 250                                         ndata->new_rate);
 251                         rate_low = ndata->new_rate;
 252                         rate_high = ndata->old_rate;
 253                 }
 254
 255                 if (!is_power_of_2(factor))
 256                                 return NOTIFY_BAD;
 257
 258                 if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
 259                         return NOTIFY_BAD;
 260
 261                 factor = __ilog2_u32(factor);
 262
 263                 /*
 264                  * store timer clock ctrl register so we can restore it in case
 265                  * of an abort.
 266                  */
 267                 ttccs->scale_clk_ctrl_reg_old =
 268                         readl_relaxed(ttccs->ttc.base_addr +
 269                         TTC_CLK_CNTRL_OFFSET);
 270
 271                 psv = (ttccs->scale_clk_ctrl_reg_old &
 272                                 TTC_CLK_CNTRL_PSV_MASK) >>
 273                                 TTC_CLK_CNTRL_PSV_SHIFT;
 274                 if (ndata->new_rate < ndata->old_rate)
 275                         psv -= factor;
 276                 else
 277                         psv += factor;
 278
 279                 /* prescaler within legal range? */
 280                 if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
 281                         return NOTIFY_BAD;
 282
 283                 ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
 284                         ~TTC_CLK_CNTRL_PSV_MASK;
 285                 ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT;
 286
 287
 288                 /* scale down: adjust divider in post-change notification */
 289                 if (ndata->new_rate < ndata->old_rate)
 290                         return NOTIFY_DONE;
 291
 292                 /* scale up: adjust divider now - before frequency change */
 293                 writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
 294                                ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
 295                 break;
 296         }
 297         case POST_RATE_CHANGE:
 298                 /* scale up: pre-change notification did the adjustment */
 299                 if (ndata->new_rate > ndata->old_rate)
 300                         return NOTIFY_OK;
 301
 302                 /* scale down: adjust divider now - after frequency change */
 303                 writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
 304                                ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
 305                 break;
 306
 307         case ABORT_RATE_CHANGE:
 308                 /* we have to undo the adjustment in case we scale up */
 309                 if (ndata->new_rate < ndata->old_rate)
 310                         return NOTIFY_OK;
 311
 312                 /* restore original register value */
 313                 writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
 314                                ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
 315                 /* fall through */
 316         default:
 317                 return NOTIFY_DONE;
 318         }
 319
 320         return NOTIFY_DONE;
 321 }
 322
 323 static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base,
 324                                          u32 timer_width)
 325 {
 326         struct ttc_timer_clocksource *ttccs;
 327         int err;
 328
 329         ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
 330         if (WARN_ON(!ttccs))
 331                 return;
 332
 333         ttccs->ttc.clk = clk;
 334
 335         err = clk_prepare_enable(ttccs->ttc.clk);
 336         if (WARN_ON(err)) {
 337                 kfree(ttccs);
 338                 return;
 339         }
 340
 341         ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
 342
 343         ttccs->ttc.clk_rate_change_nb.notifier_call =
 344                 ttc_rate_change_clocksource_cb;
 345         ttccs->ttc.clk_rate_change_nb.next = NULL;
 346         if (clk_notifier_register(ttccs->ttc.clk,
 347                                 &ttccs->ttc.clk_rate_change_nb))
 348                 pr_warn("Unable to register clock notifier.\n");
 349
 350         ttccs->ttc.base_addr = base;
 351         ttccs->cs.name = "ttc_clocksource";
 352         ttccs->cs.rating = 200;
 353         ttccs->cs.read = __ttc_clocksource_read;
 354         ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
 355         ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
 356
 357         /*
 358          * Setup the clock source counter to be an incrementing counter
 359          * with no interrupt and it rolls over at 0xFFFF. Pre-scale
 360          * it by 32 also. Let it start running now.
 361          */
 362         writel_relaxed(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);
 363         writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
 364                      ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
 365         writel_relaxed(CNT_CNTRL_RESET,
 366                      ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
 367
 368         err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
 369         if (WARN_ON(err)) {
 370                 kfree(ttccs);
 371                 return;
 372         }
 373
 374         ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
 375         sched_clock_register(ttc_sched_clock_read, timer_width,
 376                              ttccs->ttc.freq / PRESCALE);
 377 }
 378
 379 static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
 380                 unsigned long event, void *data)
 381 {
 382         struct clk_notifier_data *ndata = data;
 383         struct ttc_timer *ttc = to_ttc_timer(nb);
 384         struct ttc_timer_clockevent *ttcce = container_of(ttc,
 385                         struct ttc_timer_clockevent, ttc);
 386
 387         switch (event) {
 388         case POST_RATE_CHANGE:
 389                 /* update cached frequency */
 390                 ttc->freq = ndata->new_rate;
 391
 392                 clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
 393
 394                 /* fall through */
 395         case PRE_RATE_CHANGE:
 396         case ABORT_RATE_CHANGE:
 397         default:
 398                 return NOTIFY_DONE;
 399         }
 400 }
 401
 402 static void __init ttc_setup_clockevent(struct clk *clk,
 403                                                 void __iomem *base, u32 irq)
 404 {
 405         struct ttc_timer_clockevent *ttcce;
 406         int err;
 407
 408         ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
 409         if (WARN_ON(!ttcce))
 410                 return;
 411
 412         ttcce->ttc.clk = clk;
 413
 414         err = clk_prepare_enable(ttcce->ttc.clk);
 415         if (WARN_ON(err)) {
 416                 kfree(ttcce);
 417                 return;
 418         }
 419
 420         ttcce->ttc.clk_rate_change_nb.notifier_call =
 421                 ttc_rate_change_clockevent_cb;
 422         ttcce->ttc.clk_rate_change_nb.next = NULL;
 423         if (clk_notifier_register(ttcce->ttc.clk,
 424                                 &ttcce->ttc.clk_rate_change_nb))
 425                 pr_warn("Unable to register clock notifier.\n");
 426         ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
 427
 428         ttcce->ttc.base_addr = base;
 429         ttcce->ce.name = "ttc_clockevent";
 430         ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
 431         ttcce->ce.set_next_event = ttc_set_next_event;
 432         ttcce->ce.set_mode = ttc_set_mode;
 433         ttcce->ce.rating = 200;
 434         ttcce->ce.irq = irq;
 435         ttcce->ce.cpumask = cpu_possible_mask;
 436
 437         /*
 438          * Setup the clock event timer to be an interval timer which
 439          * is prescaled by 32 using the interval interrupt. Leave it
 440          * disabled for now.
 441          */
 442         writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
 443         writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
 444                      ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
 445         writel_relaxed(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);
 446
 447         err = request_irq(irq, ttc_clock_event_interrupt,
 448                           IRQF_TIMER, ttcce->ce.name, ttcce);
 449         if (WARN_ON(err)) {
 450                 kfree(ttcce);
 451                 return;
 452         }
 453
 454         clockevents_config_and_register(&ttcce->ce,
 455                         ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
 456 }
 457
 458 /**
 459  * ttc_timer_init - Initialize the timer
 460  *
 461  * Initializes the timer hardware and register the clock source and clock event
 462  * timers with Linux kernal timer framework
 463  */
 464 static void __init ttc_timer_init(struct device_node *timer)
 465 {
 466         unsigned int irq;
 467         void __iomem *timer_baseaddr;
 468         struct clk *clk_cs, *clk_ce;
 469         static int initialized;
 470         int clksel;
 471         u32 timer_width = 16;
 472
 473         if (initialized)
 474                 return;
 475
 476         initialized = 1;
 477
 478         /*
 479          * Get the 1st Triple Timer Counter (TTC) block from the device tree
 480          * and use it. Note that the event timer uses the interrupt and it's the
 481          * 2nd TTC hence the irq_of_parse_and_map(,1)
 482          */
 483         timer_baseaddr = of_iomap(timer, 0);
 484         if (!timer_baseaddr) {
 485                 pr_err("ERROR: invalid timer base address\n");
 486                 BUG();
 487         }
 488
 489         irq = irq_of_parse_and_map(timer, 1);
 490         if (irq <= 0) {
 491                 pr_err("ERROR: invalid interrupt number\n");
 492                 BUG();
 493         }
 494
 495         of_property_read_u32(timer, "timer-width", &timer_width);
 496
 497         clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
 498         clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
 499         clk_cs = of_clk_get(timer, clksel);
 500         if (IS_ERR(clk_cs)) {
 501                 pr_err("ERROR: timer input clock not found\n");
 502                 BUG();
 503         }
 504
 505         clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
 506         clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
 507         clk_ce = of_clk_get(timer, clksel);
 508         if (IS_ERR(clk_ce)) {
 509                 pr_err("ERROR: timer input clock not found\n");
 510                 BUG();
 511         }
 512
 513         ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
 514         ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
 515
 516         pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
 517 }
 518
 519 CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);