drivers/crypto/sunxi-ss/sun4i-ss-core.c

   1 /*
   2  * sun4i-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC
   3  *
   4  * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
   5  *
   6  * Core file which registers crypto algorithms supported by the SS.
   7  *
   8  * You could find a link for the datasheet in Documentation/arm/sunxi/README
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/crypto.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <crypto/scatterwalk.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/reset.h>
  26
  27 #include "sun4i-ss.h"
  28
  29 static struct sun4i_ss_alg_template ss_algs[] = {
  30 {       .type = CRYPTO_ALG_TYPE_AHASH,
  31         .mode = SS_OP_MD5,
  32         .alg.hash = {
  33                 .init = sun4i_hash_init,
  34                 .update = sun4i_hash_update,
  35                 .final = sun4i_hash_final,
  36                 .finup = sun4i_hash_finup,
  37                 .digest = sun4i_hash_digest,
  38                 .export = sun4i_hash_export_md5,
  39                 .import = sun4i_hash_import_md5,
  40                 .halg = {
  41                         .digestsize = MD5_DIGEST_SIZE,
  42                         .base = {
  43                                 .cra_name = "md5",
  44                                 .cra_driver_name = "md5-sun4i-ss",
  45                                 .cra_priority = 300,
  46                                 .cra_alignmask = 3,
  47                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH,
  48                                 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
  49                                 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
  50                                 .cra_module = THIS_MODULE,
  51                                 .cra_type = &crypto_ahash_type,
  52                                 .cra_init = sun4i_hash_crainit
  53                         }
  54                 }
  55         }
  56 },
  57 {       .type = CRYPTO_ALG_TYPE_AHASH,
  58         .mode = SS_OP_SHA1,
  59         .alg.hash = {
  60                 .init = sun4i_hash_init,
  61                 .update = sun4i_hash_update,
  62                 .final = sun4i_hash_final,
  63                 .finup = sun4i_hash_finup,
  64                 .digest = sun4i_hash_digest,
  65                 .export = sun4i_hash_export_sha1,
  66                 .import = sun4i_hash_import_sha1,
  67                 .halg = {
  68                         .digestsize = SHA1_DIGEST_SIZE,
  69                         .base = {
  70                                 .cra_name = "sha1",
  71                                 .cra_driver_name = "sha1-sun4i-ss",
  72                                 .cra_priority = 300,
  73                                 .cra_alignmask = 3,
  74                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH,
  75                                 .cra_blocksize = SHA1_BLOCK_SIZE,
  76                                 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
  77                                 .cra_module = THIS_MODULE,
  78                                 .cra_type = &crypto_ahash_type,
  79                                 .cra_init = sun4i_hash_crainit
  80                         }
  81                 }
  82         }
  83 },
  84 {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
  85         .alg.crypto = {
  86                 .cra_name = "cbc(aes)",
  87                 .cra_driver_name = "cbc-aes-sun4i-ss",
  88                 .cra_priority = 300,
  89                 .cra_blocksize = AES_BLOCK_SIZE,
  90                 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
  91                 .cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
  92                 .cra_module = THIS_MODULE,
  93                 .cra_alignmask = 3,
  94                 .cra_type = &crypto_ablkcipher_type,
  95                 .cra_init = sun4i_ss_cipher_init,
  96                 .cra_ablkcipher = {
  97                         .min_keysize    = AES_MIN_KEY_SIZE,
  98                         .max_keysize    = AES_MAX_KEY_SIZE,
  99                         .ivsize         = AES_BLOCK_SIZE,
 100                         .setkey         = sun4i_ss_aes_setkey,
 101                         .encrypt        = sun4i_ss_cbc_aes_encrypt,
 102                         .decrypt        = sun4i_ss_cbc_aes_decrypt,
 103                 }
 104         }
 105 },
 106 {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
 107         .alg.crypto = {
 108                 .cra_name = "ecb(aes)",
 109                 .cra_driver_name = "ecb-aes-sun4i-ss",
 110                 .cra_priority = 300,
 111                 .cra_blocksize = AES_BLOCK_SIZE,
 112                 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
 113                 .cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
 114                 .cra_module = THIS_MODULE,
 115                 .cra_alignmask = 3,
 116                 .cra_type = &crypto_ablkcipher_type,
 117                 .cra_init = sun4i_ss_cipher_init,
 118                 .cra_ablkcipher = {
 119                         .min_keysize    = AES_MIN_KEY_SIZE,
 120                         .max_keysize    = AES_MAX_KEY_SIZE,
 121                         .ivsize         = AES_BLOCK_SIZE,
 122                         .setkey         = sun4i_ss_aes_setkey,
 123                         .encrypt        = sun4i_ss_ecb_aes_encrypt,
 124                         .decrypt        = sun4i_ss_ecb_aes_decrypt,
 125                 }
 126         }
 127 },
 128 {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
 129         .alg.crypto = {
 130                 .cra_name = "cbc(des)",
 131                 .cra_driver_name = "cbc-des-sun4i-ss",
 132                 .cra_priority = 300,
 133                 .cra_blocksize = DES_BLOCK_SIZE,
 134                 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
 135                 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
 136                 .cra_module = THIS_MODULE,
 137                 .cra_alignmask = 3,
 138                 .cra_type = &crypto_ablkcipher_type,
 139                 .cra_init = sun4i_ss_cipher_init,
 140                 .cra_u.ablkcipher = {
 141                         .min_keysize    = DES_KEY_SIZE,
 142                         .max_keysize    = DES_KEY_SIZE,
 143                         .ivsize         = DES_BLOCK_SIZE,
 144                         .setkey         = sun4i_ss_des_setkey,
 145                         .encrypt        = sun4i_ss_cbc_des_encrypt,
 146                         .decrypt        = sun4i_ss_cbc_des_decrypt,
 147                 }
 148         }
 149 },
 150 {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
 151         .alg.crypto = {
 152                 .cra_name = "ecb(des)",
 153                 .cra_driver_name = "ecb-des-sun4i-ss",
 154                 .cra_priority = 300,
 155                 .cra_blocksize = DES_BLOCK_SIZE,
 156                 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
 157                 .cra_ctxsize = sizeof(struct sun4i_req_ctx),
 158                 .cra_module = THIS_MODULE,
 159                 .cra_alignmask = 3,
 160                 .cra_type = &crypto_ablkcipher_type,
 161                 .cra_init = sun4i_ss_cipher_init,
 162                 .cra_u.ablkcipher = {
 163                         .min_keysize    = DES_KEY_SIZE,
 164                         .max_keysize    = DES_KEY_SIZE,
 165                         .setkey         = sun4i_ss_des_setkey,
 166                         .encrypt        = sun4i_ss_ecb_des_encrypt,
 167                         .decrypt        = sun4i_ss_ecb_des_decrypt,
 168                 }
 169         }
 170 },
 171 {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
 172         .alg.crypto = {
 173                         .cra_name = "cbc(des3_ede)",
 174                         .cra_driver_name = "cbc-des3-sun4i-ss",
 175                         .cra_priority = 300,
 176                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
 177                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
 178                         .cra_ctxsize = sizeof(struct sun4i_req_ctx),
 179                         .cra_module = THIS_MODULE,
 180                         .cra_alignmask = 3,
 181                         .cra_type = &crypto_ablkcipher_type,
 182                         .cra_init = sun4i_ss_cipher_init,
 183                         .cra_u.ablkcipher = {
 184                                 .min_keysize    = DES3_EDE_KEY_SIZE,
 185                                 .max_keysize    = DES3_EDE_KEY_SIZE,
 186                                 .ivsize         = DES3_EDE_BLOCK_SIZE,
 187                                 .setkey         = sun4i_ss_des3_setkey,
 188                                 .encrypt        = sun4i_ss_cbc_des3_encrypt,
 189                                 .decrypt        = sun4i_ss_cbc_des3_decrypt,
 190                 }
 191         }
 192 },
 193 {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
 194         .alg.crypto = {
 195                         .cra_name = "ecb(des3_ede)",
 196                         .cra_driver_name = "ecb-des3-sun4i-ss",
 197                         .cra_priority = 300,
 198                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
 199                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
 200                         .cra_ctxsize = sizeof(struct sun4i_req_ctx),
 201                         .cra_module = THIS_MODULE,
 202                         .cra_alignmask = 3,
 203                         .cra_type = &crypto_ablkcipher_type,
 204                         .cra_init = sun4i_ss_cipher_init,
 205                         .cra_u.ablkcipher = {
 206                                 .min_keysize    = DES3_EDE_KEY_SIZE,
 207                                 .max_keysize    = DES3_EDE_KEY_SIZE,
 208                                 .ivsize         = DES3_EDE_BLOCK_SIZE,
 209                                 .setkey         = sun4i_ss_des3_setkey,
 210                                 .encrypt        = sun4i_ss_ecb_des3_encrypt,
 211                                 .decrypt        = sun4i_ss_ecb_des3_decrypt,
 212                 }
 213         }
 214 },
 215 };
 216
 217 static int sun4i_ss_probe(struct platform_device *pdev)
 218 {
 219         struct resource *res;
 220         u32 v;
 221         int err, i;
 222         unsigned long cr;
 223         const unsigned long cr_ahb = 24 * 1000 * 1000;
 224         const unsigned long cr_mod = 150 * 1000 * 1000;
 225         struct sun4i_ss_ctx *ss;
 226
 227         if (!pdev->dev.of_node)
 228                 return -ENODEV;
 229
 230         ss = devm_kzalloc(&pdev->dev, sizeof(*ss), GFP_KERNEL);
 231         if (!ss)
 232                 return -ENOMEM;
 233
 234         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 235         ss->base = devm_ioremap_resource(&pdev->dev, res);
 236         if (IS_ERR(ss->base)) {
 237                 dev_err(&pdev->dev, "Cannot request MMIO\n");
 238                 return PTR_ERR(ss->base);
 239         }
 240
 241         ss->ssclk = devm_clk_get(&pdev->dev, "mod");
 242         if (IS_ERR(ss->ssclk)) {
 243                 err = PTR_ERR(ss->ssclk);
 244                 dev_err(&pdev->dev, "Cannot get SS clock err=%d\n", err);
 245                 return err;
 246         }
 247         dev_dbg(&pdev->dev, "clock ss acquired\n");
 248
 249         ss->busclk = devm_clk_get(&pdev->dev, "ahb");
 250         if (IS_ERR(ss->busclk)) {
 251                 err = PTR_ERR(ss->busclk);
 252                 dev_err(&pdev->dev, "Cannot get AHB SS clock err=%d\n", err);
 253                 return err;
 254         }
 255         dev_dbg(&pdev->dev, "clock ahb_ss acquired\n");
 256
 257         ss->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
 258         if (IS_ERR(ss->reset)) {
 259                 if (PTR_ERR(ss->reset) == -EPROBE_DEFER)
 260                         return PTR_ERR(ss->reset);
 261                 dev_info(&pdev->dev, "no reset control found\n");
 262                 ss->reset = NULL;
 263         }
 264
 265         /* Enable both clocks */
 266         err = clk_prepare_enable(ss->busclk);
 267         if (err != 0) {
 268                 dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
 269                 return err;
 270         }
 271         err = clk_prepare_enable(ss->ssclk);
 272         if (err != 0) {
 273                 dev_err(&pdev->dev, "Cannot prepare_enable ssclk\n");
 274                 goto error_ssclk;
 275         }
 276
 277         /*
 278          * Check that clock have the correct rates given in the datasheet
 279          * Try to set the clock to the maximum allowed
 280          */
 281         err = clk_set_rate(ss->ssclk, cr_mod);
 282         if (err != 0) {
 283                 dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n");
 284                 goto error_clk;
 285         }
 286
 287         /* Deassert reset if we have a reset control */
 288         if (ss->reset) {
 289                 err = reset_control_deassert(ss->reset);
 290                 if (err) {
 291                         dev_err(&pdev->dev, "Cannot deassert reset control\n");
 292                         goto error_clk;
 293                 }
 294         }
 295
 296         /*
 297          * The only impact on clocks below requirement are bad performance,
 298          * so do not print "errors"
 299          * warn on Overclocked clocks
 300          */
 301         cr = clk_get_rate(ss->busclk);
 302         if (cr >= cr_ahb)
 303                 dev_dbg(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
 304                         cr, cr / 1000000, cr_ahb);
 305         else
 306                 dev_warn(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
 307                          cr, cr / 1000000, cr_ahb);
 308
 309         cr = clk_get_rate(ss->ssclk);
 310         if (cr <= cr_mod)
 311                 if (cr < cr_mod)
 312                         dev_warn(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
 313                                  cr, cr / 1000000, cr_mod);
 314                 else
 315                         dev_dbg(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
 316                                 cr, cr / 1000000, cr_mod);
 317         else
 318                 dev_warn(&pdev->dev, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n",
 319                          cr, cr / 1000000, cr_mod);
 320
 321         /*
 322          * Datasheet named it "Die Bonding ID"
 323          * I expect to be a sort of Security System Revision number.
 324          * Since the A80 seems to have an other version of SS
 325          * this info could be useful
 326          */
 327         writel(SS_ENABLED, ss->base + SS_CTL);
 328         v = readl(ss->base + SS_CTL);
 329         v >>= 16;
 330         v &= 0x07;
 331         dev_info(&pdev->dev, "Die ID %d\n", v);
 332         writel(0, ss->base + SS_CTL);
 333
 334         ss->dev = &pdev->dev;
 335
 336         spin_lock_init(&ss->slock);
 337
 338         for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
 339                 ss_algs[i].ss = ss;
 340                 switch (ss_algs[i].type) {
 341                 case CRYPTO_ALG_TYPE_ABLKCIPHER:
 342                         err = crypto_register_alg(&ss_algs[i].alg.crypto);
 343                         if (err != 0) {
 344                                 dev_err(ss->dev, "Fail to register %s\n",
 345                                         ss_algs[i].alg.crypto.cra_name);
 346                                 goto error_alg;
 347                         }
 348                         break;
 349                 case CRYPTO_ALG_TYPE_AHASH:
 350                         err = crypto_register_ahash(&ss_algs[i].alg.hash);
 351                         if (err != 0) {
 352                                 dev_err(ss->dev, "Fail to register %s\n",
 353                                         ss_algs[i].alg.hash.halg.base.cra_name);
 354                                 goto error_alg;
 355                         }
 356                         break;
 357                 }
 358         }
 359         platform_set_drvdata(pdev, ss);
 360         return 0;
 361 error_alg:
 362         i--;
 363         for (; i >= 0; i--) {
 364                 switch (ss_algs[i].type) {
 365                 case CRYPTO_ALG_TYPE_ABLKCIPHER:
 366                         crypto_unregister_alg(&ss_algs[i].alg.crypto);
 367                         break;
 368                 case CRYPTO_ALG_TYPE_AHASH:
 369                         crypto_unregister_ahash(&ss_algs[i].alg.hash);
 370                         break;
 371                 }
 372         }
 373         if (ss->reset)
 374                 reset_control_assert(ss->reset);
 375 error_clk:
 376         clk_disable_unprepare(ss->ssclk);
 377 error_ssclk:
 378         clk_disable_unprepare(ss->busclk);
 379         return err;
 380 }
 381
 382 static int sun4i_ss_remove(struct platform_device *pdev)
 383 {
 384         int i;
 385         struct sun4i_ss_ctx *ss = platform_get_drvdata(pdev);
 386
 387         for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
 388                 switch (ss_algs[i].type) {
 389                 case CRYPTO_ALG_TYPE_ABLKCIPHER:
 390                         crypto_unregister_alg(&ss_algs[i].alg.crypto);
 391                         break;
 392                 case CRYPTO_ALG_TYPE_AHASH:
 393                         crypto_unregister_ahash(&ss_algs[i].alg.hash);
 394                         break;
 395                 }
 396         }
 397
 398         writel(0, ss->base + SS_CTL);
 399         if (ss->reset)
 400                 reset_control_assert(ss->reset);
 401         clk_disable_unprepare(ss->busclk);
 402         clk_disable_unprepare(ss->ssclk);
 403         return 0;
 404 }
 405
 406 static const struct of_device_id a20ss_crypto_of_match_table[] = {
 407         { .compatible = "allwinner,sun4i-a10-crypto" },
 408         {}
 409 };
 410 MODULE_DEVICE_TABLE(of, a20ss_crypto_of_match_table);
 411
 412 static struct platform_driver sun4i_ss_driver = {
 413         .probe          = sun4i_ss_probe,
 414         .remove         = sun4i_ss_remove,
 415         .driver         = {
 416                 .name           = "sun4i-ss",
 417                 .of_match_table = a20ss_crypto_of_match_table,
 418         },
 419 };
 420
 421 module_platform_driver(sun4i_ss_driver);
 422
 423 MODULE_DESCRIPTION("Allwinner Security System cryptographic accelerator");
 424 MODULE_LICENSE("GPL");
 425 MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie@gmail.com>");