2 * Copyright Altera Corporation (C) 2014-2015
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/fpga_manager.h>
10 #include <asm/arch/sdram.h>
11 #include <asm/arch/system_manager.h>
15 * FIXME: This path is temporary until the SDRAM driver gets
16 * a proper thorough cleanup.
18 #include "../../../board/altera/socfpga/qts/sdram_config.h"
20 DECLARE_GLOBAL_DATA_PTR;
22 struct sdram_prot_rule {
23 u64 sdram_start; /* SDRAM start address */
24 u64 sdram_end; /* SDRAM end address */
25 u32 rule; /* SDRAM protection rule number: 0-19 */
26 int valid; /* Rule valid or not? 1 - valid, 0 not*/
35 static struct socfpga_system_manager *sysmgr_regs =
36 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
37 static struct socfpga_sdr_ctrl *sdr_ctrl =
38 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
41 * get_errata_rows() - Up the number of DRAM rows to cover entire address space
43 * SDRAM Failure happens when accessing non-existent memory. Artificially
44 * increase the number of rows so that the memory controller thinks it has
45 * 4GB of RAM. This function returns such amount of rows.
47 static int get_errata_rows(void)
49 /* Define constant for 4G memory - used for SDRAM errata workaround */
50 #define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
51 const unsigned long long memsize = MEMSIZE_4G;
52 const unsigned int cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
53 const unsigned int rows = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
54 const unsigned int banks = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS;
55 const unsigned int cols = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS;
56 const unsigned int width = 8;
58 unsigned long long newrows;
59 int bits, inewrowslog2;
61 debug("workaround rows - memsize %lld\n", memsize);
62 debug("workaround rows - cs %d\n", cs);
63 debug("workaround rows - width %d\n", width);
64 debug("workaround rows - rows %d\n", rows);
65 debug("workaround rows - banks %d\n", banks);
66 debug("workaround rows - cols %d\n", cols);
68 newrows = lldiv(memsize, cs * (width / 8));
69 debug("rows workaround - term1 %lld\n", newrows);
71 newrows = lldiv(newrows, (1 << banks) * (1 << cols));
72 debug("rows workaround - term2 %lld\n", newrows);
75 * Compute the hamming weight - same as number of bits set.
76 * Need to see if result is ordinal power of 2 before
77 * attempting log2 of result.
79 bits = generic_hweight32(newrows);
81 debug("rows workaround - bits %d\n", bits);
84 printf("SDRAM workaround failed, bits set %d\n", bits);
88 if (newrows > UINT_MAX) {
89 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
93 inewrowslog2 = __ilog2(newrows);
95 debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
97 if (inewrowslog2 == -1) {
98 printf("SDRAM workaround failed, newrows %lld\n", newrows);
105 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
106 static void sdram_set_rule(struct sdram_prot_rule *prule)
108 uint32_t lo_addr_bits;
109 uint32_t hi_addr_bits;
110 int ruleno = prule->rule;
112 /* Select the rule */
113 writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
115 /* Obtain the address bits */
116 lo_addr_bits = (uint32_t)(((prule->sdram_start) >> 20ULL) & 0xFFF);
117 hi_addr_bits = (uint32_t)((((prule->sdram_end-1) >> 20ULL)) & 0xFFF);
119 debug("sdram set rule start %x, %lld\n", lo_addr_bits,
121 debug("sdram set rule end %x, %lld\n", hi_addr_bits,
124 /* Set rule addresses */
125 writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
127 /* Set rule protection ids */
128 writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
129 &sdr_ctrl->prot_rule_id);
131 /* Set the rule data */
132 writel(prule->security | (prule->valid << 2) |
133 (prule->portmask << 3) | (prule->result << 13),
134 &sdr_ctrl->prot_rule_data);
137 writel(ruleno | (1L << 5), &sdr_ctrl->prot_rule_rdwr);
139 /* Set rule number to 0 by default */
140 writel(0, &sdr_ctrl->prot_rule_rdwr);
143 static void sdram_get_rule(struct sdram_prot_rule *prule)
148 int ruleno = prule->rule;
151 writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
152 writel(ruleno | (1L << 6), &sdr_ctrl->prot_rule_rdwr);
154 /* Get the addresses */
155 addr = readl(&sdr_ctrl->prot_rule_addr);
156 prule->sdram_start = (addr & 0xFFF) << 20;
157 prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
159 /* Get the configured protection IDs */
160 id = readl(&sdr_ctrl->prot_rule_id);
161 prule->lo_prot_id = id & 0xFFF;
162 prule->hi_prot_id = (id >> 12) & 0xFFF;
164 /* Get protection data */
165 data = readl(&sdr_ctrl->prot_rule_data);
167 prule->security = data & 0x3;
168 prule->valid = (data >> 2) & 0x1;
169 prule->portmask = (data >> 3) & 0x3FF;
170 prule->result = (data >> 13) & 0x1;
173 static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end)
175 struct sdram_prot_rule rule;
178 /* Start with accepting all SDRAM transaction */
179 writel(0x0, &sdr_ctrl->protport_default);
181 /* Clear all protection rules for warm boot case */
182 memset(&rule, 0, sizeof(struct sdram_prot_rule));
184 for (rules = 0; rules < 20; rules++) {
186 sdram_set_rule(&rule);
189 /* new rule: accept SDRAM */
190 rule.sdram_start = sdram_start;
191 rule.sdram_end = sdram_end;
192 rule.lo_prot_id = 0x0;
193 rule.hi_prot_id = 0xFFF;
194 rule.portmask = 0x3FF;
201 sdram_set_rule(&rule);
203 /* default rule: reject everything */
204 writel(0x3ff, &sdr_ctrl->protport_default);
207 static void sdram_dump_protection_config(void)
209 struct sdram_prot_rule rule;
212 debug("SDRAM Prot rule, default %x\n",
213 readl(&sdr_ctrl->protport_default));
215 for (rules = 0; rules < 20; rules++) {
216 sdram_get_rule(&rule);
217 debug("Rule %d, rules ...\n", rules);
218 debug(" sdram start %llx\n", rule.sdram_start);
219 debug(" sdram end %llx\n", rule.sdram_end);
220 debug(" low prot id %d, hi prot id %d\n",
223 debug(" portmask %x\n", rule.portmask);
224 debug(" security %d\n", rule.security);
225 debug(" result %d\n", rule.result);
226 debug(" valid %d\n", rule.valid);
230 /* Function to write to register and verify the write */
231 static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value)
233 #ifndef SDRAM_MMR_SKIP_VERIFY
236 debug(" Write - Address ");
237 debug("0x%08x Data 0x%08x\n", (u32)addr, reg_value);
238 /* Write to register */
239 writel(reg_value, addr);
240 #ifndef SDRAM_MMR_SKIP_VERIFY
241 debug(" Read and verify...");
242 /* Read back the wrote value */
243 reg_value1 = readl(addr);
244 /* Indicate failure if value not matched */
245 if (reg_value1 != reg_value) {
246 debug("FAIL - Address 0x%08x Expected 0x%08x Data 0x%08x\n",
247 (u32)addr, reg_value, reg_value1);
251 #endif /* SDRAM_MMR_SKIP_VERIFY */
255 static void set_sdr_ctrlcfg(void)
259 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
260 SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
261 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
262 SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
263 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
264 SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
265 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
266 SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
267 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
268 SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
269 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
270 SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
271 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
272 SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
273 (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
274 SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB);
276 debug("\nConfiguring CTRLCFG\n");
279 * SDRAM Failure When Accessing Non-Existent Memory
280 * Set the addrorder field of the SDRAM control register
281 * based on the CSBITs setting.
283 switch (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) {
285 addrorder = 0; /* chip, row, bank, column */
286 if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 0)
287 debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
290 addrorder = 2; /* row, chip, bank, column */
291 if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 2)
292 debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
295 addrorder = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER;
299 ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
301 writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
304 static void set_sdr_dram_timing1(void)
306 debug("Configuring DRAMTIMING1\n");
307 clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK,
308 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
309 SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB);
311 clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TAL_MASK,
312 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
313 SDR_CTRLGRP_DRAMTIMING1_TAL_LSB);
315 clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCL_MASK,
316 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
317 SDR_CTRLGRP_DRAMTIMING1_TCL_LSB);
319 clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK,
320 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
321 SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB);
323 clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK,
324 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
325 SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB);
327 clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK,
328 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
329 SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB);
332 static void set_sdr_dram_timing2(void)
334 debug("Configuring DRAMTIMING2\n");
335 clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK,
336 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
337 SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB);
339 clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK,
340 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
341 SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB);
343 clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRP_MASK,
344 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
345 SDR_CTRLGRP_DRAMTIMING2_TRP_LSB);
347 clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWR_MASK,
348 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
349 SDR_CTRLGRP_DRAMTIMING2_TWR_LSB);
351 clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK,
352 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
353 SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB);
356 static void set_sdr_dram_timing3(void)
358 debug("Configuring DRAMTIMING3\n");
359 clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK,
360 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
361 SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB);
363 clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK,
364 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
365 SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB);
367 clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRC_MASK,
368 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
369 SDR_CTRLGRP_DRAMTIMING3_TRC_LSB);
371 clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK,
372 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
373 SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB);
375 clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK,
376 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
377 SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB);
380 static void set_sdr_dram_timing4(void)
382 debug("Configuring DRAMTIMING4\n");
383 clrsetbits_le32(&sdr_ctrl->dram_timing4,
384 SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK,
385 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
386 SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB);
388 clrsetbits_le32(&sdr_ctrl->dram_timing4,
389 SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK,
390 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
391 SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB);
394 static void set_sdr_dram_lowpwr_timing(void)
396 debug("Configuring LOWPWRTIMING\n");
397 clrsetbits_le32(&sdr_ctrl->lowpwr_timing,
398 SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK,
399 CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
400 SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB);
402 clrsetbits_le32(&sdr_ctrl->lowpwr_timing,
403 SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK,
404 CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
405 SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB);
408 static void set_sdr_addr_rw(void)
412 debug("Configuring DRAMADDRW\n");
413 clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK,
414 CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
415 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB);
417 * SDRAM Failure When Accessing Non-Existent Memory
418 * Update Preloader to artificially increase the number of rows so
419 * that the memory thinks it has 4GB of RAM.
421 rows = get_errata_rows();
423 clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK,
424 rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
426 clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK,
427 CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
428 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB);
429 /* SDRAM Failure When Accessing Non-Existent Memory
430 * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
431 * log2(number of chip select bits). Since there's only
432 * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
433 * which is the same as "chip selects" - 1.
435 clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK,
436 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
437 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB);
440 static void set_sdr_static_cfg(void)
442 debug("Configuring STATICCFG\n");
443 clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_MEMBL_MASK,
444 CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
445 SDR_CTRLGRP_STATICCFG_MEMBL_LSB);
447 clrsetbits_le32(&sdr_ctrl->static_cfg,
448 SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK,
449 CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
450 SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB);
453 static void set_sdr_fifo_cfg(void)
455 debug("Configuring FIFOCFG\n");
456 clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK,
457 CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
458 SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB);
460 clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK,
461 CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
462 SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB);
465 static void set_sdr_mp_weight(void)
467 debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
468 clrsetbits_le32(&sdr_ctrl->mp_weight0,
469 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK,
470 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
471 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB);
473 clrsetbits_le32(&sdr_ctrl->mp_weight1,
474 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK,
475 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
476 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB);
478 clrsetbits_le32(&sdr_ctrl->mp_weight1,
479 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK,
480 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
481 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB);
483 clrsetbits_le32(&sdr_ctrl->mp_weight2,
484 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK,
485 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
486 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB);
488 clrsetbits_le32(&sdr_ctrl->mp_weight3,
489 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK,
490 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
491 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB);
494 static void set_sdr_mp_pacing(void)
496 debug("Configuring MPPACING_MPPACING_0\n");
497 clrsetbits_le32(&sdr_ctrl->mp_pacing0,
498 SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK,
499 CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
500 SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB);
502 clrsetbits_le32(&sdr_ctrl->mp_pacing1,
503 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK,
504 CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
505 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB);
507 clrsetbits_le32(&sdr_ctrl->mp_pacing1,
508 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK,
509 CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
510 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB);
512 clrsetbits_le32(&sdr_ctrl->mp_pacing2,
513 SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK,
514 CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
515 SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB);
517 clrsetbits_le32(&sdr_ctrl->mp_pacing3,
518 SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK,
519 CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
520 SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB);
523 static void set_sdr_mp_threshold(void)
525 debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
526 clrsetbits_le32(&sdr_ctrl->mp_threshold0,
527 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK,
528 CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
529 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB);
531 clrsetbits_le32(&sdr_ctrl->mp_threshold1,
532 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK,
533 CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
534 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB);
536 clrsetbits_le32(&sdr_ctrl->mp_threshold2,
537 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK,
538 CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
539 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB);
543 /* Function to initialize SDRAM MMR */
544 unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
546 unsigned long reg_value;
547 unsigned long status = 0;
549 #if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) && \
550 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) && \
551 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS) && \
552 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS) && \
553 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS)
555 writel(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS,
556 &sysmgr_regs->iswgrp_handoff[4]);
559 set_sdr_dram_timing1();
560 set_sdr_dram_timing2();
561 set_sdr_dram_timing3();
562 set_sdr_dram_timing4();
563 set_sdr_dram_lowpwr_timing();
566 debug("Configuring DRAMIFWIDTH\n");
567 clrsetbits_le32(&sdr_ctrl->dram_if_width,
568 SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK,
569 CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
570 SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB);
572 debug("Configuring DRAMDEVWIDTH\n");
573 clrsetbits_le32(&sdr_ctrl->dram_dev_width,
574 SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK,
575 CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
576 SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB);
578 debug("Configuring LOWPWREQ\n");
579 clrsetbits_le32(&sdr_ctrl->lowpwr_eq,
580 SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK,
581 CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
582 SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB);
584 debug("Configuring DRAMINTR\n");
585 clrsetbits_le32(&sdr_ctrl->dram_intr, SDR_CTRLGRP_DRAMINTR_INTREN_MASK,
586 CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
587 SDR_CTRLGRP_DRAMINTR_INTREN_LSB);
589 set_sdr_static_cfg();
591 debug("Configuring CTRLWIDTH\n");
592 clrsetbits_le32(&sdr_ctrl->ctrl_width,
593 SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK,
594 CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
595 SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB);
597 debug("Configuring PORTCFG\n");
598 clrsetbits_le32(&sdr_ctrl->port_cfg, SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK,
599 CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
600 SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB);
604 debug("Configuring MPPRIORITY\n");
605 clrsetbits_le32(&sdr_ctrl->mp_priority,
606 SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK,
607 CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
608 SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB);
612 set_sdr_mp_threshold();
614 debug("Configuring PHYCTRL_PHYCTRL_0\n");
615 setbits_le32(&sdr_ctrl->phy_ctrl0,
616 CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0);
618 debug("Configuring CPORTWIDTH\n");
619 clrsetbits_le32(&sdr_ctrl->cport_width,
620 SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK,
621 CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
622 SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB);
623 debug(" Write - Address ");
624 debug("0x%08x Data 0x%08x\n",
625 (unsigned)(&sdr_ctrl->cport_width),
626 (unsigned)reg_value);
627 reg_value = readl(&sdr_ctrl->cport_width);
628 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
630 debug("Configuring CPORTWMAP\n");
631 clrsetbits_le32(&sdr_ctrl->cport_wmap,
632 SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK,
633 CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
634 SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB);
635 debug(" Write - Address ");
636 debug("0x%08x Data 0x%08x\n",
637 (unsigned)(&sdr_ctrl->cport_wmap),
638 (unsigned)reg_value);
639 reg_value = readl(&sdr_ctrl->cport_wmap);
640 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
642 debug("Configuring CPORTRMAP\n");
643 clrsetbits_le32(&sdr_ctrl->cport_rmap,
644 SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK,
645 CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
646 SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB);
647 debug(" Write - Address ");
648 debug("0x%08x Data 0x%08x\n",
649 (unsigned)(&sdr_ctrl->cport_rmap),
650 (unsigned)reg_value);
651 reg_value = readl(&sdr_ctrl->cport_rmap);
652 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
654 debug("Configuring RFIFOCMAP\n");
655 clrsetbits_le32(&sdr_ctrl->rfifo_cmap,
656 SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK,
657 CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
658 SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB);
659 debug(" Write - Address ");
660 debug("0x%08x Data 0x%08x\n",
661 (unsigned)(&sdr_ctrl->rfifo_cmap),
662 (unsigned)reg_value);
663 reg_value = readl(&sdr_ctrl->rfifo_cmap);
664 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
666 debug("Configuring WFIFOCMAP\n");
667 reg_value = readl(&sdr_ctrl->wfifo_cmap);
668 clrsetbits_le32(&sdr_ctrl->wfifo_cmap,
669 SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK,
670 CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
671 SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB);
672 debug(" Write - Address ");
673 debug("0x%08x Data 0x%08x\n",
674 (unsigned)(&sdr_ctrl->wfifo_cmap),
675 (unsigned)reg_value);
676 reg_value = readl(&sdr_ctrl->wfifo_cmap);
677 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
679 debug("Configuring CPORTRDWR\n");
680 clrsetbits_le32(&sdr_ctrl->cport_rdwr,
681 SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK,
682 CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
683 SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB);
684 debug(" Write - Address ");
685 debug("0x%08x Data 0x%08x\n",
686 (unsigned)(&sdr_ctrl->cport_rdwr),
687 (unsigned)reg_value);
688 reg_value = readl(&sdr_ctrl->cport_rdwr);
689 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
691 debug("Configuring DRAMODT\n");
692 clrsetbits_le32(&sdr_ctrl->dram_odt,
693 SDR_CTRLGRP_DRAMODT_READ_MASK,
694 CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
695 SDR_CTRLGRP_DRAMODT_READ_LSB);
697 clrsetbits_le32(&sdr_ctrl->dram_odt,
698 SDR_CTRLGRP_DRAMODT_WRITE_MASK,
699 CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
700 SDR_CTRLGRP_DRAMODT_WRITE_LSB);
702 /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
703 writel(CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
704 &sysmgr_regs->iswgrp_handoff[3]);
706 /* only enable if the FPGA is programmed */
707 if (fpgamgr_test_fpga_ready()) {
708 if (sdram_write_verify(&sdr_ctrl->fpgaport_rst,
709 CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST) == 1) {
715 /* Restore the SDR PHY Register if valid */
716 if (sdr_phy_reg != 0xffffffff)
717 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
719 /***** Final step - apply configuration changes *****/
720 debug("Configuring STATICCFG_\n");
721 clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
722 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
723 debug(" Write - Address ");
724 debug("0x%08x Data 0x%08x\n",
725 (unsigned)(&sdr_ctrl->static_cfg),
726 (unsigned)reg_value);
727 reg_value = readl(&sdr_ctrl->static_cfg);
728 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
730 sdram_set_protection_config(0, sdram_calculate_size());
732 sdram_dump_protection_config();
738 * To calculate SDRAM device size based on SDRAM controller parameters.
739 * Size is specified in bytes.
742 * This function is compiled and linked into the preloader and
743 * Uboot (there may be others). So if this function changes, the Preloader
744 * and UBoot must be updated simultaneously.
746 unsigned long sdram_calculate_size(void)
749 unsigned long row, bank, col, cs, width;
751 temp = readl(&sdr_ctrl->dram_addrw);
752 col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
753 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
755 /* SDRAM Failure When Accessing Non-Existent Memory
756 * Use ROWBITS from Quartus/QSys to calculate SDRAM size
757 * since the FB specifies we modify ROWBITs to work around SDRAM
760 * If the stored handoff value for rows is 0, it probably means
761 * the preloader is older than UBoot. Use the
762 * #define from the SOCEDS Tools per Crucible review
763 * uboot-socfpga-204. Note that this is not a supported
764 * configuration and is not tested. The customer
765 * should be using preloader and uboot built from the
768 row = readl(&sysmgr_regs->iswgrp_handoff[4]);
770 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
771 /* If the stored handoff value for rows is greater than
772 * the field width in the sdr.dramaddrw register then
773 * something is very wrong. Revert to using the the #define
774 * value handed off by the SOCEDS tool chain instead of
775 * using a broken value.
778 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
780 bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
781 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
783 /* SDRAM Failure When Accessing Non-Existent Memory
784 * Use CSBITs from Quartus/QSys to calculate SDRAM size
785 * since the FB specifies we modify CSBITs to work around SDRAM
788 cs = (temp & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
789 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB;
792 cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
794 width = readl(&sdr_ctrl->dram_if_width);
795 /* ECC would not be calculated as its not addressible */
796 if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
798 if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
801 /* calculate the SDRAM size base on this info */
802 temp = 1 << (row + bank + col);
803 temp = temp * cs * (width / 8);
805 debug("sdram_calculate_memory returns %ld\n", temp);