2 * Core driver for the Synopsys DesignWare DMA Controller
4 * Copyright (C) 2007-2008 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
6 * Copyright (C) 2013 Intel Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/bitops.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmapool.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/pm_runtime.h>
27 #include "../dmaengine.h"
31 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
32 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
33 * of which use ARM any more). See the "Databook" from Synopsys for
34 * information beyond what licensees probably provide.
36 * The driver has been tested with the Atmel AT32AP7000, which does not
37 * support descriptor writeback.
40 #define DWC_DEFAULT_CTLLO(_chan) ({ \
41 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
42 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
43 bool _is_slave = is_slave_direction(_dwc->direction); \
44 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \
46 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \
49 (DWC_CTLL_DST_MSIZE(_dmsize) \
50 | DWC_CTLL_SRC_MSIZE(_smsize) \
53 | DWC_CTLL_DMS(_dwc->dst_master) \
54 | DWC_CTLL_SMS(_dwc->src_master)); \
58 * Number of descriptors to allocate for each channel. This should be
59 * made configurable somehow; preferably, the clients (at least the
60 * ones using slave transfers) should be able to give us a hint.
62 #define NR_DESCS_PER_CHANNEL 64
64 /* The set of bus widths supported by the DMA controller */
65 #define DW_DMA_BUSWIDTHS \
66 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
67 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
68 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
69 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
71 /*----------------------------------------------------------------------*/
73 static struct device *chan2dev(struct dma_chan *chan)
75 return &chan->dev->device;
78 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
80 return to_dw_desc(dwc->active_list.next);
83 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
85 struct dw_desc *desc, *_desc;
86 struct dw_desc *ret = NULL;
90 spin_lock_irqsave(&dwc->lock, flags);
91 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
93 if (async_tx_test_ack(&desc->txd)) {
94 list_del(&desc->desc_node);
98 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
100 spin_unlock_irqrestore(&dwc->lock, flags);
102 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
108 * Move a descriptor, including any children, to the free list.
109 * `desc' must not be on any lists.
111 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
116 struct dw_desc *child;
118 spin_lock_irqsave(&dwc->lock, flags);
119 list_for_each_entry(child, &desc->tx_list, desc_node)
120 dev_vdbg(chan2dev(&dwc->chan),
121 "moving child desc %p to freelist\n",
123 list_splice_init(&desc->tx_list, &dwc->free_list);
124 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
125 list_add(&desc->desc_node, &dwc->free_list);
126 spin_unlock_irqrestore(&dwc->lock, flags);
130 static void dwc_initialize(struct dw_dma_chan *dwc)
132 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
133 struct dw_dma_slave *dws = dwc->chan.private;
134 u32 cfghi = DWC_CFGH_FIFO_MODE;
135 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
137 if (dwc->initialized == true)
142 * We need controller-specific data to set up slave
145 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
147 cfghi |= DWC_CFGH_DST_PER(dws->dst_id);
148 cfghi |= DWC_CFGH_SRC_PER(dws->src_id);
150 cfghi |= DWC_CFGH_DST_PER(dwc->dst_id);
151 cfghi |= DWC_CFGH_SRC_PER(dwc->src_id);
154 channel_writel(dwc, CFG_LO, cfglo);
155 channel_writel(dwc, CFG_HI, cfghi);
157 /* Enable interrupts */
158 channel_set_bit(dw, MASK.XFER, dwc->mask);
159 channel_set_bit(dw, MASK.ERROR, dwc->mask);
161 dwc->initialized = true;
164 /*----------------------------------------------------------------------*/
166 static inline unsigned int dwc_fast_ffs(unsigned long long v)
169 * We can be a lot more clever here, but this should take care
170 * of the most common optimization.
181 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
183 dev_err(chan2dev(&dwc->chan),
184 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
185 channel_readl(dwc, SAR),
186 channel_readl(dwc, DAR),
187 channel_readl(dwc, LLP),
188 channel_readl(dwc, CTL_HI),
189 channel_readl(dwc, CTL_LO));
192 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
194 channel_clear_bit(dw, CH_EN, dwc->mask);
195 while (dma_readl(dw, CH_EN) & dwc->mask)
199 /*----------------------------------------------------------------------*/
201 /* Perform single block transfer */
202 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
203 struct dw_desc *desc)
205 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
209 * Software emulation of LLP mode relies on interrupts to continue
210 * multi block transfer.
212 ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
214 channel_writel(dwc, SAR, desc->lli.sar);
215 channel_writel(dwc, DAR, desc->lli.dar);
216 channel_writel(dwc, CTL_LO, ctllo);
217 channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
218 channel_set_bit(dw, CH_EN, dwc->mask);
220 /* Move pointer to next descriptor */
221 dwc->tx_node_active = dwc->tx_node_active->next;
224 /* Called with dwc->lock held and bh disabled */
225 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
227 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
228 unsigned long was_soft_llp;
230 /* ASSERT: channel is idle */
231 if (dma_readl(dw, CH_EN) & dwc->mask) {
232 dev_err(chan2dev(&dwc->chan),
233 "%s: BUG: Attempted to start non-idle channel\n",
235 dwc_dump_chan_regs(dwc);
237 /* The tasklet will hopefully advance the queue... */
242 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
245 dev_err(chan2dev(&dwc->chan),
246 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
252 dwc->residue = first->total_len;
253 dwc->tx_node_active = &first->tx_list;
255 /* Submit first block */
256 dwc_do_single_block(dwc, first);
263 channel_writel(dwc, LLP, first->txd.phys);
264 channel_writel(dwc, CTL_LO,
265 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
266 channel_writel(dwc, CTL_HI, 0);
267 channel_set_bit(dw, CH_EN, dwc->mask);
270 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
272 struct dw_desc *desc;
274 if (list_empty(&dwc->queue))
277 list_move(dwc->queue.next, &dwc->active_list);
278 desc = dwc_first_active(dwc);
279 dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
280 dwc_dostart(dwc, desc);
283 /*----------------------------------------------------------------------*/
286 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
287 bool callback_required)
289 dma_async_tx_callback callback = NULL;
291 struct dma_async_tx_descriptor *txd = &desc->txd;
292 struct dw_desc *child;
295 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
297 spin_lock_irqsave(&dwc->lock, flags);
298 dma_cookie_complete(txd);
299 if (callback_required) {
300 callback = txd->callback;
301 param = txd->callback_param;
305 list_for_each_entry(child, &desc->tx_list, desc_node)
306 async_tx_ack(&child->txd);
307 async_tx_ack(&desc->txd);
309 list_splice_init(&desc->tx_list, &dwc->free_list);
310 list_move(&desc->desc_node, &dwc->free_list);
312 dma_descriptor_unmap(txd);
313 spin_unlock_irqrestore(&dwc->lock, flags);
319 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
321 struct dw_desc *desc, *_desc;
325 spin_lock_irqsave(&dwc->lock, flags);
326 if (dma_readl(dw, CH_EN) & dwc->mask) {
327 dev_err(chan2dev(&dwc->chan),
328 "BUG: XFER bit set, but channel not idle!\n");
330 /* Try to continue after resetting the channel... */
331 dwc_chan_disable(dw, dwc);
335 * Submit queued descriptors ASAP, i.e. before we go through
336 * the completed ones.
338 list_splice_init(&dwc->active_list, &list);
339 dwc_dostart_first_queued(dwc);
341 spin_unlock_irqrestore(&dwc->lock, flags);
343 list_for_each_entry_safe(desc, _desc, &list, desc_node)
344 dwc_descriptor_complete(dwc, desc, true);
347 /* Returns how many bytes were already received from source */
348 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
350 u32 ctlhi = channel_readl(dwc, CTL_HI);
351 u32 ctllo = channel_readl(dwc, CTL_LO);
353 return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
356 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
359 struct dw_desc *desc, *_desc;
360 struct dw_desc *child;
364 spin_lock_irqsave(&dwc->lock, flags);
365 llp = channel_readl(dwc, LLP);
366 status_xfer = dma_readl(dw, RAW.XFER);
368 if (status_xfer & dwc->mask) {
369 /* Everything we've submitted is done */
370 dma_writel(dw, CLEAR.XFER, dwc->mask);
372 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
373 struct list_head *head, *active = dwc->tx_node_active;
376 * We are inside first active descriptor.
377 * Otherwise something is really wrong.
379 desc = dwc_first_active(dwc);
381 head = &desc->tx_list;
382 if (active != head) {
383 /* Update desc to reflect last sent one */
384 if (active != head->next)
385 desc = to_dw_desc(active->prev);
387 dwc->residue -= desc->len;
389 child = to_dw_desc(active);
391 /* Submit next block */
392 dwc_do_single_block(dwc, child);
394 spin_unlock_irqrestore(&dwc->lock, flags);
398 /* We are done here */
399 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
404 spin_unlock_irqrestore(&dwc->lock, flags);
406 dwc_complete_all(dw, dwc);
410 if (list_empty(&dwc->active_list)) {
412 spin_unlock_irqrestore(&dwc->lock, flags);
416 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
417 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
418 spin_unlock_irqrestore(&dwc->lock, flags);
422 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
424 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
425 /* Initial residue value */
426 dwc->residue = desc->total_len;
428 /* Check first descriptors addr */
429 if (desc->txd.phys == llp) {
430 spin_unlock_irqrestore(&dwc->lock, flags);
434 /* Check first descriptors llp */
435 if (desc->lli.llp == llp) {
436 /* This one is currently in progress */
437 dwc->residue -= dwc_get_sent(dwc);
438 spin_unlock_irqrestore(&dwc->lock, flags);
442 dwc->residue -= desc->len;
443 list_for_each_entry(child, &desc->tx_list, desc_node) {
444 if (child->lli.llp == llp) {
445 /* Currently in progress */
446 dwc->residue -= dwc_get_sent(dwc);
447 spin_unlock_irqrestore(&dwc->lock, flags);
450 dwc->residue -= child->len;
454 * No descriptors so far seem to be in progress, i.e.
455 * this one must be done.
457 spin_unlock_irqrestore(&dwc->lock, flags);
458 dwc_descriptor_complete(dwc, desc, true);
459 spin_lock_irqsave(&dwc->lock, flags);
462 dev_err(chan2dev(&dwc->chan),
463 "BUG: All descriptors done, but channel not idle!\n");
465 /* Try to continue after resetting the channel... */
466 dwc_chan_disable(dw, dwc);
468 dwc_dostart_first_queued(dwc);
469 spin_unlock_irqrestore(&dwc->lock, flags);
472 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
474 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
475 lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
478 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
480 struct dw_desc *bad_desc;
481 struct dw_desc *child;
484 dwc_scan_descriptors(dw, dwc);
486 spin_lock_irqsave(&dwc->lock, flags);
489 * The descriptor currently at the head of the active list is
490 * borked. Since we don't have any way to report errors, we'll
491 * just have to scream loudly and try to carry on.
493 bad_desc = dwc_first_active(dwc);
494 list_del_init(&bad_desc->desc_node);
495 list_move(dwc->queue.next, dwc->active_list.prev);
497 /* Clear the error flag and try to restart the controller */
498 dma_writel(dw, CLEAR.ERROR, dwc->mask);
499 if (!list_empty(&dwc->active_list))
500 dwc_dostart(dwc, dwc_first_active(dwc));
503 * WARN may seem harsh, but since this only happens
504 * when someone submits a bad physical address in a
505 * descriptor, we should consider ourselves lucky that the
506 * controller flagged an error instead of scribbling over
507 * random memory locations.
509 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
510 " cookie: %d\n", bad_desc->txd.cookie);
511 dwc_dump_lli(dwc, &bad_desc->lli);
512 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
513 dwc_dump_lli(dwc, &child->lli);
515 spin_unlock_irqrestore(&dwc->lock, flags);
517 /* Pretend the descriptor completed successfully */
518 dwc_descriptor_complete(dwc, bad_desc, true);
521 /* --------------------- Cyclic DMA API extensions -------------------- */
523 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
525 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
526 return channel_readl(dwc, SAR);
528 EXPORT_SYMBOL(dw_dma_get_src_addr);
530 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
532 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
533 return channel_readl(dwc, DAR);
535 EXPORT_SYMBOL(dw_dma_get_dst_addr);
537 /* Called with dwc->lock held and all DMAC interrupts disabled */
538 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
539 u32 status_err, u32 status_xfer)
544 void (*callback)(void *param);
545 void *callback_param;
547 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
548 channel_readl(dwc, LLP));
550 callback = dwc->cdesc->period_callback;
551 callback_param = dwc->cdesc->period_callback_param;
554 callback(callback_param);
558 * Error and transfer complete are highly unlikely, and will most
559 * likely be due to a configuration error by the user.
561 if (unlikely(status_err & dwc->mask) ||
562 unlikely(status_xfer & dwc->mask)) {
565 dev_err(chan2dev(&dwc->chan),
566 "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
567 status_xfer ? "xfer" : "error");
569 spin_lock_irqsave(&dwc->lock, flags);
571 dwc_dump_chan_regs(dwc);
573 dwc_chan_disable(dw, dwc);
575 /* Make sure DMA does not restart by loading a new list */
576 channel_writel(dwc, LLP, 0);
577 channel_writel(dwc, CTL_LO, 0);
578 channel_writel(dwc, CTL_HI, 0);
580 dma_writel(dw, CLEAR.ERROR, dwc->mask);
581 dma_writel(dw, CLEAR.XFER, dwc->mask);
583 for (i = 0; i < dwc->cdesc->periods; i++)
584 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
586 spin_unlock_irqrestore(&dwc->lock, flags);
590 /* ------------------------------------------------------------------------- */
592 static void dw_dma_tasklet(unsigned long data)
594 struct dw_dma *dw = (struct dw_dma *)data;
595 struct dw_dma_chan *dwc;
600 status_xfer = dma_readl(dw, RAW.XFER);
601 status_err = dma_readl(dw, RAW.ERROR);
603 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
605 for (i = 0; i < dw->dma.chancnt; i++) {
607 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
608 dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
609 else if (status_err & (1 << i))
610 dwc_handle_error(dw, dwc);
611 else if (status_xfer & (1 << i))
612 dwc_scan_descriptors(dw, dwc);
616 * Re-enable interrupts.
618 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
619 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
622 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
624 struct dw_dma *dw = dev_id;
627 /* Check if we have any interrupt from the DMAC which is not in use */
631 status = dma_readl(dw, STATUS_INT);
632 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
634 /* Check if we have any interrupt from the DMAC */
639 * Just disable the interrupts. We'll turn them back on in the
642 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
643 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
645 status = dma_readl(dw, STATUS_INT);
648 "BUG: Unexpected interrupts pending: 0x%x\n",
652 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
653 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
654 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
655 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
658 tasklet_schedule(&dw->tasklet);
663 /*----------------------------------------------------------------------*/
665 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
667 struct dw_desc *desc = txd_to_dw_desc(tx);
668 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
672 spin_lock_irqsave(&dwc->lock, flags);
673 cookie = dma_cookie_assign(tx);
676 * REVISIT: We should attempt to chain as many descriptors as
677 * possible, perhaps even appending to those already submitted
678 * for DMA. But this is hard to do in a race-free manner.
681 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie);
682 list_add_tail(&desc->desc_node, &dwc->queue);
684 spin_unlock_irqrestore(&dwc->lock, flags);
689 static struct dma_async_tx_descriptor *
690 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
691 size_t len, unsigned long flags)
693 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
694 struct dw_dma *dw = to_dw_dma(chan->device);
695 struct dw_desc *desc;
696 struct dw_desc *first;
697 struct dw_desc *prev;
700 unsigned int src_width;
701 unsigned int dst_width;
702 unsigned int data_width;
705 dev_vdbg(chan2dev(chan),
706 "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
707 &dest, &src, len, flags);
709 if (unlikely(!len)) {
710 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
714 dwc->direction = DMA_MEM_TO_MEM;
716 data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
717 dw->data_width[dwc->dst_master]);
719 src_width = dst_width = min_t(unsigned int, data_width,
720 dwc_fast_ffs(src | dest | len));
722 ctllo = DWC_DEFAULT_CTLLO(chan)
723 | DWC_CTLL_DST_WIDTH(dst_width)
724 | DWC_CTLL_SRC_WIDTH(src_width)
730 for (offset = 0; offset < len; offset += xfer_count << src_width) {
731 xfer_count = min_t(size_t, (len - offset) >> src_width,
734 desc = dwc_desc_get(dwc);
738 desc->lli.sar = src + offset;
739 desc->lli.dar = dest + offset;
740 desc->lli.ctllo = ctllo;
741 desc->lli.ctlhi = xfer_count;
742 desc->len = xfer_count << src_width;
747 prev->lli.llp = desc->txd.phys;
748 list_add_tail(&desc->desc_node,
754 if (flags & DMA_PREP_INTERRUPT)
755 /* Trigger interrupt after last block */
756 prev->lli.ctllo |= DWC_CTLL_INT_EN;
759 first->txd.flags = flags;
760 first->total_len = len;
765 dwc_desc_put(dwc, first);
769 static struct dma_async_tx_descriptor *
770 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
771 unsigned int sg_len, enum dma_transfer_direction direction,
772 unsigned long flags, void *context)
774 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
775 struct dw_dma *dw = to_dw_dma(chan->device);
776 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
777 struct dw_desc *prev;
778 struct dw_desc *first;
781 unsigned int reg_width;
782 unsigned int mem_width;
783 unsigned int data_width;
785 struct scatterlist *sg;
786 size_t total_len = 0;
788 dev_vdbg(chan2dev(chan), "%s\n", __func__);
790 if (unlikely(!is_slave_direction(direction) || !sg_len))
793 dwc->direction = direction;
799 reg_width = __ffs(sconfig->dst_addr_width);
800 reg = sconfig->dst_addr;
801 ctllo = (DWC_DEFAULT_CTLLO(chan)
802 | DWC_CTLL_DST_WIDTH(reg_width)
806 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
807 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
809 data_width = dw->data_width[dwc->src_master];
811 for_each_sg(sgl, sg, sg_len, i) {
812 struct dw_desc *desc;
815 mem = sg_dma_address(sg);
816 len = sg_dma_len(sg);
818 mem_width = min_t(unsigned int,
819 data_width, dwc_fast_ffs(mem | len));
821 slave_sg_todev_fill_desc:
822 desc = dwc_desc_get(dwc);
828 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
829 if ((len >> mem_width) > dwc->block_size) {
830 dlen = dwc->block_size << mem_width;
838 desc->lli.ctlhi = dlen >> mem_width;
844 prev->lli.llp = desc->txd.phys;
845 list_add_tail(&desc->desc_node,
852 goto slave_sg_todev_fill_desc;
856 reg_width = __ffs(sconfig->src_addr_width);
857 reg = sconfig->src_addr;
858 ctllo = (DWC_DEFAULT_CTLLO(chan)
859 | DWC_CTLL_SRC_WIDTH(reg_width)
863 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
864 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
866 data_width = dw->data_width[dwc->dst_master];
868 for_each_sg(sgl, sg, sg_len, i) {
869 struct dw_desc *desc;
872 mem = sg_dma_address(sg);
873 len = sg_dma_len(sg);
875 mem_width = min_t(unsigned int,
876 data_width, dwc_fast_ffs(mem | len));
878 slave_sg_fromdev_fill_desc:
879 desc = dwc_desc_get(dwc);
885 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
886 if ((len >> reg_width) > dwc->block_size) {
887 dlen = dwc->block_size << reg_width;
894 desc->lli.ctlhi = dlen >> reg_width;
900 prev->lli.llp = desc->txd.phys;
901 list_add_tail(&desc->desc_node,
908 goto slave_sg_fromdev_fill_desc;
915 if (flags & DMA_PREP_INTERRUPT)
916 /* Trigger interrupt after last block */
917 prev->lli.ctllo |= DWC_CTLL_INT_EN;
920 first->total_len = total_len;
925 dev_err(chan2dev(chan),
926 "not enough descriptors available. Direction %d\n", direction);
927 dwc_desc_put(dwc, first);
931 bool dw_dma_filter(struct dma_chan *chan, void *param)
933 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
934 struct dw_dma_slave *dws = param;
936 if (!dws || dws->dma_dev != chan->device->dev)
939 /* We have to copy data since dws can be temporary storage */
941 dwc->src_id = dws->src_id;
942 dwc->dst_id = dws->dst_id;
944 dwc->src_master = dws->src_master;
945 dwc->dst_master = dws->dst_master;
949 EXPORT_SYMBOL_GPL(dw_dma_filter);
952 * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
953 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
955 * NOTE: burst size 2 is not supported by controller.
957 * This can be done by finding least significant bit set: n & (n - 1)
959 static inline void convert_burst(u32 *maxburst)
962 *maxburst = fls(*maxburst) - 2;
967 static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
969 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
971 /* Check if chan will be configured for slave transfers */
972 if (!is_slave_direction(sconfig->direction))
975 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
976 dwc->direction = sconfig->direction;
978 convert_burst(&dwc->dma_sconfig.src_maxburst);
979 convert_burst(&dwc->dma_sconfig.dst_maxburst);
984 static int dwc_pause(struct dma_chan *chan)
986 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
988 unsigned int count = 20; /* timeout iterations */
991 spin_lock_irqsave(&dwc->lock, flags);
993 cfglo = channel_readl(dwc, CFG_LO);
994 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
995 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
1000 spin_unlock_irqrestore(&dwc->lock, flags);
1005 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
1007 u32 cfglo = channel_readl(dwc, CFG_LO);
1009 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1011 dwc->paused = false;
1014 static int dwc_resume(struct dma_chan *chan)
1016 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1017 unsigned long flags;
1022 spin_lock_irqsave(&dwc->lock, flags);
1024 dwc_chan_resume(dwc);
1026 spin_unlock_irqrestore(&dwc->lock, flags);
1031 static int dwc_terminate_all(struct dma_chan *chan)
1033 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1034 struct dw_dma *dw = to_dw_dma(chan->device);
1035 struct dw_desc *desc, *_desc;
1036 unsigned long flags;
1039 spin_lock_irqsave(&dwc->lock, flags);
1041 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1043 dwc_chan_disable(dw, dwc);
1045 dwc_chan_resume(dwc);
1047 /* active_list entries will end up before queued entries */
1048 list_splice_init(&dwc->queue, &list);
1049 list_splice_init(&dwc->active_list, &list);
1051 spin_unlock_irqrestore(&dwc->lock, flags);
1053 /* Flush all pending and queued descriptors */
1054 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1055 dwc_descriptor_complete(dwc, desc, false);
1060 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1062 unsigned long flags;
1065 spin_lock_irqsave(&dwc->lock, flags);
1067 residue = dwc->residue;
1068 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1069 residue -= dwc_get_sent(dwc);
1071 spin_unlock_irqrestore(&dwc->lock, flags);
1075 static enum dma_status
1076 dwc_tx_status(struct dma_chan *chan,
1077 dma_cookie_t cookie,
1078 struct dma_tx_state *txstate)
1080 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1081 enum dma_status ret;
1083 ret = dma_cookie_status(chan, cookie, txstate);
1084 if (ret == DMA_COMPLETE)
1087 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1089 ret = dma_cookie_status(chan, cookie, txstate);
1090 if (ret != DMA_COMPLETE)
1091 dma_set_residue(txstate, dwc_get_residue(dwc));
1093 if (dwc->paused && ret == DMA_IN_PROGRESS)
1099 static void dwc_issue_pending(struct dma_chan *chan)
1101 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1102 unsigned long flags;
1104 spin_lock_irqsave(&dwc->lock, flags);
1105 if (list_empty(&dwc->active_list))
1106 dwc_dostart_first_queued(dwc);
1107 spin_unlock_irqrestore(&dwc->lock, flags);
1110 /*----------------------------------------------------------------------*/
1112 static void dw_dma_off(struct dw_dma *dw)
1116 dma_writel(dw, CFG, 0);
1118 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1119 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1120 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1121 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1123 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1126 for (i = 0; i < dw->dma.chancnt; i++)
1127 dw->chan[i].initialized = false;
1130 static void dw_dma_on(struct dw_dma *dw)
1132 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1135 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1137 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1138 struct dw_dma *dw = to_dw_dma(chan->device);
1139 struct dw_desc *desc;
1141 unsigned long flags;
1143 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1145 /* ASSERT: channel is idle */
1146 if (dma_readl(dw, CH_EN) & dwc->mask) {
1147 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1151 dma_cookie_init(chan);
1154 * NOTE: some controllers may have additional features that we
1155 * need to initialize here, like "scatter-gather" (which
1156 * doesn't mean what you think it means), and status writeback.
1159 /* Enable controller here if needed */
1162 dw->in_use |= dwc->mask;
1164 spin_lock_irqsave(&dwc->lock, flags);
1165 i = dwc->descs_allocated;
1166 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1169 spin_unlock_irqrestore(&dwc->lock, flags);
1171 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1173 goto err_desc_alloc;
1175 memset(desc, 0, sizeof(struct dw_desc));
1177 INIT_LIST_HEAD(&desc->tx_list);
1178 dma_async_tx_descriptor_init(&desc->txd, chan);
1179 desc->txd.tx_submit = dwc_tx_submit;
1180 desc->txd.flags = DMA_CTRL_ACK;
1181 desc->txd.phys = phys;
1183 dwc_desc_put(dwc, desc);
1185 spin_lock_irqsave(&dwc->lock, flags);
1186 i = ++dwc->descs_allocated;
1189 spin_unlock_irqrestore(&dwc->lock, flags);
1191 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1196 dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1201 static void dwc_free_chan_resources(struct dma_chan *chan)
1203 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1204 struct dw_dma *dw = to_dw_dma(chan->device);
1205 struct dw_desc *desc, *_desc;
1206 unsigned long flags;
1209 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1210 dwc->descs_allocated);
1212 /* ASSERT: channel is idle */
1213 BUG_ON(!list_empty(&dwc->active_list));
1214 BUG_ON(!list_empty(&dwc->queue));
1215 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1217 spin_lock_irqsave(&dwc->lock, flags);
1218 list_splice_init(&dwc->free_list, &list);
1219 dwc->descs_allocated = 0;
1220 dwc->initialized = false;
1222 /* Disable interrupts */
1223 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1224 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1226 spin_unlock_irqrestore(&dwc->lock, flags);
1228 /* Disable controller in case it was a last user */
1229 dw->in_use &= ~dwc->mask;
1233 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1234 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1235 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1238 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1241 /* --------------------- Cyclic DMA API extensions -------------------- */
1244 * dw_dma_cyclic_start - start the cyclic DMA transfer
1245 * @chan: the DMA channel to start
1247 * Must be called with soft interrupts disabled. Returns zero on success or
1248 * -errno on failure.
1250 int dw_dma_cyclic_start(struct dma_chan *chan)
1252 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1253 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1254 unsigned long flags;
1256 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1257 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1261 spin_lock_irqsave(&dwc->lock, flags);
1263 /* Assert channel is idle */
1264 if (dma_readl(dw, CH_EN) & dwc->mask) {
1265 dev_err(chan2dev(&dwc->chan),
1266 "%s: BUG: Attempted to start non-idle channel\n",
1268 dwc_dump_chan_regs(dwc);
1269 spin_unlock_irqrestore(&dwc->lock, flags);
1273 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1274 dma_writel(dw, CLEAR.XFER, dwc->mask);
1276 /* Setup DMAC channel registers */
1277 channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1278 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1279 channel_writel(dwc, CTL_HI, 0);
1281 channel_set_bit(dw, CH_EN, dwc->mask);
1283 spin_unlock_irqrestore(&dwc->lock, flags);
1287 EXPORT_SYMBOL(dw_dma_cyclic_start);
1290 * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1291 * @chan: the DMA channel to stop
1293 * Must be called with soft interrupts disabled.
1295 void dw_dma_cyclic_stop(struct dma_chan *chan)
1297 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1298 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1299 unsigned long flags;
1301 spin_lock_irqsave(&dwc->lock, flags);
1303 dwc_chan_disable(dw, dwc);
1305 spin_unlock_irqrestore(&dwc->lock, flags);
1307 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1310 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1311 * @chan: the DMA channel to prepare
1312 * @buf_addr: physical DMA address where the buffer starts
1313 * @buf_len: total number of bytes for the entire buffer
1314 * @period_len: number of bytes for each period
1315 * @direction: transfer direction, to or from device
1317 * Must be called before trying to start the transfer. Returns a valid struct
1318 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1320 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1321 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1322 enum dma_transfer_direction direction)
1324 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1325 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
1326 struct dw_cyclic_desc *cdesc;
1327 struct dw_cyclic_desc *retval = NULL;
1328 struct dw_desc *desc;
1329 struct dw_desc *last = NULL;
1330 unsigned long was_cyclic;
1331 unsigned int reg_width;
1332 unsigned int periods;
1334 unsigned long flags;
1336 spin_lock_irqsave(&dwc->lock, flags);
1338 spin_unlock_irqrestore(&dwc->lock, flags);
1339 dev_dbg(chan2dev(&dwc->chan),
1340 "channel doesn't support LLP transfers\n");
1341 return ERR_PTR(-EINVAL);
1344 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1345 spin_unlock_irqrestore(&dwc->lock, flags);
1346 dev_dbg(chan2dev(&dwc->chan),
1347 "queue and/or active list are not empty\n");
1348 return ERR_PTR(-EBUSY);
1351 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1352 spin_unlock_irqrestore(&dwc->lock, flags);
1354 dev_dbg(chan2dev(&dwc->chan),
1355 "channel already prepared for cyclic DMA\n");
1356 return ERR_PTR(-EBUSY);
1359 retval = ERR_PTR(-EINVAL);
1361 if (unlikely(!is_slave_direction(direction)))
1364 dwc->direction = direction;
1366 if (direction == DMA_MEM_TO_DEV)
1367 reg_width = __ffs(sconfig->dst_addr_width);
1369 reg_width = __ffs(sconfig->src_addr_width);
1371 periods = buf_len / period_len;
1373 /* Check for too big/unaligned periods and unaligned DMA buffer. */
1374 if (period_len > (dwc->block_size << reg_width))
1376 if (unlikely(period_len & ((1 << reg_width) - 1)))
1378 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1381 retval = ERR_PTR(-ENOMEM);
1383 if (periods > NR_DESCS_PER_CHANNEL)
1386 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1390 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1394 for (i = 0; i < periods; i++) {
1395 desc = dwc_desc_get(dwc);
1397 goto out_err_desc_get;
1399 switch (direction) {
1400 case DMA_MEM_TO_DEV:
1401 desc->lli.dar = sconfig->dst_addr;
1402 desc->lli.sar = buf_addr + (period_len * i);
1403 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1404 | DWC_CTLL_DST_WIDTH(reg_width)
1405 | DWC_CTLL_SRC_WIDTH(reg_width)
1410 desc->lli.ctllo |= sconfig->device_fc ?
1411 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1412 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1415 case DMA_DEV_TO_MEM:
1416 desc->lli.dar = buf_addr + (period_len * i);
1417 desc->lli.sar = sconfig->src_addr;
1418 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1419 | DWC_CTLL_SRC_WIDTH(reg_width)
1420 | DWC_CTLL_DST_WIDTH(reg_width)
1425 desc->lli.ctllo |= sconfig->device_fc ?
1426 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1427 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1434 desc->lli.ctlhi = (period_len >> reg_width);
1435 cdesc->desc[i] = desc;
1438 last->lli.llp = desc->txd.phys;
1443 /* Let's make a cyclic list */
1444 last->lli.llp = cdesc->desc[0]->txd.phys;
1446 dev_dbg(chan2dev(&dwc->chan),
1447 "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1448 &buf_addr, buf_len, period_len, periods);
1450 cdesc->periods = periods;
1457 dwc_desc_put(dwc, cdesc->desc[i]);
1461 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1462 return (struct dw_cyclic_desc *)retval;
1464 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1467 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1468 * @chan: the DMA channel to free
1470 void dw_dma_cyclic_free(struct dma_chan *chan)
1472 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1473 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1474 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1476 unsigned long flags;
1478 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1483 spin_lock_irqsave(&dwc->lock, flags);
1485 dwc_chan_disable(dw, dwc);
1487 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1488 dma_writel(dw, CLEAR.XFER, dwc->mask);
1490 spin_unlock_irqrestore(&dwc->lock, flags);
1492 for (i = 0; i < cdesc->periods; i++)
1493 dwc_desc_put(dwc, cdesc->desc[i]);
1498 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1500 EXPORT_SYMBOL(dw_dma_cyclic_free);
1502 /*----------------------------------------------------------------------*/
1504 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1507 bool autocfg = false;
1508 unsigned int dw_params;
1509 unsigned int max_blk_size = 0;
1513 dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1517 dw->regs = chip->regs;
1520 pm_runtime_get_sync(chip->dev);
1523 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1524 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1526 autocfg = dw_params >> DW_PARAMS_EN & 1;
1532 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1538 /* Get hardware configuration parameters */
1539 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
1540 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1541 for (i = 0; i < pdata->nr_masters; i++) {
1542 pdata->data_width[i] =
1543 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1545 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1547 /* Fill platform data with the default values */
1548 pdata->is_private = true;
1549 pdata->is_memcpy = true;
1550 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1551 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1552 } else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1557 dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
1564 /* Get hardware configuration parameters */
1565 dw->nr_masters = pdata->nr_masters;
1566 for (i = 0; i < dw->nr_masters; i++)
1567 dw->data_width[i] = pdata->data_width[i];
1569 /* Calculate all channel mask before DMA setup */
1570 dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1572 /* Force dma off, just in case */
1575 /* Disable BLOCK interrupts as well */
1576 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1578 /* Create a pool of consistent memory blocks for hardware descriptors */
1579 dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1580 sizeof(struct dw_desc), 4, 0);
1581 if (!dw->desc_pool) {
1582 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1587 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1589 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1594 INIT_LIST_HEAD(&dw->dma.channels);
1595 for (i = 0; i < pdata->nr_channels; i++) {
1596 struct dw_dma_chan *dwc = &dw->chan[i];
1598 dwc->chan.device = &dw->dma;
1599 dma_cookie_init(&dwc->chan);
1600 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1601 list_add_tail(&dwc->chan.device_node,
1604 list_add(&dwc->chan.device_node, &dw->dma.channels);
1606 /* 7 is highest priority & 0 is lowest. */
1607 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1608 dwc->priority = pdata->nr_channels - i - 1;
1612 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1613 spin_lock_init(&dwc->lock);
1616 INIT_LIST_HEAD(&dwc->active_list);
1617 INIT_LIST_HEAD(&dwc->queue);
1618 INIT_LIST_HEAD(&dwc->free_list);
1620 channel_clear_bit(dw, CH_EN, dwc->mask);
1622 dwc->direction = DMA_TRANS_NONE;
1624 /* Hardware configuration */
1626 unsigned int dwc_params;
1627 unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1;
1628 void __iomem *addr = chip->regs + r * sizeof(u32);
1630 dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1632 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1636 * Decode maximum block size for given channel. The
1637 * stored 4 bit value represents blocks from 0x00 for 3
1638 * up to 0x0a for 4095.
1641 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1643 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1645 dwc->block_size = pdata->block_size;
1647 /* Check if channel supports multi block transfer */
1648 channel_writel(dwc, LLP, 0xfffffffc);
1650 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1651 channel_writel(dwc, LLP, 0);
1655 /* Clear all interrupts on all channels. */
1656 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1657 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1658 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1659 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1660 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1662 /* Set capabilities */
1663 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1664 if (pdata->is_private)
1665 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1666 if (pdata->is_memcpy)
1667 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1669 dw->dma.dev = chip->dev;
1670 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1671 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1673 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1674 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1676 dw->dma.device_config = dwc_config;
1677 dw->dma.device_pause = dwc_pause;
1678 dw->dma.device_resume = dwc_resume;
1679 dw->dma.device_terminate_all = dwc_terminate_all;
1681 dw->dma.device_tx_status = dwc_tx_status;
1682 dw->dma.device_issue_pending = dwc_issue_pending;
1684 /* DMA capabilities */
1685 dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
1686 dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
1687 dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
1688 BIT(DMA_MEM_TO_MEM);
1689 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1691 err = dma_async_device_register(&dw->dma);
1693 goto err_dma_register;
1695 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1696 pdata->nr_channels);
1698 pm_runtime_put_sync_suspend(chip->dev);
1703 free_irq(chip->irq, dw);
1705 pm_runtime_put_sync_suspend(chip->dev);
1708 EXPORT_SYMBOL_GPL(dw_dma_probe);
1710 int dw_dma_remove(struct dw_dma_chip *chip)
1712 struct dw_dma *dw = chip->dw;
1713 struct dw_dma_chan *dwc, *_dwc;
1715 pm_runtime_get_sync(chip->dev);
1718 dma_async_device_unregister(&dw->dma);
1720 free_irq(chip->irq, dw);
1721 tasklet_kill(&dw->tasklet);
1723 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1725 list_del(&dwc->chan.device_node);
1726 channel_clear_bit(dw, CH_EN, dwc->mask);
1729 pm_runtime_put_sync_suspend(chip->dev);
1732 EXPORT_SYMBOL_GPL(dw_dma_remove);
1734 int dw_dma_disable(struct dw_dma_chip *chip)
1736 struct dw_dma *dw = chip->dw;
1741 EXPORT_SYMBOL_GPL(dw_dma_disable);
1743 int dw_dma_enable(struct dw_dma_chip *chip)
1745 struct dw_dma *dw = chip->dw;
1750 EXPORT_SYMBOL_GPL(dw_dma_enable);
1752 MODULE_LICENSE("GPL v2");
1753 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1754 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1755 MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");