2 * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
5 * Copyright (C) 2007-2008 Atmel Corporation
6 * Copyright (C) 2010-2011 ST Microelectronics
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
25 #include "dw_dmac_regs.h"
26 #include "dmaengine.h"
29 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
30 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
31 * of which use ARM any more). See the "Databook" from Synopsys for
32 * information beyond what licensees probably provide.
34 * The driver has currently been tested only with the Atmel AT32AP7000,
35 * which does not support descriptor writeback.
38 #define DWC_DEFAULT_CTLLO(_chan) ({ \
39 struct dw_dma_slave *__slave = (_chan->private); \
40 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
41 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
42 int _dms = __slave ? __slave->dst_master : 0; \
43 int _sms = __slave ? __slave->src_master : 1; \
44 u8 _smsize = __slave ? _sconfig->src_maxburst : \
46 u8 _dmsize = __slave ? _sconfig->dst_maxburst : \
49 (DWC_CTLL_DST_MSIZE(_dmsize) \
50 | DWC_CTLL_SRC_MSIZE(_smsize) \
53 | DWC_CTLL_DMS(_dms) \
54 | DWC_CTLL_SMS(_sms)); \
58 * This is configuration-dependent and usually a funny size like 4095.
60 * Note that this is a transfer count, i.e. if we transfer 32-bit
61 * words, we can do 16380 bytes per descriptor.
63 * This parameter is also system-specific.
65 #define DWC_MAX_COUNT 4095U
68 * Number of descriptors to allocate for each channel. This should be
69 * made configurable somehow; preferably, the clients (at least the
70 * ones using slave transfers) should be able to give us a hint.
72 #define NR_DESCS_PER_CHANNEL 64
74 /*----------------------------------------------------------------------*/
77 * Because we're not relying on writeback from the controller (it may not
78 * even be configured into the core!) we don't need to use dma_pool. These
79 * descriptors -- and associated data -- are cacheable. We do need to make
80 * sure their dcache entries are written back before handing them off to
81 * the controller, though.
84 static struct device *chan2dev(struct dma_chan *chan)
86 return &chan->dev->device;
88 static struct device *chan2parent(struct dma_chan *chan)
90 return chan->dev->device.parent;
93 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
95 return list_entry(dwc->active_list.next, struct dw_desc, desc_node);
98 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
100 struct dw_desc *desc, *_desc;
101 struct dw_desc *ret = NULL;
105 spin_lock_irqsave(&dwc->lock, flags);
106 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
107 if (async_tx_test_ack(&desc->txd)) {
108 list_del(&desc->desc_node);
112 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
115 spin_unlock_irqrestore(&dwc->lock, flags);
117 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
122 static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc)
124 struct dw_desc *child;
126 list_for_each_entry(child, &desc->tx_list, desc_node)
127 dma_sync_single_for_cpu(chan2parent(&dwc->chan),
128 child->txd.phys, sizeof(child->lli),
130 dma_sync_single_for_cpu(chan2parent(&dwc->chan),
131 desc->txd.phys, sizeof(desc->lli),
136 * Move a descriptor, including any children, to the free list.
137 * `desc' must not be on any lists.
139 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
144 struct dw_desc *child;
146 dwc_sync_desc_for_cpu(dwc, desc);
148 spin_lock_irqsave(&dwc->lock, flags);
149 list_for_each_entry(child, &desc->tx_list, desc_node)
150 dev_vdbg(chan2dev(&dwc->chan),
151 "moving child desc %p to freelist\n",
153 list_splice_init(&desc->tx_list, &dwc->free_list);
154 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
155 list_add(&desc->desc_node, &dwc->free_list);
156 spin_unlock_irqrestore(&dwc->lock, flags);
160 static void dwc_initialize(struct dw_dma_chan *dwc)
162 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
163 struct dw_dma_slave *dws = dwc->chan.private;
164 u32 cfghi = DWC_CFGH_FIFO_MODE;
165 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
167 if (dwc->initialized == true)
172 * We need controller-specific data to set up slave
175 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
178 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
181 channel_writel(dwc, CFG_LO, cfglo);
182 channel_writel(dwc, CFG_HI, cfghi);
184 /* Enable interrupts */
185 channel_set_bit(dw, MASK.XFER, dwc->mask);
186 channel_set_bit(dw, MASK.ERROR, dwc->mask);
188 dwc->initialized = true;
191 /*----------------------------------------------------------------------*/
193 /* Called with dwc->lock held and bh disabled */
194 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
196 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
198 /* ASSERT: channel is idle */
199 if (dma_readl(dw, CH_EN) & dwc->mask) {
200 dev_err(chan2dev(&dwc->chan),
201 "BUG: Attempted to start non-idle channel\n");
202 dev_err(chan2dev(&dwc->chan),
203 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
204 channel_readl(dwc, SAR),
205 channel_readl(dwc, DAR),
206 channel_readl(dwc, LLP),
207 channel_readl(dwc, CTL_HI),
208 channel_readl(dwc, CTL_LO));
210 /* The tasklet will hopefully advance the queue... */
216 channel_writel(dwc, LLP, first->txd.phys);
217 channel_writel(dwc, CTL_LO,
218 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
219 channel_writel(dwc, CTL_HI, 0);
220 channel_set_bit(dw, CH_EN, dwc->mask);
223 /*----------------------------------------------------------------------*/
226 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
227 bool callback_required)
229 dma_async_tx_callback callback = NULL;
231 struct dma_async_tx_descriptor *txd = &desc->txd;
232 struct dw_desc *child;
235 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
237 spin_lock_irqsave(&dwc->lock, flags);
238 dwc->chan.completed_cookie = txd->cookie;
239 if (callback_required) {
240 callback = txd->callback;
241 param = txd->callback_param;
244 dwc_sync_desc_for_cpu(dwc, desc);
247 list_for_each_entry(child, &desc->tx_list, desc_node)
248 async_tx_ack(&child->txd);
249 async_tx_ack(&desc->txd);
251 list_splice_init(&desc->tx_list, &dwc->free_list);
252 list_move(&desc->desc_node, &dwc->free_list);
254 if (!dwc->chan.private) {
255 struct device *parent = chan2parent(&dwc->chan);
256 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
257 if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
258 dma_unmap_single(parent, desc->lli.dar,
259 desc->len, DMA_FROM_DEVICE);
261 dma_unmap_page(parent, desc->lli.dar,
262 desc->len, DMA_FROM_DEVICE);
264 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
265 if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
266 dma_unmap_single(parent, desc->lli.sar,
267 desc->len, DMA_TO_DEVICE);
269 dma_unmap_page(parent, desc->lli.sar,
270 desc->len, DMA_TO_DEVICE);
274 spin_unlock_irqrestore(&dwc->lock, flags);
276 if (callback_required && callback)
280 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
282 struct dw_desc *desc, *_desc;
286 spin_lock_irqsave(&dwc->lock, flags);
287 if (dma_readl(dw, CH_EN) & dwc->mask) {
288 dev_err(chan2dev(&dwc->chan),
289 "BUG: XFER bit set, but channel not idle!\n");
291 /* Try to continue after resetting the channel... */
292 channel_clear_bit(dw, CH_EN, dwc->mask);
293 while (dma_readl(dw, CH_EN) & dwc->mask)
298 * Submit queued descriptors ASAP, i.e. before we go through
299 * the completed ones.
301 list_splice_init(&dwc->active_list, &list);
302 if (!list_empty(&dwc->queue)) {
303 list_move(dwc->queue.next, &dwc->active_list);
304 dwc_dostart(dwc, dwc_first_active(dwc));
307 spin_unlock_irqrestore(&dwc->lock, flags);
309 list_for_each_entry_safe(desc, _desc, &list, desc_node)
310 dwc_descriptor_complete(dwc, desc, true);
313 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
316 struct dw_desc *desc, *_desc;
317 struct dw_desc *child;
321 spin_lock_irqsave(&dwc->lock, flags);
322 llp = channel_readl(dwc, LLP);
323 status_xfer = dma_readl(dw, RAW.XFER);
325 if (status_xfer & dwc->mask) {
326 /* Everything we've submitted is done */
327 dma_writel(dw, CLEAR.XFER, dwc->mask);
328 spin_unlock_irqrestore(&dwc->lock, flags);
330 dwc_complete_all(dw, dwc);
334 if (list_empty(&dwc->active_list)) {
335 spin_unlock_irqrestore(&dwc->lock, flags);
339 dev_vdbg(chan2dev(&dwc->chan), "scan_descriptors: llp=0x%x\n", llp);
341 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
342 /* check first descriptors addr */
343 if (desc->txd.phys == llp) {
344 spin_unlock_irqrestore(&dwc->lock, flags);
348 /* check first descriptors llp */
349 if (desc->lli.llp == llp) {
350 /* This one is currently in progress */
351 spin_unlock_irqrestore(&dwc->lock, flags);
355 list_for_each_entry(child, &desc->tx_list, desc_node)
356 if (child->lli.llp == llp) {
357 /* Currently in progress */
358 spin_unlock_irqrestore(&dwc->lock, flags);
363 * No descriptors so far seem to be in progress, i.e.
364 * this one must be done.
366 spin_unlock_irqrestore(&dwc->lock, flags);
367 dwc_descriptor_complete(dwc, desc, true);
368 spin_lock_irqsave(&dwc->lock, flags);
371 dev_err(chan2dev(&dwc->chan),
372 "BUG: All descriptors done, but channel not idle!\n");
374 /* Try to continue after resetting the channel... */
375 channel_clear_bit(dw, CH_EN, dwc->mask);
376 while (dma_readl(dw, CH_EN) & dwc->mask)
379 if (!list_empty(&dwc->queue)) {
380 list_move(dwc->queue.next, &dwc->active_list);
381 dwc_dostart(dwc, dwc_first_active(dwc));
383 spin_unlock_irqrestore(&dwc->lock, flags);
386 static void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
388 dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
389 " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
390 lli->sar, lli->dar, lli->llp,
391 lli->ctlhi, lli->ctllo);
394 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
396 struct dw_desc *bad_desc;
397 struct dw_desc *child;
400 dwc_scan_descriptors(dw, dwc);
402 spin_lock_irqsave(&dwc->lock, flags);
405 * The descriptor currently at the head of the active list is
406 * borked. Since we don't have any way to report errors, we'll
407 * just have to scream loudly and try to carry on.
409 bad_desc = dwc_first_active(dwc);
410 list_del_init(&bad_desc->desc_node);
411 list_move(dwc->queue.next, dwc->active_list.prev);
413 /* Clear the error flag and try to restart the controller */
414 dma_writel(dw, CLEAR.ERROR, dwc->mask);
415 if (!list_empty(&dwc->active_list))
416 dwc_dostart(dwc, dwc_first_active(dwc));
419 * KERN_CRITICAL may seem harsh, but since this only happens
420 * when someone submits a bad physical address in a
421 * descriptor, we should consider ourselves lucky that the
422 * controller flagged an error instead of scribbling over
423 * random memory locations.
425 dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
426 "Bad descriptor submitted for DMA!\n");
427 dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
428 " cookie: %d\n", bad_desc->txd.cookie);
429 dwc_dump_lli(dwc, &bad_desc->lli);
430 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
431 dwc_dump_lli(dwc, &child->lli);
433 spin_unlock_irqrestore(&dwc->lock, flags);
435 /* Pretend the descriptor completed successfully */
436 dwc_descriptor_complete(dwc, bad_desc, true);
439 /* --------------------- Cyclic DMA API extensions -------------------- */
441 inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
443 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
444 return channel_readl(dwc, SAR);
446 EXPORT_SYMBOL(dw_dma_get_src_addr);
448 inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
450 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
451 return channel_readl(dwc, DAR);
453 EXPORT_SYMBOL(dw_dma_get_dst_addr);
455 /* called with dwc->lock held and all DMAC interrupts disabled */
456 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
457 u32 status_err, u32 status_xfer)
462 void (*callback)(void *param);
463 void *callback_param;
465 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
466 channel_readl(dwc, LLP));
468 callback = dwc->cdesc->period_callback;
469 callback_param = dwc->cdesc->period_callback_param;
472 callback(callback_param);
476 * Error and transfer complete are highly unlikely, and will most
477 * likely be due to a configuration error by the user.
479 if (unlikely(status_err & dwc->mask) ||
480 unlikely(status_xfer & dwc->mask)) {
483 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
484 "interrupt, stopping DMA transfer\n",
485 status_xfer ? "xfer" : "error");
487 spin_lock_irqsave(&dwc->lock, flags);
489 dev_err(chan2dev(&dwc->chan),
490 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
491 channel_readl(dwc, SAR),
492 channel_readl(dwc, DAR),
493 channel_readl(dwc, LLP),
494 channel_readl(dwc, CTL_HI),
495 channel_readl(dwc, CTL_LO));
497 channel_clear_bit(dw, CH_EN, dwc->mask);
498 while (dma_readl(dw, CH_EN) & dwc->mask)
501 /* make sure DMA does not restart by loading a new list */
502 channel_writel(dwc, LLP, 0);
503 channel_writel(dwc, CTL_LO, 0);
504 channel_writel(dwc, CTL_HI, 0);
506 dma_writel(dw, CLEAR.ERROR, dwc->mask);
507 dma_writel(dw, CLEAR.XFER, dwc->mask);
509 for (i = 0; i < dwc->cdesc->periods; i++)
510 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
512 spin_unlock_irqrestore(&dwc->lock, flags);
516 /* ------------------------------------------------------------------------- */
518 static void dw_dma_tasklet(unsigned long data)
520 struct dw_dma *dw = (struct dw_dma *)data;
521 struct dw_dma_chan *dwc;
526 status_xfer = dma_readl(dw, RAW.XFER);
527 status_err = dma_readl(dw, RAW.ERROR);
529 dev_vdbg(dw->dma.dev, "tasklet: status_err=%x\n", status_err);
531 for (i = 0; i < dw->dma.chancnt; i++) {
533 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
534 dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
535 else if (status_err & (1 << i))
536 dwc_handle_error(dw, dwc);
537 else if (status_xfer & (1 << i))
538 dwc_scan_descriptors(dw, dwc);
542 * Re-enable interrupts.
544 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
545 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
548 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
550 struct dw_dma *dw = dev_id;
553 dev_vdbg(dw->dma.dev, "interrupt: status=0x%x\n",
554 dma_readl(dw, STATUS_INT));
557 * Just disable the interrupts. We'll turn them back on in the
560 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
561 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
563 status = dma_readl(dw, STATUS_INT);
566 "BUG: Unexpected interrupts pending: 0x%x\n",
570 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
571 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
572 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
573 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
576 tasklet_schedule(&dw->tasklet);
581 /*----------------------------------------------------------------------*/
583 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
585 struct dw_desc *desc = txd_to_dw_desc(tx);
586 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
590 spin_lock_irqsave(&dwc->lock, flags);
591 cookie = dma_cookie_assign(tx);
594 * REVISIT: We should attempt to chain as many descriptors as
595 * possible, perhaps even appending to those already submitted
596 * for DMA. But this is hard to do in a race-free manner.
598 if (list_empty(&dwc->active_list)) {
599 dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
601 list_add_tail(&desc->desc_node, &dwc->active_list);
602 dwc_dostart(dwc, dwc_first_active(dwc));
604 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
607 list_add_tail(&desc->desc_node, &dwc->queue);
610 spin_unlock_irqrestore(&dwc->lock, flags);
615 static struct dma_async_tx_descriptor *
616 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
617 size_t len, unsigned long flags)
619 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
620 struct dw_desc *desc;
621 struct dw_desc *first;
622 struct dw_desc *prev;
625 unsigned int src_width;
626 unsigned int dst_width;
629 dev_vdbg(chan2dev(chan), "prep_dma_memcpy d0x%x s0x%x l0x%zx f0x%lx\n",
630 dest, src, len, flags);
632 if (unlikely(!len)) {
633 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
638 * We can be a lot more clever here, but this should take care
639 * of the most common optimization.
641 if (!((src | dest | len) & 7))
642 src_width = dst_width = 3;
643 else if (!((src | dest | len) & 3))
644 src_width = dst_width = 2;
645 else if (!((src | dest | len) & 1))
646 src_width = dst_width = 1;
648 src_width = dst_width = 0;
650 ctllo = DWC_DEFAULT_CTLLO(chan)
651 | DWC_CTLL_DST_WIDTH(dst_width)
652 | DWC_CTLL_SRC_WIDTH(src_width)
658 for (offset = 0; offset < len; offset += xfer_count << src_width) {
659 xfer_count = min_t(size_t, (len - offset) >> src_width,
662 desc = dwc_desc_get(dwc);
666 desc->lli.sar = src + offset;
667 desc->lli.dar = dest + offset;
668 desc->lli.ctllo = ctllo;
669 desc->lli.ctlhi = xfer_count;
674 prev->lli.llp = desc->txd.phys;
675 dma_sync_single_for_device(chan2parent(chan),
676 prev->txd.phys, sizeof(prev->lli),
678 list_add_tail(&desc->desc_node,
685 if (flags & DMA_PREP_INTERRUPT)
686 /* Trigger interrupt after last block */
687 prev->lli.ctllo |= DWC_CTLL_INT_EN;
690 dma_sync_single_for_device(chan2parent(chan),
691 prev->txd.phys, sizeof(prev->lli),
694 first->txd.flags = flags;
700 dwc_desc_put(dwc, first);
704 static struct dma_async_tx_descriptor *
705 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
706 unsigned int sg_len, enum dma_transfer_direction direction,
709 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
710 struct dw_dma_slave *dws = chan->private;
711 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
712 struct dw_desc *prev;
713 struct dw_desc *first;
716 unsigned int reg_width;
717 unsigned int mem_width;
719 struct scatterlist *sg;
720 size_t total_len = 0;
722 dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
724 if (unlikely(!dws || !sg_len))
731 reg_width = __fls(sconfig->dst_addr_width);
732 reg = sconfig->dst_addr;
733 ctllo = (DWC_DEFAULT_CTLLO(chan)
734 | DWC_CTLL_DST_WIDTH(reg_width)
738 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
739 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
741 for_each_sg(sgl, sg, sg_len, i) {
742 struct dw_desc *desc;
746 len = sg_dma_len(sg);
748 if (!((mem | len) & 7))
750 else if (!((mem | len) & 3))
752 else if (!((mem | len) & 1))
757 slave_sg_todev_fill_desc:
758 desc = dwc_desc_get(dwc);
760 dev_err(chan2dev(chan),
761 "not enough descriptors available\n");
767 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
768 if ((len >> mem_width) > DWC_MAX_COUNT) {
769 dlen = DWC_MAX_COUNT << mem_width;
777 desc->lli.ctlhi = dlen >> mem_width;
782 prev->lli.llp = desc->txd.phys;
783 dma_sync_single_for_device(chan2parent(chan),
787 list_add_tail(&desc->desc_node,
794 goto slave_sg_todev_fill_desc;
798 reg_width = __fls(sconfig->src_addr_width);
799 reg = sconfig->src_addr;
800 ctllo = (DWC_DEFAULT_CTLLO(chan)
801 | DWC_CTLL_SRC_WIDTH(reg_width)
805 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
806 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
808 for_each_sg(sgl, sg, sg_len, i) {
809 struct dw_desc *desc;
813 len = sg_dma_len(sg);
815 if (!((mem | len) & 7))
817 else if (!((mem | len) & 3))
819 else if (!((mem | len) & 1))
824 slave_sg_fromdev_fill_desc:
825 desc = dwc_desc_get(dwc);
827 dev_err(chan2dev(chan),
828 "not enough descriptors available\n");
834 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
835 if ((len >> reg_width) > DWC_MAX_COUNT) {
836 dlen = DWC_MAX_COUNT << reg_width;
843 desc->lli.ctlhi = dlen >> reg_width;
848 prev->lli.llp = desc->txd.phys;
849 dma_sync_single_for_device(chan2parent(chan),
853 list_add_tail(&desc->desc_node,
860 goto slave_sg_fromdev_fill_desc;
867 if (flags & DMA_PREP_INTERRUPT)
868 /* Trigger interrupt after last block */
869 prev->lli.ctllo |= DWC_CTLL_INT_EN;
872 dma_sync_single_for_device(chan2parent(chan),
873 prev->txd.phys, sizeof(prev->lli),
876 first->len = total_len;
881 dwc_desc_put(dwc, first);
886 * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
887 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
889 * NOTE: burst size 2 is not supported by controller.
891 * This can be done by finding least significant bit set: n & (n - 1)
893 static inline void convert_burst(u32 *maxburst)
896 *maxburst = fls(*maxburst) - 2;
902 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
904 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
906 /* Check if it is chan is configured for slave transfers */
910 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
912 convert_burst(&dwc->dma_sconfig.src_maxburst);
913 convert_burst(&dwc->dma_sconfig.dst_maxburst);
918 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
921 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
922 struct dw_dma *dw = to_dw_dma(chan->device);
923 struct dw_desc *desc, *_desc;
928 if (cmd == DMA_PAUSE) {
929 spin_lock_irqsave(&dwc->lock, flags);
931 cfglo = channel_readl(dwc, CFG_LO);
932 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
933 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY))
937 spin_unlock_irqrestore(&dwc->lock, flags);
938 } else if (cmd == DMA_RESUME) {
942 spin_lock_irqsave(&dwc->lock, flags);
944 cfglo = channel_readl(dwc, CFG_LO);
945 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
948 spin_unlock_irqrestore(&dwc->lock, flags);
949 } else if (cmd == DMA_TERMINATE_ALL) {
950 spin_lock_irqsave(&dwc->lock, flags);
952 channel_clear_bit(dw, CH_EN, dwc->mask);
953 while (dma_readl(dw, CH_EN) & dwc->mask)
958 /* active_list entries will end up before queued entries */
959 list_splice_init(&dwc->queue, &list);
960 list_splice_init(&dwc->active_list, &list);
962 spin_unlock_irqrestore(&dwc->lock, flags);
964 /* Flush all pending and queued descriptors */
965 list_for_each_entry_safe(desc, _desc, &list, desc_node)
966 dwc_descriptor_complete(dwc, desc, false);
967 } else if (cmd == DMA_SLAVE_CONFIG) {
968 return set_runtime_config(chan, (struct dma_slave_config *)arg);
976 static enum dma_status
977 dwc_tx_status(struct dma_chan *chan,
979 struct dma_tx_state *txstate)
981 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
982 dma_cookie_t last_used;
983 dma_cookie_t last_complete;
986 last_complete = chan->completed_cookie;
987 last_used = chan->cookie;
989 ret = dma_async_is_complete(cookie, last_complete, last_used);
990 if (ret != DMA_SUCCESS) {
991 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
993 last_complete = chan->completed_cookie;
994 last_used = chan->cookie;
996 ret = dma_async_is_complete(cookie, last_complete, last_used);
999 if (ret != DMA_SUCCESS)
1000 dma_set_tx_state(txstate, last_complete, last_used,
1001 dwc_first_active(dwc)->len);
1003 dma_set_tx_state(txstate, last_complete, last_used, 0);
1011 static void dwc_issue_pending(struct dma_chan *chan)
1013 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1015 if (!list_empty(&dwc->queue))
1016 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1019 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1021 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1022 struct dw_dma *dw = to_dw_dma(chan->device);
1023 struct dw_desc *desc;
1025 unsigned long flags;
1027 dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
1029 /* ASSERT: channel is idle */
1030 if (dma_readl(dw, CH_EN) & dwc->mask) {
1031 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1035 chan->completed_cookie = chan->cookie = 1;
1038 * NOTE: some controllers may have additional features that we
1039 * need to initialize here, like "scatter-gather" (which
1040 * doesn't mean what you think it means), and status writeback.
1043 spin_lock_irqsave(&dwc->lock, flags);
1044 i = dwc->descs_allocated;
1045 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1046 spin_unlock_irqrestore(&dwc->lock, flags);
1048 desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL);
1050 dev_info(chan2dev(chan),
1051 "only allocated %d descriptors\n", i);
1052 spin_lock_irqsave(&dwc->lock, flags);
1056 INIT_LIST_HEAD(&desc->tx_list);
1057 dma_async_tx_descriptor_init(&desc->txd, chan);
1058 desc->txd.tx_submit = dwc_tx_submit;
1059 desc->txd.flags = DMA_CTRL_ACK;
1060 desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli,
1061 sizeof(desc->lli), DMA_TO_DEVICE);
1062 dwc_desc_put(dwc, desc);
1064 spin_lock_irqsave(&dwc->lock, flags);
1065 i = ++dwc->descs_allocated;
1068 spin_unlock_irqrestore(&dwc->lock, flags);
1070 dev_dbg(chan2dev(chan),
1071 "alloc_chan_resources allocated %d descriptors\n", i);
1076 static void dwc_free_chan_resources(struct dma_chan *chan)
1078 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1079 struct dw_dma *dw = to_dw_dma(chan->device);
1080 struct dw_desc *desc, *_desc;
1081 unsigned long flags;
1084 dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
1085 dwc->descs_allocated);
1087 /* ASSERT: channel is idle */
1088 BUG_ON(!list_empty(&dwc->active_list));
1089 BUG_ON(!list_empty(&dwc->queue));
1090 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1092 spin_lock_irqsave(&dwc->lock, flags);
1093 list_splice_init(&dwc->free_list, &list);
1094 dwc->descs_allocated = 0;
1095 dwc->initialized = false;
1097 /* Disable interrupts */
1098 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1099 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1101 spin_unlock_irqrestore(&dwc->lock, flags);
1103 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1104 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1105 dma_unmap_single(chan2parent(chan), desc->txd.phys,
1106 sizeof(desc->lli), DMA_TO_DEVICE);
1110 dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
1113 /* --------------------- Cyclic DMA API extensions -------------------- */
1116 * dw_dma_cyclic_start - start the cyclic DMA transfer
1117 * @chan: the DMA channel to start
1119 * Must be called with soft interrupts disabled. Returns zero on success or
1120 * -errno on failure.
1122 int dw_dma_cyclic_start(struct dma_chan *chan)
1124 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1125 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1126 unsigned long flags;
1128 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1129 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1133 spin_lock_irqsave(&dwc->lock, flags);
1135 /* assert channel is idle */
1136 if (dma_readl(dw, CH_EN) & dwc->mask) {
1137 dev_err(chan2dev(&dwc->chan),
1138 "BUG: Attempted to start non-idle channel\n");
1139 dev_err(chan2dev(&dwc->chan),
1140 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
1141 channel_readl(dwc, SAR),
1142 channel_readl(dwc, DAR),
1143 channel_readl(dwc, LLP),
1144 channel_readl(dwc, CTL_HI),
1145 channel_readl(dwc, CTL_LO));
1146 spin_unlock_irqrestore(&dwc->lock, flags);
1150 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1151 dma_writel(dw, CLEAR.XFER, dwc->mask);
1153 /* setup DMAC channel registers */
1154 channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1155 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1156 channel_writel(dwc, CTL_HI, 0);
1158 channel_set_bit(dw, CH_EN, dwc->mask);
1160 spin_unlock_irqrestore(&dwc->lock, flags);
1164 EXPORT_SYMBOL(dw_dma_cyclic_start);
1167 * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1168 * @chan: the DMA channel to stop
1170 * Must be called with soft interrupts disabled.
1172 void dw_dma_cyclic_stop(struct dma_chan *chan)
1174 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1175 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1176 unsigned long flags;
1178 spin_lock_irqsave(&dwc->lock, flags);
1180 channel_clear_bit(dw, CH_EN, dwc->mask);
1181 while (dma_readl(dw, CH_EN) & dwc->mask)
1184 spin_unlock_irqrestore(&dwc->lock, flags);
1186 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1189 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1190 * @chan: the DMA channel to prepare
1191 * @buf_addr: physical DMA address where the buffer starts
1192 * @buf_len: total number of bytes for the entire buffer
1193 * @period_len: number of bytes for each period
1194 * @direction: transfer direction, to or from device
1196 * Must be called before trying to start the transfer. Returns a valid struct
1197 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1199 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1200 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1201 enum dma_transfer_direction direction)
1203 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1204 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
1205 struct dw_cyclic_desc *cdesc;
1206 struct dw_cyclic_desc *retval = NULL;
1207 struct dw_desc *desc;
1208 struct dw_desc *last = NULL;
1209 unsigned long was_cyclic;
1210 unsigned int reg_width;
1211 unsigned int periods;
1213 unsigned long flags;
1215 spin_lock_irqsave(&dwc->lock, flags);
1216 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1217 spin_unlock_irqrestore(&dwc->lock, flags);
1218 dev_dbg(chan2dev(&dwc->chan),
1219 "queue and/or active list are not empty\n");
1220 return ERR_PTR(-EBUSY);
1223 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1224 spin_unlock_irqrestore(&dwc->lock, flags);
1226 dev_dbg(chan2dev(&dwc->chan),
1227 "channel already prepared for cyclic DMA\n");
1228 return ERR_PTR(-EBUSY);
1231 retval = ERR_PTR(-EINVAL);
1233 if (direction == DMA_MEM_TO_DEV)
1234 reg_width = __ffs(sconfig->dst_addr_width);
1236 reg_width = __ffs(sconfig->src_addr_width);
1238 periods = buf_len / period_len;
1240 /* Check for too big/unaligned periods and unaligned DMA buffer. */
1241 if (period_len > (DWC_MAX_COUNT << reg_width))
1243 if (unlikely(period_len & ((1 << reg_width) - 1)))
1245 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1247 if (unlikely(!(direction & (DMA_MEM_TO_DEV | DMA_DEV_TO_MEM))))
1250 retval = ERR_PTR(-ENOMEM);
1252 if (periods > NR_DESCS_PER_CHANNEL)
1255 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1259 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1263 for (i = 0; i < periods; i++) {
1264 desc = dwc_desc_get(dwc);
1266 goto out_err_desc_get;
1268 switch (direction) {
1269 case DMA_MEM_TO_DEV:
1270 desc->lli.dar = sconfig->dst_addr;
1271 desc->lli.sar = buf_addr + (period_len * i);
1272 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1273 | DWC_CTLL_DST_WIDTH(reg_width)
1274 | DWC_CTLL_SRC_WIDTH(reg_width)
1279 desc->lli.ctllo |= sconfig->device_fc ?
1280 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1281 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1284 case DMA_DEV_TO_MEM:
1285 desc->lli.dar = buf_addr + (period_len * i);
1286 desc->lli.sar = sconfig->src_addr;
1287 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1288 | DWC_CTLL_SRC_WIDTH(reg_width)
1289 | DWC_CTLL_DST_WIDTH(reg_width)
1294 desc->lli.ctllo |= sconfig->device_fc ?
1295 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1296 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1303 desc->lli.ctlhi = (period_len >> reg_width);
1304 cdesc->desc[i] = desc;
1307 last->lli.llp = desc->txd.phys;
1308 dma_sync_single_for_device(chan2parent(chan),
1309 last->txd.phys, sizeof(last->lli),
1316 /* lets make a cyclic list */
1317 last->lli.llp = cdesc->desc[0]->txd.phys;
1318 dma_sync_single_for_device(chan2parent(chan), last->txd.phys,
1319 sizeof(last->lli), DMA_TO_DEVICE);
1321 dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%08x len %zu "
1322 "period %zu periods %d\n", buf_addr, buf_len,
1323 period_len, periods);
1325 cdesc->periods = periods;
1332 dwc_desc_put(dwc, cdesc->desc[i]);
1336 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1337 return (struct dw_cyclic_desc *)retval;
1339 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1342 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1343 * @chan: the DMA channel to free
1345 void dw_dma_cyclic_free(struct dma_chan *chan)
1347 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1348 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1349 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1351 unsigned long flags;
1353 dev_dbg(chan2dev(&dwc->chan), "cyclic free\n");
1358 spin_lock_irqsave(&dwc->lock, flags);
1360 channel_clear_bit(dw, CH_EN, dwc->mask);
1361 while (dma_readl(dw, CH_EN) & dwc->mask)
1364 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1365 dma_writel(dw, CLEAR.XFER, dwc->mask);
1367 spin_unlock_irqrestore(&dwc->lock, flags);
1369 for (i = 0; i < cdesc->periods; i++)
1370 dwc_desc_put(dwc, cdesc->desc[i]);
1375 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1377 EXPORT_SYMBOL(dw_dma_cyclic_free);
1379 /*----------------------------------------------------------------------*/
1381 static void dw_dma_off(struct dw_dma *dw)
1385 dma_writel(dw, CFG, 0);
1387 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1388 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1389 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1390 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1392 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1395 for (i = 0; i < dw->dma.chancnt; i++)
1396 dw->chan[i].initialized = false;
1399 static int __init dw_probe(struct platform_device *pdev)
1401 struct dw_dma_platform_data *pdata;
1402 struct resource *io;
1409 pdata = dev_get_platdata(&pdev->dev);
1410 if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1413 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1417 irq = platform_get_irq(pdev, 0);
1421 size = sizeof(struct dw_dma);
1422 size += pdata->nr_channels * sizeof(struct dw_dma_chan);
1423 dw = kzalloc(size, GFP_KERNEL);
1427 if (!request_mem_region(io->start, DW_REGLEN, pdev->dev.driver->name)) {
1432 dw->regs = ioremap(io->start, DW_REGLEN);
1438 dw->clk = clk_get(&pdev->dev, "hclk");
1439 if (IS_ERR(dw->clk)) {
1440 err = PTR_ERR(dw->clk);
1443 clk_enable(dw->clk);
1445 /* force dma off, just in case */
1448 err = request_irq(irq, dw_dma_interrupt, 0, "dw_dmac", dw);
1452 platform_set_drvdata(pdev, dw);
1454 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1456 dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1458 INIT_LIST_HEAD(&dw->dma.channels);
1459 for (i = 0; i < pdata->nr_channels; i++) {
1460 struct dw_dma_chan *dwc = &dw->chan[i];
1462 dwc->chan.device = &dw->dma;
1463 dwc->chan.cookie = dwc->chan.completed_cookie = 1;
1464 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1465 list_add_tail(&dwc->chan.device_node,
1468 list_add(&dwc->chan.device_node, &dw->dma.channels);
1470 /* 7 is highest priority & 0 is lowest. */
1471 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1472 dwc->priority = pdata->nr_channels - i - 1;
1476 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1477 spin_lock_init(&dwc->lock);
1480 INIT_LIST_HEAD(&dwc->active_list);
1481 INIT_LIST_HEAD(&dwc->queue);
1482 INIT_LIST_HEAD(&dwc->free_list);
1484 channel_clear_bit(dw, CH_EN, dwc->mask);
1487 /* Clear/disable all interrupts on all channels. */
1488 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1489 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1490 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1491 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1493 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1494 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1495 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1496 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1498 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1499 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1500 if (pdata->is_private)
1501 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1502 dw->dma.dev = &pdev->dev;
1503 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1504 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1506 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1508 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1509 dw->dma.device_control = dwc_control;
1511 dw->dma.device_tx_status = dwc_tx_status;
1512 dw->dma.device_issue_pending = dwc_issue_pending;
1514 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1516 printk(KERN_INFO "%s: DesignWare DMA Controller, %d channels\n",
1517 dev_name(&pdev->dev), pdata->nr_channels);
1519 dma_async_device_register(&dw->dma);
1524 clk_disable(dw->clk);
1530 release_resource(io);
1536 static int __exit dw_remove(struct platform_device *pdev)
1538 struct dw_dma *dw = platform_get_drvdata(pdev);
1539 struct dw_dma_chan *dwc, *_dwc;
1540 struct resource *io;
1543 dma_async_device_unregister(&dw->dma);
1545 free_irq(platform_get_irq(pdev, 0), dw);
1546 tasklet_kill(&dw->tasklet);
1548 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1550 list_del(&dwc->chan.device_node);
1551 channel_clear_bit(dw, CH_EN, dwc->mask);
1554 clk_disable(dw->clk);
1560 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1561 release_mem_region(io->start, DW_REGLEN);
1568 static void dw_shutdown(struct platform_device *pdev)
1570 struct dw_dma *dw = platform_get_drvdata(pdev);
1572 dw_dma_off(platform_get_drvdata(pdev));
1573 clk_disable(dw->clk);
1576 static int dw_suspend_noirq(struct device *dev)
1578 struct platform_device *pdev = to_platform_device(dev);
1579 struct dw_dma *dw = platform_get_drvdata(pdev);
1581 dw_dma_off(platform_get_drvdata(pdev));
1582 clk_disable(dw->clk);
1587 static int dw_resume_noirq(struct device *dev)
1589 struct platform_device *pdev = to_platform_device(dev);
1590 struct dw_dma *dw = platform_get_drvdata(pdev);
1592 clk_enable(dw->clk);
1593 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1597 static const struct dev_pm_ops dw_dev_pm_ops = {
1598 .suspend_noirq = dw_suspend_noirq,
1599 .resume_noirq = dw_resume_noirq,
1600 .freeze_noirq = dw_suspend_noirq,
1601 .thaw_noirq = dw_resume_noirq,
1602 .restore_noirq = dw_resume_noirq,
1603 .poweroff_noirq = dw_suspend_noirq,
1606 static struct platform_driver dw_driver = {
1607 .remove = __exit_p(dw_remove),
1608 .shutdown = dw_shutdown,
1611 .pm = &dw_dev_pm_ops,
1615 static int __init dw_init(void)
1617 return platform_driver_probe(&dw_driver, dw_probe);
1619 subsys_initcall(dw_init);
1621 static void __exit dw_exit(void)
1623 platform_driver_unregister(&dw_driver);
1625 module_exit(dw_exit);
1627 MODULE_LICENSE("GPL v2");
1628 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1629 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1630 MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");