drivers/dma/dw_dmac.c

   1 /*
   2  * Core driver for the Synopsys DesignWare DMA Controller
   3  *
   4  * Copyright (C) 2007-2008 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/of.h>
  21 #include <linux/mm.h>
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/slab.h>
  25
  26 #include "dw_dmac_regs.h"
  27 #include "dmaengine.h"
  28
  29 /*
  30  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  31  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  32  * of which use ARM any more).  See the "Databook" from Synopsys for
  33  * information beyond what licensees probably provide.
  34  *
  35  * The driver has currently been tested only with the Atmel AT32AP7000,
  36  * which does not support descriptor writeback.
  37  */
  38
  39 static inline unsigned int dwc_get_dms(struct dw_dma_slave *slave)
  40 {
  41         return slave ? slave->dst_master : 0;
  42 }
  43
  44 static inline unsigned int dwc_get_sms(struct dw_dma_slave *slave)
  45 {
  46         return slave ? slave->src_master : 1;
  47 }
  48
  49 #define DWC_DEFAULT_CTLLO(_chan) ({                             \
  50                 struct dw_dma_slave *__slave = (_chan->private);        \
  51                 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
  52                 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
  53                 int _dms = dwc_get_dms(__slave);                \
  54                 int _sms = dwc_get_sms(__slave);                \
  55                 u8 _smsize = __slave ? _sconfig->src_maxburst : \
  56                         DW_DMA_MSIZE_16;                        \
  57                 u8 _dmsize = __slave ? _sconfig->dst_maxburst : \
  58                         DW_DMA_MSIZE_16;                        \
  59                                                                 \
  60                 (DWC_CTLL_DST_MSIZE(_dmsize)                    \
  61                  | DWC_CTLL_SRC_MSIZE(_smsize)                  \
  62                  | DWC_CTLL_LLP_D_EN                            \
  63                  | DWC_CTLL_LLP_S_EN                            \
  64                  | DWC_CTLL_DMS(_dms)                           \
  65                  | DWC_CTLL_SMS(_sms));                         \
  66         })
  67
  68 /*
  69  * Number of descriptors to allocate for each channel. This should be
  70  * made configurable somehow; preferably, the clients (at least the
  71  * ones using slave transfers) should be able to give us a hint.
  72  */
  73 #define NR_DESCS_PER_CHANNEL    64
  74
  75 /*----------------------------------------------------------------------*/
  76
  77 /*
  78  * Because we're not relying on writeback from the controller (it may not
  79  * even be configured into the core!) we don't need to use dma_pool.  These
  80  * descriptors -- and associated data -- are cacheable.  We do need to make
  81  * sure their dcache entries are written back before handing them off to
  82  * the controller, though.
  83  */
  84
  85 static struct device *chan2dev(struct dma_chan *chan)
  86 {
  87         return &chan->dev->device;
  88 }
  89 static struct device *chan2parent(struct dma_chan *chan)
  90 {
  91         return chan->dev->device.parent;
  92 }
  93
  94 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
  95 {
  96         return list_entry(dwc->active_list.next, struct dw_desc, desc_node);
  97 }
  98
  99 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
 100 {
 101         struct dw_desc *desc, *_desc;
 102         struct dw_desc *ret = NULL;
 103         unsigned int i = 0;
 104         unsigned long flags;
 105
 106         spin_lock_irqsave(&dwc->lock, flags);
 107         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
 108                 i++;
 109                 if (async_tx_test_ack(&desc->txd)) {
 110                         list_del(&desc->desc_node);
 111                         ret = desc;
 112                         break;
 113                 }
 114                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
 115         }
 116         spin_unlock_irqrestore(&dwc->lock, flags);
 117
 118         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
 119
 120         return ret;
 121 }
 122
 123 static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc)
 124 {
 125         struct dw_desc  *child;
 126
 127         list_for_each_entry(child, &desc->tx_list, desc_node)
 128                 dma_sync_single_for_cpu(chan2parent(&dwc->chan),
 129                                 child->txd.phys, sizeof(child->lli),
 130                                 DMA_TO_DEVICE);
 131         dma_sync_single_for_cpu(chan2parent(&dwc->chan),
 132                         desc->txd.phys, sizeof(desc->lli),
 133                         DMA_TO_DEVICE);
 134 }
 135
 136 /*
 137  * Move a descriptor, including any children, to the free list.
 138  * `desc' must not be on any lists.
 139  */
 140 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 141 {
 142         unsigned long flags;
 143
 144         if (desc) {
 145                 struct dw_desc *child;
 146
 147                 dwc_sync_desc_for_cpu(dwc, desc);
 148
 149                 spin_lock_irqsave(&dwc->lock, flags);
 150                 list_for_each_entry(child, &desc->tx_list, desc_node)
 151                         dev_vdbg(chan2dev(&dwc->chan),
 152                                         "moving child desc %p to freelist\n",
 153                                         child);
 154                 list_splice_init(&desc->tx_list, &dwc->free_list);
 155                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
 156                 list_add(&desc->desc_node, &dwc->free_list);
 157                 spin_unlock_irqrestore(&dwc->lock, flags);
 158         }
 159 }
 160
 161 static void dwc_initialize(struct dw_dma_chan *dwc)
 162 {
 163         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 164         struct dw_dma_slave *dws = dwc->chan.private;
 165         u32 cfghi = DWC_CFGH_FIFO_MODE;
 166         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
 167
 168         if (dwc->initialized == true)
 169                 return;
 170
 171         if (dws) {
 172                 /*
 173                  * We need controller-specific data to set up slave
 174                  * transfers.
 175                  */
 176                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 177
 178                 cfghi = dws->cfg_hi;
 179                 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
 180         } else {
 181                 if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV)
 182                         cfghi = DWC_CFGH_DST_PER(dwc->dma_sconfig.slave_id);
 183                 else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM)
 184                         cfghi = DWC_CFGH_SRC_PER(dwc->dma_sconfig.slave_id);
 185         }
 186
 187         channel_writel(dwc, CFG_LO, cfglo);
 188         channel_writel(dwc, CFG_HI, cfghi);
 189
 190         /* Enable interrupts */
 191         channel_set_bit(dw, MASK.XFER, dwc->mask);
 192         channel_set_bit(dw, MASK.ERROR, dwc->mask);
 193
 194         dwc->initialized = true;
 195 }
 196
 197 /*----------------------------------------------------------------------*/
 198
 199 static inline unsigned int dwc_fast_fls(unsigned long long v)
 200 {
 201         /*
 202          * We can be a lot more clever here, but this should take care
 203          * of the most common optimization.
 204          */
 205         if (!(v & 7))
 206                 return 3;
 207         else if (!(v & 3))
 208                 return 2;
 209         else if (!(v & 1))
 210                 return 1;
 211         return 0;
 212 }
 213
 214 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
 215 {
 216         dev_err(chan2dev(&dwc->chan),
 217                 "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 218                 channel_readl(dwc, SAR),
 219                 channel_readl(dwc, DAR),
 220                 channel_readl(dwc, LLP),
 221                 channel_readl(dwc, CTL_HI),
 222                 channel_readl(dwc, CTL_LO));
 223 }
 224
 225 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
 226 {
 227         channel_clear_bit(dw, CH_EN, dwc->mask);
 228         while (dma_readl(dw, CH_EN) & dwc->mask)
 229                 cpu_relax();
 230 }
 231
 232 /*----------------------------------------------------------------------*/
 233
 234 /* Perform single block transfer */
 235 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
 236                                        struct dw_desc *desc)
 237 {
 238         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 239         u32             ctllo;
 240
 241         /* Software emulation of LLP mode relies on interrupts to continue
 242          * multi block transfer. */
 243         ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
 244
 245         channel_writel(dwc, SAR, desc->lli.sar);
 246         channel_writel(dwc, DAR, desc->lli.dar);
 247         channel_writel(dwc, CTL_LO, ctllo);
 248         channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
 249         channel_set_bit(dw, CH_EN, dwc->mask);
 250 }
 251
 252 /* Called with dwc->lock held and bh disabled */
 253 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 254 {
 255         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 256         unsigned long   was_soft_llp;
 257
 258         /* ASSERT:  channel is idle */
 259         if (dma_readl(dw, CH_EN) & dwc->mask) {
 260                 dev_err(chan2dev(&dwc->chan),
 261                         "BUG: Attempted to start non-idle channel\n");
 262                 dwc_dump_chan_regs(dwc);
 263
 264                 /* The tasklet will hopefully advance the queue... */
 265                 return;
 266         }
 267
 268         if (dwc->nollp) {
 269                 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
 270                                                 &dwc->flags);
 271                 if (was_soft_llp) {
 272                         dev_err(chan2dev(&dwc->chan),
 273                                 "BUG: Attempted to start new LLP transfer "
 274                                 "inside ongoing one\n");
 275                         return;
 276                 }
 277
 278                 dwc_initialize(dwc);
 279
 280                 dwc->tx_list = &first->tx_list;
 281                 dwc->tx_node_active = first->tx_list.next;
 282
 283                 dwc_do_single_block(dwc, first);
 284
 285                 return;
 286         }
 287
 288         dwc_initialize(dwc);
 289
 290         channel_writel(dwc, LLP, first->txd.phys);
 291         channel_writel(dwc, CTL_LO,
 292                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 293         channel_writel(dwc, CTL_HI, 0);
 294         channel_set_bit(dw, CH_EN, dwc->mask);
 295 }
 296
 297 /*----------------------------------------------------------------------*/
 298
 299 static void
 300 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 301                 bool callback_required)
 302 {
 303         dma_async_tx_callback           callback = NULL;
 304         void                            *param = NULL;
 305         struct dma_async_tx_descriptor  *txd = &desc->txd;
 306         struct dw_desc                  *child;
 307         unsigned long                   flags;
 308
 309         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 310
 311         spin_lock_irqsave(&dwc->lock, flags);
 312         dma_cookie_complete(txd);
 313         if (callback_required) {
 314                 callback = txd->callback;
 315                 param = txd->callback_param;
 316         }
 317
 318         dwc_sync_desc_for_cpu(dwc, desc);
 319
 320         /* async_tx_ack */
 321         list_for_each_entry(child, &desc->tx_list, desc_node)
 322                 async_tx_ack(&child->txd);
 323         async_tx_ack(&desc->txd);
 324
 325         list_splice_init(&desc->tx_list, &dwc->free_list);
 326         list_move(&desc->desc_node, &dwc->free_list);
 327
 328         if (!dwc->chan.private) {
 329                 struct device *parent = chan2parent(&dwc->chan);
 330                 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
 331                         if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
 332                                 dma_unmap_single(parent, desc->lli.dar,
 333                                                 desc->len, DMA_FROM_DEVICE);
 334                         else
 335                                 dma_unmap_page(parent, desc->lli.dar,
 336                                                 desc->len, DMA_FROM_DEVICE);
 337                 }
 338                 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
 339                         if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
 340                                 dma_unmap_single(parent, desc->lli.sar,
 341                                                 desc->len, DMA_TO_DEVICE);
 342                         else
 343                                 dma_unmap_page(parent, desc->lli.sar,
 344                                                 desc->len, DMA_TO_DEVICE);
 345                 }
 346         }
 347
 348         spin_unlock_irqrestore(&dwc->lock, flags);
 349
 350         if (callback_required && callback)
 351                 callback(param);
 352 }
 353
 354 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 355 {
 356         struct dw_desc *desc, *_desc;
 357         LIST_HEAD(list);
 358         unsigned long flags;
 359
 360         spin_lock_irqsave(&dwc->lock, flags);
 361         if (dma_readl(dw, CH_EN) & dwc->mask) {
 362                 dev_err(chan2dev(&dwc->chan),
 363                         "BUG: XFER bit set, but channel not idle!\n");
 364
 365                 /* Try to continue after resetting the channel... */
 366                 dwc_chan_disable(dw, dwc);
 367         }
 368
 369         /*
 370          * Submit queued descriptors ASAP, i.e. before we go through
 371          * the completed ones.
 372          */
 373         list_splice_init(&dwc->active_list, &list);
 374         if (!list_empty(&dwc->queue)) {
 375                 list_move(dwc->queue.next, &dwc->active_list);
 376                 dwc_dostart(dwc, dwc_first_active(dwc));
 377         }
 378
 379         spin_unlock_irqrestore(&dwc->lock, flags);
 380
 381         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 382                 dwc_descriptor_complete(dwc, desc, true);
 383 }
 384
 385 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 386 {
 387         dma_addr_t llp;
 388         struct dw_desc *desc, *_desc;
 389         struct dw_desc *child;
 390         u32 status_xfer;
 391         unsigned long flags;
 392
 393         spin_lock_irqsave(&dwc->lock, flags);
 394         llp = channel_readl(dwc, LLP);
 395         status_xfer = dma_readl(dw, RAW.XFER);
 396
 397         if (status_xfer & dwc->mask) {
 398                 /* Everything we've submitted is done */
 399                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 400                 spin_unlock_irqrestore(&dwc->lock, flags);
 401
 402                 dwc_complete_all(dw, dwc);
 403                 return;
 404         }
 405
 406         if (list_empty(&dwc->active_list)) {
 407                 spin_unlock_irqrestore(&dwc->lock, flags);
 408                 return;
 409         }
 410
 411         dev_vdbg(chan2dev(&dwc->chan), "%s: llp=0x%llx\n", __func__,
 412                         (unsigned long long)llp);
 413
 414         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 415                 /* check first descriptors addr */
 416                 if (desc->txd.phys == llp) {
 417                         spin_unlock_irqrestore(&dwc->lock, flags);
 418                         return;
 419                 }
 420
 421                 /* check first descriptors llp */
 422                 if (desc->lli.llp == llp) {
 423                         /* This one is currently in progress */
 424                         spin_unlock_irqrestore(&dwc->lock, flags);
 425                         return;
 426                 }
 427
 428                 list_for_each_entry(child, &desc->tx_list, desc_node)
 429                         if (child->lli.llp == llp) {
 430                                 /* Currently in progress */
 431                                 spin_unlock_irqrestore(&dwc->lock, flags);
 432                                 return;
 433                         }
 434
 435                 /*
 436                  * No descriptors so far seem to be in progress, i.e.
 437                  * this one must be done.
 438                  */
 439                 spin_unlock_irqrestore(&dwc->lock, flags);
 440                 dwc_descriptor_complete(dwc, desc, true);
 441                 spin_lock_irqsave(&dwc->lock, flags);
 442         }
 443
 444         dev_err(chan2dev(&dwc->chan),
 445                 "BUG: All descriptors done, but channel not idle!\n");
 446
 447         /* Try to continue after resetting the channel... */
 448         dwc_chan_disable(dw, dwc);
 449
 450         if (!list_empty(&dwc->queue)) {
 451                 list_move(dwc->queue.next, &dwc->active_list);
 452                 dwc_dostart(dwc, dwc_first_active(dwc));
 453         }
 454         spin_unlock_irqrestore(&dwc->lock, flags);
 455 }
 456
 457 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 458 {
 459         dev_crit(chan2dev(&dwc->chan), "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 460                  lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
 461 }
 462
 463 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 464 {
 465         struct dw_desc *bad_desc;
 466         struct dw_desc *child;
 467         unsigned long flags;
 468
 469         dwc_scan_descriptors(dw, dwc);
 470
 471         spin_lock_irqsave(&dwc->lock, flags);
 472
 473         /*
 474          * The descriptor currently at the head of the active list is
 475          * borked. Since we don't have any way to report errors, we'll
 476          * just have to scream loudly and try to carry on.
 477          */
 478         bad_desc = dwc_first_active(dwc);
 479         list_del_init(&bad_desc->desc_node);
 480         list_move(dwc->queue.next, dwc->active_list.prev);
 481
 482         /* Clear the error flag and try to restart the controller */
 483         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 484         if (!list_empty(&dwc->active_list))
 485                 dwc_dostart(dwc, dwc_first_active(dwc));
 486
 487         /*
 488          * WARN may seem harsh, but since this only happens
 489          * when someone submits a bad physical address in a
 490          * descriptor, we should consider ourselves lucky that the
 491          * controller flagged an error instead of scribbling over
 492          * random memory locations.
 493          */
 494         dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
 495                                        "  cookie: %d\n", bad_desc->txd.cookie);
 496         dwc_dump_lli(dwc, &bad_desc->lli);
 497         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 498                 dwc_dump_lli(dwc, &child->lli);
 499
 500         spin_unlock_irqrestore(&dwc->lock, flags);
 501
 502         /* Pretend the descriptor completed successfully */
 503         dwc_descriptor_complete(dwc, bad_desc, true);
 504 }
 505
 506 /* --------------------- Cyclic DMA API extensions -------------------- */
 507
 508 inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
 509 {
 510         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 511         return channel_readl(dwc, SAR);
 512 }
 513 EXPORT_SYMBOL(dw_dma_get_src_addr);
 514
 515 inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
 516 {
 517         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 518         return channel_readl(dwc, DAR);
 519 }
 520 EXPORT_SYMBOL(dw_dma_get_dst_addr);
 521
 522 /* called with dwc->lock held and all DMAC interrupts disabled */
 523 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 524                 u32 status_err, u32 status_xfer)
 525 {
 526         unsigned long flags;
 527
 528         if (dwc->mask) {
 529                 void (*callback)(void *param);
 530                 void *callback_param;
 531
 532                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
 533                                 channel_readl(dwc, LLP));
 534
 535                 callback = dwc->cdesc->period_callback;
 536                 callback_param = dwc->cdesc->period_callback_param;
 537
 538                 if (callback)
 539                         callback(callback_param);
 540         }
 541
 542         /*
 543          * Error and transfer complete are highly unlikely, and will most
 544          * likely be due to a configuration error by the user.
 545          */
 546         if (unlikely(status_err & dwc->mask) ||
 547                         unlikely(status_xfer & dwc->mask)) {
 548                 int i;
 549
 550                 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
 551                                 "interrupt, stopping DMA transfer\n",
 552                                 status_xfer ? "xfer" : "error");
 553
 554                 spin_lock_irqsave(&dwc->lock, flags);
 555
 556                 dwc_dump_chan_regs(dwc);
 557
 558                 dwc_chan_disable(dw, dwc);
 559
 560                 /* make sure DMA does not restart by loading a new list */
 561                 channel_writel(dwc, LLP, 0);
 562                 channel_writel(dwc, CTL_LO, 0);
 563                 channel_writel(dwc, CTL_HI, 0);
 564
 565                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
 566                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 567
 568                 for (i = 0; i < dwc->cdesc->periods; i++)
 569                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
 570
 571                 spin_unlock_irqrestore(&dwc->lock, flags);
 572         }
 573 }
 574
 575 /* ------------------------------------------------------------------------- */
 576
 577 static void dw_dma_tasklet(unsigned long data)
 578 {
 579         struct dw_dma *dw = (struct dw_dma *)data;
 580         struct dw_dma_chan *dwc;
 581         u32 status_xfer;
 582         u32 status_err;
 583         int i;
 584
 585         status_xfer = dma_readl(dw, RAW.XFER);
 586         status_err = dma_readl(dw, RAW.ERROR);
 587
 588         dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
 589
 590         for (i = 0; i < dw->dma.chancnt; i++) {
 591                 dwc = &dw->chan[i];
 592                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 593                         dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
 594                 else if (status_err & (1 << i))
 595                         dwc_handle_error(dw, dwc);
 596                 else if (status_xfer & (1 << i)) {
 597                         unsigned long flags;
 598
 599                         spin_lock_irqsave(&dwc->lock, flags);
 600                         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 601                                 if (dwc->tx_node_active != dwc->tx_list) {
 602                                         struct dw_desc *desc =
 603                                                 list_entry(dwc->tx_node_active,
 604                                                            struct dw_desc,
 605                                                            desc_node);
 606
 607                                         dma_writel(dw, CLEAR.XFER, dwc->mask);
 608
 609                                         /* move pointer to next descriptor */
 610                                         dwc->tx_node_active =
 611                                                 dwc->tx_node_active->next;
 612
 613                                         dwc_do_single_block(dwc, desc);
 614
 615                                         spin_unlock_irqrestore(&dwc->lock, flags);
 616                                         continue;
 617                                 } else {
 618                                         /* we are done here */
 619                                         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
 620                                 }
 621                         }
 622                         spin_unlock_irqrestore(&dwc->lock, flags);
 623
 624                         dwc_scan_descriptors(dw, dwc);
 625                 }
 626         }
 627
 628         /*
 629          * Re-enable interrupts.
 630          */
 631         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 632         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 633 }
 634
 635 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 636 {
 637         struct dw_dma *dw = dev_id;
 638         u32 status;
 639
 640         dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__,
 641                         dma_readl(dw, STATUS_INT));
 642
 643         /*
 644          * Just disable the interrupts. We'll turn them back on in the
 645          * softirq handler.
 646          */
 647         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 648         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 649
 650         status = dma_readl(dw, STATUS_INT);
 651         if (status) {
 652                 dev_err(dw->dma.dev,
 653                         "BUG: Unexpected interrupts pending: 0x%x\n",
 654                         status);
 655
 656                 /* Try to recover */
 657                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 658                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 659                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 660                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 661         }
 662
 663         tasklet_schedule(&dw->tasklet);
 664
 665         return IRQ_HANDLED;
 666 }
 667
 668 /*----------------------------------------------------------------------*/
 669
 670 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 671 {
 672         struct dw_desc          *desc = txd_to_dw_desc(tx);
 673         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
 674         dma_cookie_t            cookie;
 675         unsigned long           flags;
 676
 677         spin_lock_irqsave(&dwc->lock, flags);
 678         cookie = dma_cookie_assign(tx);
 679
 680         /*
 681          * REVISIT: We should attempt to chain as many descriptors as
 682          * possible, perhaps even appending to those already submitted
 683          * for DMA. But this is hard to do in a race-free manner.
 684          */
 685         if (list_empty(&dwc->active_list)) {
 686                 dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__,
 687                                 desc->txd.cookie);
 688                 list_add_tail(&desc->desc_node, &dwc->active_list);
 689                 dwc_dostart(dwc, dwc_first_active(dwc));
 690         } else {
 691                 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__,
 692                                 desc->txd.cookie);
 693
 694                 list_add_tail(&desc->desc_node, &dwc->queue);
 695         }
 696
 697         spin_unlock_irqrestore(&dwc->lock, flags);
 698
 699         return cookie;
 700 }
 701
 702 static struct dma_async_tx_descriptor *
 703 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 704                 size_t len, unsigned long flags)
 705 {
 706         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 707         struct dw_dma_slave     *dws = chan->private;
 708         struct dw_desc          *desc;
 709         struct dw_desc          *first;
 710         struct dw_desc          *prev;
 711         size_t                  xfer_count;
 712         size_t                  offset;
 713         unsigned int            src_width;
 714         unsigned int            dst_width;
 715         unsigned int            data_width;
 716         u32                     ctllo;
 717
 718         dev_vdbg(chan2dev(chan),
 719                         "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__,
 720                         (unsigned long long)dest, (unsigned long long)src,
 721                         len, flags);
 722
 723         if (unlikely(!len)) {
 724                 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
 725                 return NULL;
 726         }
 727
 728         data_width = min_t(unsigned int, dwc->dw->data_width[dwc_get_sms(dws)],
 729                                          dwc->dw->data_width[dwc_get_dms(dws)]);
 730
 731         src_width = dst_width = min_t(unsigned int, data_width,
 732                                       dwc_fast_fls(src | dest | len));
 733
 734         ctllo = DWC_DEFAULT_CTLLO(chan)
 735                         | DWC_CTLL_DST_WIDTH(dst_width)
 736                         | DWC_CTLL_SRC_WIDTH(src_width)
 737                         | DWC_CTLL_DST_INC
 738                         | DWC_CTLL_SRC_INC
 739                         | DWC_CTLL_FC_M2M;
 740         prev = first = NULL;
 741
 742         for (offset = 0; offset < len; offset += xfer_count << src_width) {
 743                 xfer_count = min_t(size_t, (len - offset) >> src_width,
 744                                            dwc->block_size);
 745
 746                 desc = dwc_desc_get(dwc);
 747                 if (!desc)
 748                         goto err_desc_get;
 749
 750                 desc->lli.sar = src + offset;
 751                 desc->lli.dar = dest + offset;
 752                 desc->lli.ctllo = ctllo;
 753                 desc->lli.ctlhi = xfer_count;
 754
 755                 if (!first) {
 756                         first = desc;
 757                 } else {
 758                         prev->lli.llp = desc->txd.phys;
 759                         dma_sync_single_for_device(chan2parent(chan),
 760                                         prev->txd.phys, sizeof(prev->lli),
 761                                         DMA_TO_DEVICE);
 762                         list_add_tail(&desc->desc_node,
 763                                         &first->tx_list);
 764                 }
 765                 prev = desc;
 766         }
 767
 768
 769         if (flags & DMA_PREP_INTERRUPT)
 770                 /* Trigger interrupt after last block */
 771                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 772
 773         prev->lli.llp = 0;
 774         dma_sync_single_for_device(chan2parent(chan),
 775                         prev->txd.phys, sizeof(prev->lli),
 776                         DMA_TO_DEVICE);
 777
 778         first->txd.flags = flags;
 779         first->len = len;
 780
 781         return &first->txd;
 782
 783 err_desc_get:
 784         dwc_desc_put(dwc, first);
 785         return NULL;
 786 }
 787
 788 static struct dma_async_tx_descriptor *
 789 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 790                 unsigned int sg_len, enum dma_transfer_direction direction,
 791                 unsigned long flags, void *context)
 792 {
 793         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 794         struct dw_dma_slave     *dws = chan->private;
 795         struct dma_slave_config *sconfig = &dwc->dma_sconfig;
 796         struct dw_desc          *prev;
 797         struct dw_desc          *first;
 798         u32                     ctllo;
 799         dma_addr_t              reg;
 800         unsigned int            reg_width;
 801         unsigned int            mem_width;
 802         unsigned int            data_width;
 803         unsigned int            i;
 804         struct scatterlist      *sg;
 805         size_t                  total_len = 0;
 806
 807         dev_vdbg(chan2dev(chan), "%s\n", __func__);
 808
 809         if (unlikely(!dws || !sg_len))
 810                 return NULL;
 811
 812         prev = first = NULL;
 813
 814         switch (direction) {
 815         case DMA_MEM_TO_DEV:
 816                 reg_width = __fls(sconfig->dst_addr_width);
 817                 reg = sconfig->dst_addr;
 818                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 819                                 | DWC_CTLL_DST_WIDTH(reg_width)
 820                                 | DWC_CTLL_DST_FIX
 821                                 | DWC_CTLL_SRC_INC);
 822
 823                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
 824                         DWC_CTLL_FC(DW_DMA_FC_D_M2P);
 825
 826                 data_width = dwc->dw->data_width[dwc_get_sms(dws)];
 827
 828                 for_each_sg(sgl, sg, sg_len, i) {
 829                         struct dw_desc  *desc;
 830                         u32             len, dlen, mem;
 831
 832                         mem = sg_dma_address(sg);
 833                         len = sg_dma_len(sg);
 834
 835                         mem_width = min_t(unsigned int,
 836                                           data_width, dwc_fast_fls(mem | len));
 837
 838 slave_sg_todev_fill_desc:
 839                         desc = dwc_desc_get(dwc);
 840                         if (!desc) {
 841                                 dev_err(chan2dev(chan),
 842                                         "not enough descriptors available\n");
 843                                 goto err_desc_get;
 844                         }
 845
 846                         desc->lli.sar = mem;
 847                         desc->lli.dar = reg;
 848                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
 849                         if ((len >> mem_width) > dwc->block_size) {
 850                                 dlen = dwc->block_size << mem_width;
 851                                 mem += dlen;
 852                                 len -= dlen;
 853                         } else {
 854                                 dlen = len;
 855                                 len = 0;
 856                         }
 857
 858                         desc->lli.ctlhi = dlen >> mem_width;
 859
 860                         if (!first) {
 861                                 first = desc;
 862                         } else {
 863                                 prev->lli.llp = desc->txd.phys;
 864                                 dma_sync_single_for_device(chan2parent(chan),
 865                                                 prev->txd.phys,
 866                                                 sizeof(prev->lli),
 867                                                 DMA_TO_DEVICE);
 868                                 list_add_tail(&desc->desc_node,
 869                                                 &first->tx_list);
 870                         }
 871                         prev = desc;
 872                         total_len += dlen;
 873
 874                         if (len)
 875                                 goto slave_sg_todev_fill_desc;
 876                 }
 877                 break;
 878         case DMA_DEV_TO_MEM:
 879                 reg_width = __fls(sconfig->src_addr_width);
 880                 reg = sconfig->src_addr;
 881                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 882                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 883                                 | DWC_CTLL_DST_INC
 884                                 | DWC_CTLL_SRC_FIX);
 885
 886                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
 887                         DWC_CTLL_FC(DW_DMA_FC_D_P2M);
 888
 889                 data_width = dwc->dw->data_width[dwc_get_dms(dws)];
 890
 891                 for_each_sg(sgl, sg, sg_len, i) {
 892                         struct dw_desc  *desc;
 893                         u32             len, dlen, mem;
 894
 895                         mem = sg_dma_address(sg);
 896                         len = sg_dma_len(sg);
 897
 898                         mem_width = min_t(unsigned int,
 899                                           data_width, dwc_fast_fls(mem | len));
 900
 901 slave_sg_fromdev_fill_desc:
 902                         desc = dwc_desc_get(dwc);
 903                         if (!desc) {
 904                                 dev_err(chan2dev(chan),
 905                                                 "not enough descriptors available\n");
 906                                 goto err_desc_get;
 907                         }
 908
 909                         desc->lli.sar = reg;
 910                         desc->lli.dar = mem;
 911                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
 912                         if ((len >> reg_width) > dwc->block_size) {
 913                                 dlen = dwc->block_size << reg_width;
 914                                 mem += dlen;
 915                                 len -= dlen;
 916                         } else {
 917                                 dlen = len;
 918                                 len = 0;
 919                         }
 920                         desc->lli.ctlhi = dlen >> reg_width;
 921
 922                         if (!first) {
 923                                 first = desc;
 924                         } else {
 925                                 prev->lli.llp = desc->txd.phys;
 926                                 dma_sync_single_for_device(chan2parent(chan),
 927                                                 prev->txd.phys,
 928                                                 sizeof(prev->lli),
 929                                                 DMA_TO_DEVICE);
 930                                 list_add_tail(&desc->desc_node,
 931                                                 &first->tx_list);
 932                         }
 933                         prev = desc;
 934                         total_len += dlen;
 935
 936                         if (len)
 937                                 goto slave_sg_fromdev_fill_desc;
 938                 }
 939                 break;
 940         default:
 941                 return NULL;
 942         }
 943
 944         if (flags & DMA_PREP_INTERRUPT)
 945                 /* Trigger interrupt after last block */
 946                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 947
 948         prev->lli.llp = 0;
 949         dma_sync_single_for_device(chan2parent(chan),
 950                         prev->txd.phys, sizeof(prev->lli),
 951                         DMA_TO_DEVICE);
 952
 953         first->len = total_len;
 954
 955         return &first->txd;
 956
 957 err_desc_get:
 958         dwc_desc_put(dwc, first);
 959         return NULL;
 960 }
 961
 962 /*
 963  * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
 964  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 965  *
 966  * NOTE: burst size 2 is not supported by controller.
 967  *
 968  * This can be done by finding least significant bit set: n & (n - 1)
 969  */
 970 static inline void convert_burst(u32 *maxburst)
 971 {
 972         if (*maxburst > 1)
 973                 *maxburst = fls(*maxburst) - 2;
 974         else
 975                 *maxburst = 0;
 976 }
 977
 978 static int
 979 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
 980 {
 981         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 982
 983         /* Check if it is chan is configured for slave transfers */
 984         if (!chan->private)
 985                 return -EINVAL;
 986
 987         memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
 988
 989         convert_burst(&dwc->dma_sconfig.src_maxburst);
 990         convert_burst(&dwc->dma_sconfig.dst_maxburst);
 991
 992         return 0;
 993 }
 994
 995 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 996                        unsigned long arg)
 997 {
 998         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 999         struct dw_dma           *dw = to_dw_dma(chan->device);
1000         struct dw_desc          *desc, *_desc;
1001         unsigned long           flags;
1002         u32                     cfglo;
1003         LIST_HEAD(list);
1004
1005         if (cmd == DMA_PAUSE) {
1006                 spin_lock_irqsave(&dwc->lock, flags);
1007
1008                 cfglo = channel_readl(dwc, CFG_LO);
1009                 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
1010                 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY))
1011                         cpu_relax();
1012
1013                 dwc->paused = true;
1014                 spin_unlock_irqrestore(&dwc->lock, flags);
1015         } else if (cmd == DMA_RESUME) {
1016                 if (!dwc->paused)
1017                         return 0;
1018
1019                 spin_lock_irqsave(&dwc->lock, flags);
1020
1021                 cfglo = channel_readl(dwc, CFG_LO);
1022                 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1023                 dwc->paused = false;
1024
1025                 spin_unlock_irqrestore(&dwc->lock, flags);
1026         } else if (cmd == DMA_TERMINATE_ALL) {
1027                 spin_lock_irqsave(&dwc->lock, flags);
1028
1029                 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1030
1031                 dwc_chan_disable(dw, dwc);
1032
1033                 dwc->paused = false;
1034
1035                 /* active_list entries will end up before queued entries */
1036                 list_splice_init(&dwc->queue, &list);
1037                 list_splice_init(&dwc->active_list, &list);
1038
1039                 spin_unlock_irqrestore(&dwc->lock, flags);
1040
1041                 /* Flush all pending and queued descriptors */
1042                 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1043                         dwc_descriptor_complete(dwc, desc, false);
1044         } else if (cmd == DMA_SLAVE_CONFIG) {
1045                 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1046         } else {
1047                 return -ENXIO;
1048         }
1049
1050         return 0;
1051 }
1052
1053 static enum dma_status
1054 dwc_tx_status(struct dma_chan *chan,
1055               dma_cookie_t cookie,
1056               struct dma_tx_state *txstate)
1057 {
1058         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1059         enum dma_status         ret;
1060
1061         ret = dma_cookie_status(chan, cookie, txstate);
1062         if (ret != DMA_SUCCESS) {
1063                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1064
1065                 ret = dma_cookie_status(chan, cookie, txstate);
1066         }
1067
1068         if (ret != DMA_SUCCESS)
1069                 dma_set_residue(txstate, dwc_first_active(dwc)->len);
1070
1071         if (dwc->paused)
1072                 return DMA_PAUSED;
1073
1074         return ret;
1075 }
1076
1077 static void dwc_issue_pending(struct dma_chan *chan)
1078 {
1079         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1080
1081         if (!list_empty(&dwc->queue))
1082                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1083 }
1084
1085 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1086 {
1087         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1088         struct dw_dma           *dw = to_dw_dma(chan->device);
1089         struct dw_desc          *desc;
1090         int                     i;
1091         unsigned long           flags;
1092
1093         dev_vdbg(chan2dev(chan), "%s\n", __func__);
1094
1095         /* ASSERT:  channel is idle */
1096         if (dma_readl(dw, CH_EN) & dwc->mask) {
1097                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1098                 return -EIO;
1099         }
1100
1101         dma_cookie_init(chan);
1102
1103         /*
1104          * NOTE: some controllers may have additional features that we
1105          * need to initialize here, like "scatter-gather" (which
1106          * doesn't mean what you think it means), and status writeback.
1107          */
1108
1109         spin_lock_irqsave(&dwc->lock, flags);
1110         i = dwc->descs_allocated;
1111         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1112                 spin_unlock_irqrestore(&dwc->lock, flags);
1113
1114                 desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL);
1115                 if (!desc) {
1116                         dev_info(chan2dev(chan),
1117                                 "only allocated %d descriptors\n", i);
1118                         spin_lock_irqsave(&dwc->lock, flags);
1119                         break;
1120                 }
1121
1122                 INIT_LIST_HEAD(&desc->tx_list);
1123                 dma_async_tx_descriptor_init(&desc->txd, chan);
1124                 desc->txd.tx_submit = dwc_tx_submit;
1125                 desc->txd.flags = DMA_CTRL_ACK;
1126                 desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli,
1127                                 sizeof(desc->lli), DMA_TO_DEVICE);
1128                 dwc_desc_put(dwc, desc);
1129
1130                 spin_lock_irqsave(&dwc->lock, flags);
1131                 i = ++dwc->descs_allocated;
1132         }
1133
1134         spin_unlock_irqrestore(&dwc->lock, flags);
1135
1136         dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1137
1138         return i;
1139 }
1140
1141 static void dwc_free_chan_resources(struct dma_chan *chan)
1142 {
1143         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1144         struct dw_dma           *dw = to_dw_dma(chan->device);
1145         struct dw_desc          *desc, *_desc;
1146         unsigned long           flags;
1147         LIST_HEAD(list);
1148
1149         dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1150                         dwc->descs_allocated);
1151
1152         /* ASSERT:  channel is idle */
1153         BUG_ON(!list_empty(&dwc->active_list));
1154         BUG_ON(!list_empty(&dwc->queue));
1155         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1156
1157         spin_lock_irqsave(&dwc->lock, flags);
1158         list_splice_init(&dwc->free_list, &list);
1159         dwc->descs_allocated = 0;
1160         dwc->initialized = false;
1161
1162         /* Disable interrupts */
1163         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1164         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1165
1166         spin_unlock_irqrestore(&dwc->lock, flags);
1167
1168         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1169                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1170                 dma_unmap_single(chan2parent(chan), desc->txd.phys,
1171                                 sizeof(desc->lli), DMA_TO_DEVICE);
1172                 kfree(desc);
1173         }
1174
1175         dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1176 }
1177
1178 bool dw_dma_generic_filter(struct dma_chan *chan, void *param)
1179 {
1180         struct dw_dma *dw = to_dw_dma(chan->device);
1181         static struct dw_dma *last_dw;
1182         static char *last_bus_id;
1183         int i = -1;
1184
1185         /*
1186          * dmaengine framework calls this routine for all channels of all dma
1187          * controller, until true is returned. If 'param' bus_id is not
1188          * registered with a dma controller (dw), then there is no need of
1189          * running below function for all channels of dw.
1190          *
1191          * This block of code does this by saving the parameters of last
1192          * failure. If dw and param are same, i.e. trying on same dw with
1193          * different channel, return false.
1194          */
1195         if ((last_dw == dw) && (last_bus_id == param))
1196                 return false;
1197         /*
1198          * Return true:
1199          * - If dw_dma's platform data is not filled with slave info, then all
1200          *   dma controllers are fine for transfer.
1201          * - Or if param is NULL
1202          */
1203         if (!dw->sd || !param)
1204                 return true;
1205
1206         while (++i < dw->sd_count) {
1207                 if (!strcmp(dw->sd[i].bus_id, param)) {
1208                         chan->private = &dw->sd[i];
1209                         last_dw = NULL;
1210                         last_bus_id = NULL;
1211
1212                         return true;
1213                 }
1214         }
1215
1216         last_dw = dw;
1217         last_bus_id = param;
1218         return false;
1219 }
1220 EXPORT_SYMBOL(dw_dma_generic_filter);
1221
1222 /* --------------------- Cyclic DMA API extensions -------------------- */
1223
1224 /**
1225  * dw_dma_cyclic_start - start the cyclic DMA transfer
1226  * @chan: the DMA channel to start
1227  *
1228  * Must be called with soft interrupts disabled. Returns zero on success or
1229  * -errno on failure.
1230  */
1231 int dw_dma_cyclic_start(struct dma_chan *chan)
1232 {
1233         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1234         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1235         unsigned long           flags;
1236
1237         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1238                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1239                 return -ENODEV;
1240         }
1241
1242         spin_lock_irqsave(&dwc->lock, flags);
1243
1244         /* assert channel is idle */
1245         if (dma_readl(dw, CH_EN) & dwc->mask) {
1246                 dev_err(chan2dev(&dwc->chan),
1247                         "BUG: Attempted to start non-idle channel\n");
1248                 dwc_dump_chan_regs(dwc);
1249                 spin_unlock_irqrestore(&dwc->lock, flags);
1250                 return -EBUSY;
1251         }
1252
1253         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1254         dma_writel(dw, CLEAR.XFER, dwc->mask);
1255
1256         /* setup DMAC channel registers */
1257         channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1258         channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1259         channel_writel(dwc, CTL_HI, 0);
1260
1261         channel_set_bit(dw, CH_EN, dwc->mask);
1262
1263         spin_unlock_irqrestore(&dwc->lock, flags);
1264
1265         return 0;
1266 }
1267 EXPORT_SYMBOL(dw_dma_cyclic_start);
1268
1269 /**
1270  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1271  * @chan: the DMA channel to stop
1272  *
1273  * Must be called with soft interrupts disabled.
1274  */
1275 void dw_dma_cyclic_stop(struct dma_chan *chan)
1276 {
1277         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1278         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1279         unsigned long           flags;
1280
1281         spin_lock_irqsave(&dwc->lock, flags);
1282
1283         dwc_chan_disable(dw, dwc);
1284
1285         spin_unlock_irqrestore(&dwc->lock, flags);
1286 }
1287 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1288
1289 /**
1290  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1291  * @chan: the DMA channel to prepare
1292  * @buf_addr: physical DMA address where the buffer starts
1293  * @buf_len: total number of bytes for the entire buffer
1294  * @period_len: number of bytes for each period
1295  * @direction: transfer direction, to or from device
1296  *
1297  * Must be called before trying to start the transfer. Returns a valid struct
1298  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1299  */
1300 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1301                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1302                 enum dma_transfer_direction direction)
1303 {
1304         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1305         struct dma_slave_config         *sconfig = &dwc->dma_sconfig;
1306         struct dw_cyclic_desc           *cdesc;
1307         struct dw_cyclic_desc           *retval = NULL;
1308         struct dw_desc                  *desc;
1309         struct dw_desc                  *last = NULL;
1310         unsigned long                   was_cyclic;
1311         unsigned int                    reg_width;
1312         unsigned int                    periods;
1313         unsigned int                    i;
1314         unsigned long                   flags;
1315
1316         spin_lock_irqsave(&dwc->lock, flags);
1317         if (dwc->nollp) {
1318                 spin_unlock_irqrestore(&dwc->lock, flags);
1319                 dev_dbg(chan2dev(&dwc->chan),
1320                                 "channel doesn't support LLP transfers\n");
1321                 return ERR_PTR(-EINVAL);
1322         }
1323
1324         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1325                 spin_unlock_irqrestore(&dwc->lock, flags);
1326                 dev_dbg(chan2dev(&dwc->chan),
1327                                 "queue and/or active list are not empty\n");
1328                 return ERR_PTR(-EBUSY);
1329         }
1330
1331         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1332         spin_unlock_irqrestore(&dwc->lock, flags);
1333         if (was_cyclic) {
1334                 dev_dbg(chan2dev(&dwc->chan),
1335                                 "channel already prepared for cyclic DMA\n");
1336                 return ERR_PTR(-EBUSY);
1337         }
1338
1339         retval = ERR_PTR(-EINVAL);
1340
1341         if (direction == DMA_MEM_TO_DEV)
1342                 reg_width = __ffs(sconfig->dst_addr_width);
1343         else
1344                 reg_width = __ffs(sconfig->src_addr_width);
1345
1346         periods = buf_len / period_len;
1347
1348         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1349         if (period_len > (dwc->block_size << reg_width))
1350                 goto out_err;
1351         if (unlikely(period_len & ((1 << reg_width) - 1)))
1352                 goto out_err;
1353         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1354                 goto out_err;
1355         if (unlikely(!(direction & (DMA_MEM_TO_DEV | DMA_DEV_TO_MEM))))
1356                 goto out_err;
1357
1358         retval = ERR_PTR(-ENOMEM);
1359
1360         if (periods > NR_DESCS_PER_CHANNEL)
1361                 goto out_err;
1362
1363         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1364         if (!cdesc)
1365                 goto out_err;
1366
1367         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1368         if (!cdesc->desc)
1369                 goto out_err_alloc;
1370
1371         for (i = 0; i < periods; i++) {
1372                 desc = dwc_desc_get(dwc);
1373                 if (!desc)
1374                         goto out_err_desc_get;
1375
1376                 switch (direction) {
1377                 case DMA_MEM_TO_DEV:
1378                         desc->lli.dar = sconfig->dst_addr;
1379                         desc->lli.sar = buf_addr + (period_len * i);
1380                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1381                                         | DWC_CTLL_DST_WIDTH(reg_width)
1382                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1383                                         | DWC_CTLL_DST_FIX
1384                                         | DWC_CTLL_SRC_INC
1385                                         | DWC_CTLL_INT_EN);
1386
1387                         desc->lli.ctllo |= sconfig->device_fc ?
1388                                 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1389                                 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1390
1391                         break;
1392                 case DMA_DEV_TO_MEM:
1393                         desc->lli.dar = buf_addr + (period_len * i);
1394                         desc->lli.sar = sconfig->src_addr;
1395                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1396                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1397                                         | DWC_CTLL_DST_WIDTH(reg_width)
1398                                         | DWC_CTLL_DST_INC
1399                                         | DWC_CTLL_SRC_FIX
1400                                         | DWC_CTLL_INT_EN);
1401
1402                         desc->lli.ctllo |= sconfig->device_fc ?
1403                                 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1404                                 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1405
1406                         break;
1407                 default:
1408                         break;
1409                 }
1410
1411                 desc->lli.ctlhi = (period_len >> reg_width);
1412                 cdesc->desc[i] = desc;
1413
1414                 if (last) {
1415                         last->lli.llp = desc->txd.phys;
1416                         dma_sync_single_for_device(chan2parent(chan),
1417                                         last->txd.phys, sizeof(last->lli),
1418                                         DMA_TO_DEVICE);
1419                 }
1420
1421                 last = desc;
1422         }
1423
1424         /* lets make a cyclic list */
1425         last->lli.llp = cdesc->desc[0]->txd.phys;
1426         dma_sync_single_for_device(chan2parent(chan), last->txd.phys,
1427                         sizeof(last->lli), DMA_TO_DEVICE);
1428
1429         dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu "
1430                         "period %zu periods %d\n", (unsigned long long)buf_addr,
1431                         buf_len, period_len, periods);
1432
1433         cdesc->periods = periods;
1434         dwc->cdesc = cdesc;
1435
1436         return cdesc;
1437
1438 out_err_desc_get:
1439         while (i--)
1440                 dwc_desc_put(dwc, cdesc->desc[i]);
1441 out_err_alloc:
1442         kfree(cdesc);
1443 out_err:
1444         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1445         return (struct dw_cyclic_desc *)retval;
1446 }
1447 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1448
1449 /**
1450  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1451  * @chan: the DMA channel to free
1452  */
1453 void dw_dma_cyclic_free(struct dma_chan *chan)
1454 {
1455         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1456         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1457         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1458         int                     i;
1459         unsigned long           flags;
1460
1461         dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1462
1463         if (!cdesc)
1464                 return;
1465
1466         spin_lock_irqsave(&dwc->lock, flags);
1467
1468         dwc_chan_disable(dw, dwc);
1469
1470         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1471         dma_writel(dw, CLEAR.XFER, dwc->mask);
1472
1473         spin_unlock_irqrestore(&dwc->lock, flags);
1474
1475         for (i = 0; i < cdesc->periods; i++)
1476                 dwc_desc_put(dwc, cdesc->desc[i]);
1477
1478         kfree(cdesc->desc);
1479         kfree(cdesc);
1480
1481         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1482 }
1483 EXPORT_SYMBOL(dw_dma_cyclic_free);
1484
1485 /*----------------------------------------------------------------------*/
1486
1487 static void dw_dma_off(struct dw_dma *dw)
1488 {
1489         int i;
1490
1491         dma_writel(dw, CFG, 0);
1492
1493         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1494         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1495         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1496         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1497
1498         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1499                 cpu_relax();
1500
1501         for (i = 0; i < dw->dma.chancnt; i++)
1502                 dw->chan[i].initialized = false;
1503 }
1504
1505 #ifdef CONFIG_OF
1506 static struct dw_dma_platform_data *
1507 dw_dma_parse_dt(struct platform_device *pdev)
1508 {
1509         struct device_node *sn, *cn, *np = pdev->dev.of_node;
1510         struct dw_dma_platform_data *pdata;
1511         struct dw_dma_slave *sd;
1512         u32 tmp, arr[4];
1513
1514         if (!np) {
1515                 dev_err(&pdev->dev, "Missing DT data\n");
1516                 return NULL;
1517         }
1518
1519         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1520         if (!pdata)
1521                 return NULL;
1522
1523         if (of_property_read_u32(np, "nr_channels", &pdata->nr_channels))
1524                 return NULL;
1525
1526         if (of_property_read_bool(np, "is_private"))
1527                 pdata->is_private = true;
1528
1529         if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
1530                 pdata->chan_allocation_order = (unsigned char)tmp;
1531
1532         if (!of_property_read_u32(np, "chan_priority", &tmp))
1533                 pdata->chan_priority = tmp;
1534
1535         if (!of_property_read_u32(np, "block_size", &tmp))
1536                 pdata->block_size = tmp;
1537
1538         if (!of_property_read_u32(np, "nr_masters", &tmp)) {
1539                 if (tmp > 4)
1540                         return NULL;
1541
1542                 pdata->nr_masters = tmp;
1543         }
1544
1545         if (!of_property_read_u32_array(np, "data_width", arr,
1546                                 pdata->nr_masters))
1547                 for (tmp = 0; tmp < pdata->nr_masters; tmp++)
1548                         pdata->data_width[tmp] = arr[tmp];
1549
1550         /* parse slave data */
1551         sn = of_find_node_by_name(np, "slave_info");
1552         if (!sn)
1553                 return pdata;
1554
1555         /* calculate number of slaves */
1556         tmp = of_get_child_count(sn);
1557         if (!tmp)
1558                 return NULL;
1559
1560         sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * tmp, GFP_KERNEL);
1561         if (!sd)
1562                 return NULL;
1563
1564         pdata->sd = sd;
1565         pdata->sd_count = tmp;
1566
1567         for_each_child_of_node(sn, cn) {
1568                 sd->dma_dev = &pdev->dev;
1569                 of_property_read_string(cn, "bus_id", &sd->bus_id);
1570                 of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi);
1571                 of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo);
1572                 if (!of_property_read_u32(cn, "src_master", &tmp))
1573                         sd->src_master = tmp;
1574
1575                 if (!of_property_read_u32(cn, "dst_master", &tmp))
1576                         sd->dst_master = tmp;
1577                 sd++;
1578         }
1579
1580         return pdata;
1581 }
1582 #else
1583 static inline struct dw_dma_platform_data *
1584 dw_dma_parse_dt(struct platform_device *pdev)
1585 {
1586         return NULL;
1587 }
1588 #endif
1589
1590 static int dw_probe(struct platform_device *pdev)
1591 {
1592         struct dw_dma_platform_data *pdata;
1593         struct resource         *io;
1594         struct dw_dma           *dw;
1595         size_t                  size;
1596         void __iomem            *regs;
1597         bool                    autocfg;
1598         unsigned int            dw_params;
1599         unsigned int            nr_channels;
1600         unsigned int            max_blk_size = 0;
1601         int                     irq;
1602         int                     err;
1603         int                     i;
1604
1605         pdata = dev_get_platdata(&pdev->dev);
1606         if (!pdata)
1607                 pdata = dw_dma_parse_dt(pdev);
1608
1609         if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1610                 return -EINVAL;
1611
1612         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1613         if (!io)
1614                 return -EINVAL;
1615
1616         irq = platform_get_irq(pdev, 0);
1617         if (irq < 0)
1618                 return irq;
1619
1620         regs = devm_request_and_ioremap(&pdev->dev, io);
1621         if (!regs)
1622                 return -EBUSY;
1623
1624         dw_params = dma_read_byaddr(regs, DW_PARAMS);
1625         autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1626
1627         if (autocfg)
1628                 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1629         else
1630                 nr_channels = pdata->nr_channels;
1631
1632         size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
1633         dw = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1634         if (!dw)
1635                 return -ENOMEM;
1636
1637         dw->clk = devm_clk_get(&pdev->dev, "hclk");
1638         if (IS_ERR(dw->clk))
1639                 return PTR_ERR(dw->clk);
1640         clk_prepare_enable(dw->clk);
1641
1642         dw->regs = regs;
1643         dw->sd = pdata->sd;
1644         dw->sd_count = pdata->sd_count;
1645
1646         /* get hardware configuration parameters */
1647         if (autocfg) {
1648                 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1649
1650                 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1651                 for (i = 0; i < dw->nr_masters; i++) {
1652                         dw->data_width[i] =
1653                                 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1654                 }
1655         } else {
1656                 dw->nr_masters = pdata->nr_masters;
1657                 memcpy(dw->data_width, pdata->data_width, 4);
1658         }
1659
1660         /* Calculate all channel mask before DMA setup */
1661         dw->all_chan_mask = (1 << nr_channels) - 1;
1662
1663         /* force dma off, just in case */
1664         dw_dma_off(dw);
1665
1666         /* disable BLOCK interrupts as well */
1667         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1668
1669         err = devm_request_irq(&pdev->dev, irq, dw_dma_interrupt, 0,
1670                                "dw_dmac", dw);
1671         if (err)
1672                 return err;
1673
1674         platform_set_drvdata(pdev, dw);
1675
1676         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1677
1678         INIT_LIST_HEAD(&dw->dma.channels);
1679         for (i = 0; i < nr_channels; i++) {
1680                 struct dw_dma_chan      *dwc = &dw->chan[i];
1681                 int                     r = nr_channels - i - 1;
1682
1683                 dwc->chan.device = &dw->dma;
1684                 dma_cookie_init(&dwc->chan);
1685                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1686                         list_add_tail(&dwc->chan.device_node,
1687                                         &dw->dma.channels);
1688                 else
1689                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1690
1691                 /* 7 is highest priority & 0 is lowest. */
1692                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1693                         dwc->priority = r;
1694                 else
1695                         dwc->priority = i;
1696
1697                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1698                 spin_lock_init(&dwc->lock);
1699                 dwc->mask = 1 << i;
1700
1701                 INIT_LIST_HEAD(&dwc->active_list);
1702                 INIT_LIST_HEAD(&dwc->queue);
1703                 INIT_LIST_HEAD(&dwc->free_list);
1704
1705                 channel_clear_bit(dw, CH_EN, dwc->mask);
1706
1707                 dwc->dw = dw;
1708
1709                 /* hardware configuration */
1710                 if (autocfg) {
1711                         unsigned int dwc_params;
1712
1713                         dwc_params = dma_read_byaddr(regs + r * sizeof(u32),
1714                                                      DWC_PARAMS);
1715
1716                         /* Decode maximum block size for given channel. The
1717                          * stored 4 bit value represents blocks from 0x00 for 3
1718                          * up to 0x0a for 4095. */
1719                         dwc->block_size =
1720                                 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1721                         dwc->nollp =
1722                                 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1723                 } else {
1724                         dwc->block_size = pdata->block_size;
1725
1726                         /* Check if channel supports multi block transfer */
1727                         channel_writel(dwc, LLP, 0xfffffffc);
1728                         dwc->nollp =
1729                                 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1730                         channel_writel(dwc, LLP, 0);
1731                 }
1732         }
1733
1734         /* Clear all interrupts on all channels. */
1735         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1736         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1737         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1738         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1739         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1740
1741         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1742         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1743         if (pdata->is_private)
1744                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1745         dw->dma.dev = &pdev->dev;
1746         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1747         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1748
1749         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1750
1751         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1752         dw->dma.device_control = dwc_control;
1753
1754         dw->dma.device_tx_status = dwc_tx_status;
1755         dw->dma.device_issue_pending = dwc_issue_pending;
1756
1757         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1758
1759         dev_info(&pdev->dev, "DesignWare DMA Controller, %d channels\n",
1760                  nr_channels);
1761
1762         dma_async_device_register(&dw->dma);
1763
1764         return 0;
1765 }
1766
1767 static int __devexit dw_remove(struct platform_device *pdev)
1768 {
1769         struct dw_dma           *dw = platform_get_drvdata(pdev);
1770         struct dw_dma_chan      *dwc, *_dwc;
1771
1772         dw_dma_off(dw);
1773         dma_async_device_unregister(&dw->dma);
1774
1775         tasklet_kill(&dw->tasklet);
1776
1777         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1778                         chan.device_node) {
1779                 list_del(&dwc->chan.device_node);
1780                 channel_clear_bit(dw, CH_EN, dwc->mask);
1781         }
1782
1783         return 0;
1784 }
1785
1786 static void dw_shutdown(struct platform_device *pdev)
1787 {
1788         struct dw_dma   *dw = platform_get_drvdata(pdev);
1789
1790         dw_dma_off(dw);
1791         clk_disable_unprepare(dw->clk);
1792 }
1793
1794 static int dw_suspend_noirq(struct device *dev)
1795 {
1796         struct platform_device *pdev = to_platform_device(dev);
1797         struct dw_dma   *dw = platform_get_drvdata(pdev);
1798
1799         dw_dma_off(dw);
1800         clk_disable_unprepare(dw->clk);
1801
1802         return 0;
1803 }
1804
1805 static int dw_resume_noirq(struct device *dev)
1806 {
1807         struct platform_device *pdev = to_platform_device(dev);
1808         struct dw_dma   *dw = platform_get_drvdata(pdev);
1809
1810         clk_prepare_enable(dw->clk);
1811         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1812
1813         return 0;
1814 }
1815
1816 static const struct dev_pm_ops dw_dev_pm_ops = {
1817         .suspend_noirq = dw_suspend_noirq,
1818         .resume_noirq = dw_resume_noirq,
1819         .freeze_noirq = dw_suspend_noirq,
1820         .thaw_noirq = dw_resume_noirq,
1821         .restore_noirq = dw_resume_noirq,
1822         .poweroff_noirq = dw_suspend_noirq,
1823 };
1824
1825 #ifdef CONFIG_OF
1826 static const struct of_device_id dw_dma_id_table[] = {
1827         { .compatible = "snps,dma-spear1340" },
1828         {}
1829 };
1830 MODULE_DEVICE_TABLE(of, dw_dma_id_table);
1831 #endif
1832
1833 static struct platform_driver dw_driver = {
1834         .remove         = dw_remove,
1835         .shutdown       = dw_shutdown,
1836         .driver = {
1837                 .name   = "dw_dmac",
1838                 .pm     = &dw_dev_pm_ops,
1839                 .of_match_table = of_match_ptr(dw_dma_id_table),
1840         },
1841 };
1842
1843 static int __init dw_init(void)
1844 {
1845         return platform_driver_probe(&dw_driver, dw_probe);
1846 }
1847 subsys_initcall(dw_init);
1848
1849 static void __exit dw_exit(void)
1850 {
1851         platform_driver_unregister(&dw_driver);
1852 }
1853 module_exit(dw_exit);
1854
1855 MODULE_LICENSE("GPL v2");
1856 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1857 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1858 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");