2 * drivers/dma/imx-sdma.c
4 * This file contains a driver for the Freescale Smart DMA engine
6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8 * Based on code from Freescale:
10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/types.h>
23 #include <linux/bitops.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/wait.h>
28 #include <linux/sched.h>
29 #include <linux/semaphore.h>
30 #include <linux/spinlock.h>
31 #include <linux/device.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/firmware.h>
34 #include <linux/slab.h>
35 #include <linux/platform_device.h>
36 #include <linux/dmaengine.h>
38 #include <linux/of_device.h>
39 #include <linux/module.h>
42 #include <mach/sdma.h>
44 #include <mach/hardware.h>
46 #include "dmaengine.h"
49 #define SDMA_H_C0PTR 0x000
50 #define SDMA_H_INTR 0x004
51 #define SDMA_H_STATSTOP 0x008
52 #define SDMA_H_START 0x00c
53 #define SDMA_H_EVTOVR 0x010
54 #define SDMA_H_DSPOVR 0x014
55 #define SDMA_H_HOSTOVR 0x018
56 #define SDMA_H_EVTPEND 0x01c
57 #define SDMA_H_DSPENBL 0x020
58 #define SDMA_H_RESET 0x024
59 #define SDMA_H_EVTERR 0x028
60 #define SDMA_H_INTRMSK 0x02c
61 #define SDMA_H_PSW 0x030
62 #define SDMA_H_EVTERRDBG 0x034
63 #define SDMA_H_CONFIG 0x038
64 #define SDMA_ONCE_ENB 0x040
65 #define SDMA_ONCE_DATA 0x044
66 #define SDMA_ONCE_INSTR 0x048
67 #define SDMA_ONCE_STAT 0x04c
68 #define SDMA_ONCE_CMD 0x050
69 #define SDMA_EVT_MIRROR 0x054
70 #define SDMA_ILLINSTADDR 0x058
71 #define SDMA_CHN0ADDR 0x05c
72 #define SDMA_ONCE_RTB 0x060
73 #define SDMA_XTRIG_CONF1 0x070
74 #define SDMA_XTRIG_CONF2 0x074
75 #define SDMA_CHNENBL0_IMX35 0x200
76 #define SDMA_CHNENBL0_IMX31 0x080
77 #define SDMA_CHNPRI_0 0x100
80 * Buffer descriptor status values.
91 * Data Node descriptor status values.
93 #define DND_END_OF_FRAME 0x80
94 #define DND_END_OF_XFER 0x40
96 #define DND_UNUSED 0x01
99 * IPCV2 descriptor status values.
101 #define BD_IPCV2_END_OF_FRAME 0x40
103 #define IPCV2_MAX_NODES 50
105 * Error bit set in the CCB status field by the SDMA,
106 * in setbd routine, in case of a transfer error
108 #define DATA_ERROR 0x10000000
111 * Buffer descriptor commands.
116 #define C0_SETCTX 0x07
117 #define C0_GETCTX 0x03
118 #define C0_SETDM 0x01
119 #define C0_SETPM 0x04
120 #define C0_GETDM 0x02
121 #define C0_GETPM 0x08
123 * Change endianness indicator in the BD command field
125 #define CHANGE_ENDIANNESS 0x80
128 * Mode/Count of data node descriptors - IPCv2
130 struct sdma_mode_count {
131 u32 count : 16; /* size of the buffer pointed by this BD */
132 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
133 u32 command : 8; /* command mostlky used for channel 0 */
139 struct sdma_buffer_descriptor {
140 struct sdma_mode_count mode;
141 u32 buffer_addr; /* address of the buffer described */
142 u32 ext_buffer_addr; /* extended buffer address */
143 } __attribute__ ((packed));
146 * struct sdma_channel_control - Channel control Block
148 * @current_bd_ptr current buffer descriptor processed
149 * @base_bd_ptr first element of buffer descriptor array
150 * @unused padding. The SDMA engine expects an array of 128 byte
153 struct sdma_channel_control {
157 } __attribute__ ((packed));
160 * struct sdma_state_registers - SDMA context for a channel
162 * @pc: program counter
163 * @t: test bit: status of arithmetic & test instruction
164 * @rpc: return program counter
165 * @sf: source fault while loading data
166 * @spc: loop start program counter
167 * @df: destination fault while storing data
168 * @epc: loop end program counter
171 struct sdma_state_registers {
183 } __attribute__ ((packed));
186 * struct sdma_context_data - sdma context specific to a channel
188 * @channel_state: channel state bits
189 * @gReg: general registers
190 * @mda: burst dma destination address register
191 * @msa: burst dma source address register
192 * @ms: burst dma status register
193 * @md: burst dma data register
194 * @pda: peripheral dma destination address register
195 * @psa: peripheral dma source address register
196 * @ps: peripheral dma status register
197 * @pd: peripheral dma data register
198 * @ca: CRC polynomial register
199 * @cs: CRC accumulator register
200 * @dda: dedicated core destination address register
201 * @dsa: dedicated core source address register
202 * @ds: dedicated core status register
203 * @dd: dedicated core data register
205 struct sdma_context_data {
206 struct sdma_state_registers channel_state;
230 } __attribute__ ((packed));
232 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
237 * struct sdma_channel - housekeeping for a SDMA channel
239 * @sdma pointer to the SDMA engine for this channel
240 * @channel the channel number, matches dmaengine chan_id + 1
241 * @direction transfer type. Needed for setting SDMA script
242 * @peripheral_type Peripheral type. Needed for setting SDMA script
243 * @event_id0 aka dma request line
244 * @event_id1 for channels that use 2 events
245 * @word_size peripheral access size
246 * @buf_tail ID of the buffer that was processed
247 * @done channel completion
248 * @num_bd max NUM_BD. number of descriptors currently handling
250 struct sdma_channel {
251 struct sdma_engine *sdma;
252 unsigned int channel;
253 enum dma_transfer_direction direction;
254 enum sdma_peripheral_type peripheral_type;
255 unsigned int event_id0;
256 unsigned int event_id1;
257 enum dma_slave_buswidth word_size;
258 unsigned int buf_tail;
259 struct completion done;
261 struct sdma_buffer_descriptor *bd;
263 unsigned int pc_from_device, pc_to_device;
265 dma_addr_t per_address;
266 unsigned long event_mask[2];
267 unsigned long watermark_level;
268 u32 shp_addr, per_addr;
269 struct dma_chan chan;
271 struct dma_async_tx_descriptor desc;
272 enum dma_status status;
273 unsigned int chn_count;
274 unsigned int chn_real_count;
277 #define IMX_DMA_SG_LOOP BIT(0)
279 #define MAX_DMA_CHANNELS 32
280 #define MXC_SDMA_DEFAULT_PRIORITY 1
281 #define MXC_SDMA_MIN_PRIORITY 1
282 #define MXC_SDMA_MAX_PRIORITY 7
284 #define SDMA_FIRMWARE_MAGIC 0x414d4453
287 * struct sdma_firmware_header - Layout of the firmware image
290 * @version_major increased whenever layout of struct sdma_script_start_addrs
292 * @version_minor firmware minor version (for binary compatible changes)
293 * @script_addrs_start offset of struct sdma_script_start_addrs in this image
294 * @num_script_addrs Number of script addresses in this image
295 * @ram_code_start offset of SDMA ram image in this firmware image
296 * @ram_code_size size of SDMA ram image
297 * @script_addrs Stores the start address of the SDMA scripts
298 * (in SDMA memory space)
300 struct sdma_firmware_header {
304 u32 script_addrs_start;
305 u32 num_script_addrs;
311 IMX31_SDMA, /* runs on i.mx31 */
312 IMX35_SDMA, /* runs on i.mx35 and later */
317 struct device_dma_parameters dma_parms;
318 struct sdma_channel channel[MAX_DMA_CHANNELS];
319 struct sdma_channel_control *channel_control;
321 enum sdma_devtype devtype;
322 unsigned int num_events;
323 struct sdma_context_data *context;
324 dma_addr_t context_phys;
325 struct dma_device dma_device;
327 struct mutex channel_0_lock;
328 struct sdma_script_start_addrs *script_addrs;
331 static struct platform_device_id sdma_devtypes[] = {
333 .name = "imx31-sdma",
334 .driver_data = IMX31_SDMA,
336 .name = "imx35-sdma",
337 .driver_data = IMX35_SDMA,
342 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
344 static const struct of_device_id sdma_dt_ids[] = {
345 { .compatible = "fsl,imx31-sdma", .data = &sdma_devtypes[IMX31_SDMA], },
346 { .compatible = "fsl,imx35-sdma", .data = &sdma_devtypes[IMX35_SDMA], },
349 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
351 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
352 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
353 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
354 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
356 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
358 u32 chnenbl0 = (sdma->devtype == IMX31_SDMA ? SDMA_CHNENBL0_IMX31 :
359 SDMA_CHNENBL0_IMX35);
360 return chnenbl0 + event * 4;
363 static int sdma_config_ownership(struct sdma_channel *sdmac,
364 bool event_override, bool mcu_override, bool dsp_override)
366 struct sdma_engine *sdma = sdmac->sdma;
367 int channel = sdmac->channel;
368 unsigned long evt, mcu, dsp;
370 if (event_override && mcu_override && dsp_override)
373 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
374 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
375 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
378 __clear_bit(channel, &dsp);
380 __set_bit(channel, &dsp);
383 __clear_bit(channel, &evt);
385 __set_bit(channel, &evt);
388 __clear_bit(channel, &mcu);
390 __set_bit(channel, &mcu);
392 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
393 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
394 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
399 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
401 writel(BIT(channel), sdma->regs + SDMA_H_START);
405 * sdma_run_channel - run a channel and wait till it's done
407 static int sdma_run_channel(struct sdma_channel *sdmac)
409 struct sdma_engine *sdma = sdmac->sdma;
410 int channel = sdmac->channel;
413 init_completion(&sdmac->done);
415 sdma_enable_channel(sdma, channel);
417 ret = wait_for_completion_timeout(&sdmac->done, HZ);
419 return ret ? 0 : -ETIMEDOUT;
422 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
425 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
430 mutex_lock(&sdma->channel_0_lock);
432 buf_virt = dma_alloc_coherent(NULL,
434 &buf_phys, GFP_KERNEL);
440 bd0->mode.command = C0_SETPM;
441 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
442 bd0->mode.count = size / 2;
443 bd0->buffer_addr = buf_phys;
444 bd0->ext_buffer_addr = address;
446 memcpy(buf_virt, buf, size);
448 ret = sdma_run_channel(&sdma->channel[0]);
450 dma_free_coherent(NULL, size, buf_virt, buf_phys);
453 mutex_unlock(&sdma->channel_0_lock);
458 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
460 struct sdma_engine *sdma = sdmac->sdma;
461 int channel = sdmac->channel;
463 u32 chnenbl = chnenbl_ofs(sdma, event);
465 val = readl_relaxed(sdma->regs + chnenbl);
466 __set_bit(channel, &val);
467 writel_relaxed(val, sdma->regs + chnenbl);
470 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
472 struct sdma_engine *sdma = sdmac->sdma;
473 int channel = sdmac->channel;
474 u32 chnenbl = chnenbl_ofs(sdma, event);
477 val = readl_relaxed(sdma->regs + chnenbl);
478 __clear_bit(channel, &val);
479 writel_relaxed(val, sdma->regs + chnenbl);
482 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
484 struct sdma_buffer_descriptor *bd;
487 * loop mode. Iterate over descriptors, re-setup them and
488 * call callback function.
491 bd = &sdmac->bd[sdmac->buf_tail];
493 if (bd->mode.status & BD_DONE)
496 if (bd->mode.status & BD_RROR)
497 sdmac->status = DMA_ERROR;
499 sdmac->status = DMA_IN_PROGRESS;
501 bd->mode.status |= BD_DONE;
503 sdmac->buf_tail %= sdmac->num_bd;
505 if (sdmac->desc.callback)
506 sdmac->desc.callback(sdmac->desc.callback_param);
510 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
512 struct sdma_buffer_descriptor *bd;
515 sdmac->chn_real_count = 0;
517 * non loop mode. Iterate over all descriptors, collect
518 * errors and call callback function
520 for (i = 0; i < sdmac->num_bd; i++) {
523 if (bd->mode.status & (BD_DONE | BD_RROR))
525 sdmac->chn_real_count += bd->mode.count;
529 sdmac->status = DMA_ERROR;
531 sdmac->status = DMA_SUCCESS;
533 sdmac->chan.completed_cookie = sdmac->desc.cookie;
534 if (sdmac->desc.callback)
535 sdmac->desc.callback(sdmac->desc.callback_param);
538 static void mxc_sdma_handle_channel(struct sdma_channel *sdmac)
540 complete(&sdmac->done);
542 /* not interested in channel 0 interrupts */
543 if (sdmac->channel == 0)
546 if (sdmac->flags & IMX_DMA_SG_LOOP)
547 sdma_handle_channel_loop(sdmac);
549 mxc_sdma_handle_channel_normal(sdmac);
552 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
554 struct sdma_engine *sdma = dev_id;
557 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
558 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
561 int channel = fls(stat) - 1;
562 struct sdma_channel *sdmac = &sdma->channel[channel];
564 mxc_sdma_handle_channel(sdmac);
566 __clear_bit(channel, &stat);
573 * sets the pc of SDMA script according to the peripheral type
575 static void sdma_get_pc(struct sdma_channel *sdmac,
576 enum sdma_peripheral_type peripheral_type)
578 struct sdma_engine *sdma = sdmac->sdma;
579 int per_2_emi = 0, emi_2_per = 0;
581 * These are needed once we start to support transfers between
582 * two peripherals or memory-to-memory transfers
584 int per_2_per = 0, emi_2_emi = 0;
586 sdmac->pc_from_device = 0;
587 sdmac->pc_to_device = 0;
589 switch (peripheral_type) {
590 case IMX_DMATYPE_MEMORY:
591 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
593 case IMX_DMATYPE_DSP:
594 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
595 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
597 case IMX_DMATYPE_FIRI:
598 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
599 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
601 case IMX_DMATYPE_UART:
602 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
603 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
605 case IMX_DMATYPE_UART_SP:
606 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
607 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
609 case IMX_DMATYPE_ATA:
610 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
611 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
613 case IMX_DMATYPE_CSPI:
614 case IMX_DMATYPE_EXT:
615 case IMX_DMATYPE_SSI:
616 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
617 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
619 case IMX_DMATYPE_SSI_SP:
620 case IMX_DMATYPE_MMC:
621 case IMX_DMATYPE_SDHC:
622 case IMX_DMATYPE_CSPI_SP:
623 case IMX_DMATYPE_ESAI:
624 case IMX_DMATYPE_MSHC_SP:
625 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
626 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
628 case IMX_DMATYPE_ASRC:
629 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
630 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
631 per_2_per = sdma->script_addrs->per_2_per_addr;
633 case IMX_DMATYPE_MSHC:
634 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
635 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
637 case IMX_DMATYPE_CCM:
638 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
640 case IMX_DMATYPE_SPDIF:
641 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
642 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
644 case IMX_DMATYPE_IPU_MEMORY:
645 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
651 sdmac->pc_from_device = per_2_emi;
652 sdmac->pc_to_device = emi_2_per;
655 static int sdma_load_context(struct sdma_channel *sdmac)
657 struct sdma_engine *sdma = sdmac->sdma;
658 int channel = sdmac->channel;
660 struct sdma_context_data *context = sdma->context;
661 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
664 if (sdmac->direction == DMA_DEV_TO_MEM) {
665 load_address = sdmac->pc_from_device;
667 load_address = sdmac->pc_to_device;
670 if (load_address < 0)
673 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
674 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
675 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
676 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
677 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
678 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
680 mutex_lock(&sdma->channel_0_lock);
682 memset(context, 0, sizeof(*context));
683 context->channel_state.pc = load_address;
685 /* Send by context the event mask,base address for peripheral
686 * and watermark level
688 context->gReg[0] = sdmac->event_mask[1];
689 context->gReg[1] = sdmac->event_mask[0];
690 context->gReg[2] = sdmac->per_addr;
691 context->gReg[6] = sdmac->shp_addr;
692 context->gReg[7] = sdmac->watermark_level;
694 bd0->mode.command = C0_SETDM;
695 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
696 bd0->mode.count = sizeof(*context) / 4;
697 bd0->buffer_addr = sdma->context_phys;
698 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
700 ret = sdma_run_channel(&sdma->channel[0]);
702 mutex_unlock(&sdma->channel_0_lock);
707 static void sdma_disable_channel(struct sdma_channel *sdmac)
709 struct sdma_engine *sdma = sdmac->sdma;
710 int channel = sdmac->channel;
712 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
713 sdmac->status = DMA_ERROR;
716 static int sdma_config_channel(struct sdma_channel *sdmac)
720 sdma_disable_channel(sdmac);
722 sdmac->event_mask[0] = 0;
723 sdmac->event_mask[1] = 0;
727 if (sdmac->event_id0) {
728 if (sdmac->event_id0 >= sdmac->sdma->num_events)
730 sdma_event_enable(sdmac, sdmac->event_id0);
733 switch (sdmac->peripheral_type) {
734 case IMX_DMATYPE_DSP:
735 sdma_config_ownership(sdmac, false, true, true);
737 case IMX_DMATYPE_MEMORY:
738 sdma_config_ownership(sdmac, false, true, false);
741 sdma_config_ownership(sdmac, true, true, false);
745 sdma_get_pc(sdmac, sdmac->peripheral_type);
747 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
748 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
749 /* Handle multiple event channels differently */
750 if (sdmac->event_id1) {
751 sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32);
752 if (sdmac->event_id1 > 31)
753 __set_bit(31, &sdmac->watermark_level);
754 sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32);
755 if (sdmac->event_id0 > 31)
756 __set_bit(30, &sdmac->watermark_level);
758 __set_bit(sdmac->event_id0, sdmac->event_mask);
760 /* Watermark Level */
761 sdmac->watermark_level |= sdmac->watermark_level;
763 sdmac->shp_addr = sdmac->per_address;
765 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
768 ret = sdma_load_context(sdmac);
773 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
774 unsigned int priority)
776 struct sdma_engine *sdma = sdmac->sdma;
777 int channel = sdmac->channel;
779 if (priority < MXC_SDMA_MIN_PRIORITY
780 || priority > MXC_SDMA_MAX_PRIORITY) {
784 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
789 static int sdma_request_channel(struct sdma_channel *sdmac)
791 struct sdma_engine *sdma = sdmac->sdma;
792 int channel = sdmac->channel;
795 sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
801 memset(sdmac->bd, 0, PAGE_SIZE);
803 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
804 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
806 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
808 init_completion(&sdmac->done);
818 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
820 return container_of(chan, struct sdma_channel, chan);
823 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
826 struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
829 spin_lock_irqsave(&sdmac->lock, flags);
831 cookie = dma_cookie_assign(tx);
833 spin_unlock_irqrestore(&sdmac->lock, flags);
838 static int sdma_alloc_chan_resources(struct dma_chan *chan)
840 struct sdma_channel *sdmac = to_sdma_chan(chan);
841 struct imx_dma_data *data = chan->private;
847 switch (data->priority) {
851 case DMA_PRIO_MEDIUM:
860 sdmac->peripheral_type = data->peripheral_type;
861 sdmac->event_id0 = data->dma_request;
863 clk_enable(sdmac->sdma->clk);
865 ret = sdma_request_channel(sdmac);
869 ret = sdma_set_channel_priority(sdmac, prio);
873 dma_async_tx_descriptor_init(&sdmac->desc, chan);
874 sdmac->desc.tx_submit = sdma_tx_submit;
875 /* txd.flags will be overwritten in prep funcs */
876 sdmac->desc.flags = DMA_CTRL_ACK;
881 static void sdma_free_chan_resources(struct dma_chan *chan)
883 struct sdma_channel *sdmac = to_sdma_chan(chan);
884 struct sdma_engine *sdma = sdmac->sdma;
886 sdma_disable_channel(sdmac);
888 if (sdmac->event_id0)
889 sdma_event_disable(sdmac, sdmac->event_id0);
890 if (sdmac->event_id1)
891 sdma_event_disable(sdmac, sdmac->event_id1);
893 sdmac->event_id0 = 0;
894 sdmac->event_id1 = 0;
896 sdma_set_channel_priority(sdmac, 0);
898 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
900 clk_disable(sdma->clk);
903 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
904 struct dma_chan *chan, struct scatterlist *sgl,
905 unsigned int sg_len, enum dma_transfer_direction direction,
908 struct sdma_channel *sdmac = to_sdma_chan(chan);
909 struct sdma_engine *sdma = sdmac->sdma;
911 int channel = sdmac->channel;
912 struct scatterlist *sg;
914 if (sdmac->status == DMA_IN_PROGRESS)
916 sdmac->status = DMA_IN_PROGRESS;
920 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
923 sdmac->direction = direction;
924 ret = sdma_load_context(sdmac);
928 if (sg_len > NUM_BD) {
929 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
930 channel, sg_len, NUM_BD);
935 sdmac->chn_count = 0;
936 for_each_sg(sgl, sg, sg_len, i) {
937 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
940 bd->buffer_addr = sg->dma_address;
944 if (count > 0xffff) {
945 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
946 channel, count, 0xffff);
951 bd->mode.count = count;
952 sdmac->chn_count += count;
954 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
959 switch (sdmac->word_size) {
960 case DMA_SLAVE_BUSWIDTH_4_BYTES:
961 bd->mode.command = 0;
962 if (count & 3 || sg->dma_address & 3)
965 case DMA_SLAVE_BUSWIDTH_2_BYTES:
966 bd->mode.command = 2;
967 if (count & 1 || sg->dma_address & 1)
970 case DMA_SLAVE_BUSWIDTH_1_BYTE:
971 bd->mode.command = 1;
977 param = BD_DONE | BD_EXTD | BD_CONT;
979 if (i + 1 == sg_len) {
985 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
986 i, count, sg->dma_address,
987 param & BD_WRAP ? "wrap" : "",
988 param & BD_INTR ? " intr" : "");
990 bd->mode.status = param;
993 sdmac->num_bd = sg_len;
994 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
998 sdmac->status = DMA_ERROR;
1002 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1003 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1004 size_t period_len, enum dma_transfer_direction direction)
1006 struct sdma_channel *sdmac = to_sdma_chan(chan);
1007 struct sdma_engine *sdma = sdmac->sdma;
1008 int num_periods = buf_len / period_len;
1009 int channel = sdmac->channel;
1010 int ret, i = 0, buf = 0;
1012 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1014 if (sdmac->status == DMA_IN_PROGRESS)
1017 sdmac->status = DMA_IN_PROGRESS;
1019 sdmac->flags |= IMX_DMA_SG_LOOP;
1020 sdmac->direction = direction;
1021 ret = sdma_load_context(sdmac);
1025 if (num_periods > NUM_BD) {
1026 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1027 channel, num_periods, NUM_BD);
1031 if (period_len > 0xffff) {
1032 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1033 channel, period_len, 0xffff);
1037 while (buf < buf_len) {
1038 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1041 bd->buffer_addr = dma_addr;
1043 bd->mode.count = period_len;
1045 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1047 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1048 bd->mode.command = 0;
1050 bd->mode.command = sdmac->word_size;
1052 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1053 if (i + 1 == num_periods)
1056 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1057 i, period_len, dma_addr,
1058 param & BD_WRAP ? "wrap" : "",
1059 param & BD_INTR ? " intr" : "");
1061 bd->mode.status = param;
1063 dma_addr += period_len;
1069 sdmac->num_bd = num_periods;
1070 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1072 return &sdmac->desc;
1074 sdmac->status = DMA_ERROR;
1078 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1081 struct sdma_channel *sdmac = to_sdma_chan(chan);
1082 struct dma_slave_config *dmaengine_cfg = (void *)arg;
1085 case DMA_TERMINATE_ALL:
1086 sdma_disable_channel(sdmac);
1088 case DMA_SLAVE_CONFIG:
1089 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1090 sdmac->per_address = dmaengine_cfg->src_addr;
1091 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1092 dmaengine_cfg->src_addr_width;
1093 sdmac->word_size = dmaengine_cfg->src_addr_width;
1095 sdmac->per_address = dmaengine_cfg->dst_addr;
1096 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1097 dmaengine_cfg->dst_addr_width;
1098 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1100 sdmac->direction = dmaengine_cfg->direction;
1101 return sdma_config_channel(sdmac);
1109 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1110 dma_cookie_t cookie,
1111 struct dma_tx_state *txstate)
1113 struct sdma_channel *sdmac = to_sdma_chan(chan);
1114 dma_cookie_t last_used;
1116 last_used = chan->cookie;
1118 dma_set_tx_state(txstate, chan->completed_cookie, last_used,
1119 sdmac->chn_count - sdmac->chn_real_count);
1121 return sdmac->status;
1124 static void sdma_issue_pending(struct dma_chan *chan)
1126 struct sdma_channel *sdmac = to_sdma_chan(chan);
1127 struct sdma_engine *sdma = sdmac->sdma;
1129 if (sdmac->status == DMA_IN_PROGRESS)
1132 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1134 static void sdma_add_scripts(struct sdma_engine *sdma,
1135 const struct sdma_script_start_addrs *addr)
1137 s32 *addr_arr = (u32 *)addr;
1138 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1141 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1142 if (addr_arr[i] > 0)
1143 saddr_arr[i] = addr_arr[i];
1146 static void sdma_load_firmware(const struct firmware *fw, void *context)
1148 struct sdma_engine *sdma = context;
1149 const struct sdma_firmware_header *header;
1150 const struct sdma_script_start_addrs *addr;
1151 unsigned short *ram_code;
1154 dev_err(sdma->dev, "firmware not found\n");
1158 if (fw->size < sizeof(*header))
1161 header = (struct sdma_firmware_header *)fw->data;
1163 if (header->magic != SDMA_FIRMWARE_MAGIC)
1165 if (header->ram_code_start + header->ram_code_size > fw->size)
1168 addr = (void *)header + header->script_addrs_start;
1169 ram_code = (void *)header + header->ram_code_start;
1171 clk_enable(sdma->clk);
1172 /* download the RAM image for SDMA */
1173 sdma_load_script(sdma, ram_code,
1174 header->ram_code_size,
1175 addr->ram_code_start_addr);
1176 clk_disable(sdma->clk);
1178 sdma_add_scripts(sdma, addr);
1180 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1181 header->version_major,
1182 header->version_minor);
1185 release_firmware(fw);
1188 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1189 const char *fw_name)
1193 ret = request_firmware_nowait(THIS_MODULE,
1194 FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1195 GFP_KERNEL, sdma, sdma_load_firmware);
1200 static int __init sdma_init(struct sdma_engine *sdma)
1203 dma_addr_t ccb_phys;
1205 switch (sdma->devtype) {
1207 sdma->num_events = 32;
1210 sdma->num_events = 48;
1213 dev_err(sdma->dev, "Unknown sdma type %d. aborting\n",
1218 clk_enable(sdma->clk);
1220 /* Be sure SDMA has not started yet */
1221 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1223 sdma->channel_control = dma_alloc_coherent(NULL,
1224 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1225 sizeof(struct sdma_context_data),
1226 &ccb_phys, GFP_KERNEL);
1228 if (!sdma->channel_control) {
1233 sdma->context = (void *)sdma->channel_control +
1234 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1235 sdma->context_phys = ccb_phys +
1236 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1238 /* Zero-out the CCB structures array just allocated */
1239 memset(sdma->channel_control, 0,
1240 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1242 /* disable all channels */
1243 for (i = 0; i < sdma->num_events; i++)
1244 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1246 /* All channels have priority 0 */
1247 for (i = 0; i < MAX_DMA_CHANNELS; i++)
1248 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1250 ret = sdma_request_channel(&sdma->channel[0]);
1254 sdma_config_ownership(&sdma->channel[0], false, true, false);
1256 /* Set Command Channel (Channel Zero) */
1257 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1259 /* Set bits of CONFIG register but with static context switching */
1260 /* FIXME: Check whether to set ACR bit depending on clock ratios */
1261 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1263 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1265 /* Set bits of CONFIG register with given context switching mode */
1266 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1268 /* Initializes channel's priorities */
1269 sdma_set_channel_priority(&sdma->channel[0], 7);
1271 clk_disable(sdma->clk);
1276 clk_disable(sdma->clk);
1277 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1281 static int __init sdma_probe(struct platform_device *pdev)
1283 const struct of_device_id *of_id =
1284 of_match_device(sdma_dt_ids, &pdev->dev);
1285 struct device_node *np = pdev->dev.of_node;
1286 const char *fw_name;
1289 struct resource *iores;
1290 struct sdma_platform_data *pdata = pdev->dev.platform_data;
1292 struct sdma_engine *sdma;
1295 sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1299 mutex_init(&sdma->channel_0_lock);
1301 sdma->dev = &pdev->dev;
1303 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1304 irq = platform_get_irq(pdev, 0);
1305 if (!iores || irq < 0) {
1310 if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1312 goto err_request_region;
1315 sdma->clk = clk_get(&pdev->dev, NULL);
1316 if (IS_ERR(sdma->clk)) {
1317 ret = PTR_ERR(sdma->clk);
1321 sdma->regs = ioremap(iores->start, resource_size(iores));
1327 ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1329 goto err_request_irq;
1331 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1332 if (!sdma->script_addrs) {
1337 /* initially no scripts available */
1338 saddr_arr = (s32 *)sdma->script_addrs;
1339 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1340 saddr_arr[i] = -EINVAL;
1343 pdev->id_entry = of_id->data;
1344 sdma->devtype = pdev->id_entry->driver_data;
1346 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1347 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1349 INIT_LIST_HEAD(&sdma->dma_device.channels);
1350 /* Initialize channel parameters */
1351 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1352 struct sdma_channel *sdmac = &sdma->channel[i];
1355 spin_lock_init(&sdmac->lock);
1357 sdmac->chan.device = &sdma->dma_device;
1361 * Add the channel to the DMAC list. Do not add channel 0 though
1362 * because we need it internally in the SDMA driver. This also means
1363 * that channel 0 in dmaengine counting matches sdma channel 1.
1366 list_add_tail(&sdmac->chan.device_node,
1367 &sdma->dma_device.channels);
1370 ret = sdma_init(sdma);
1374 if (pdata && pdata->script_addrs)
1375 sdma_add_scripts(sdma, pdata->script_addrs);
1378 sdma_get_firmware(sdma, pdata->fw_name);
1381 * Because that device tree does not encode ROM script address,
1382 * the RAM script in firmware is mandatory for device tree
1383 * probe, otherwise it fails.
1385 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1388 dev_err(&pdev->dev, "failed to get firmware name\n");
1392 ret = sdma_get_firmware(sdma, fw_name);
1394 dev_err(&pdev->dev, "failed to get firmware\n");
1399 sdma->dma_device.dev = &pdev->dev;
1401 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1402 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1403 sdma->dma_device.device_tx_status = sdma_tx_status;
1404 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1405 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1406 sdma->dma_device.device_control = sdma_control;
1407 sdma->dma_device.device_issue_pending = sdma_issue_pending;
1408 sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1409 dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1411 ret = dma_async_device_register(&sdma->dma_device);
1413 dev_err(&pdev->dev, "unable to register\n");
1417 dev_info(sdma->dev, "initialized\n");
1422 kfree(sdma->script_addrs);
1424 free_irq(irq, sdma);
1426 iounmap(sdma->regs);
1430 release_mem_region(iores->start, resource_size(iores));
1437 static int __exit sdma_remove(struct platform_device *pdev)
1442 static struct platform_driver sdma_driver = {
1445 .of_match_table = sdma_dt_ids,
1447 .id_table = sdma_devtypes,
1448 .remove = __exit_p(sdma_remove),
1451 static int __init sdma_module_init(void)
1453 return platform_driver_probe(&sdma_driver, sdma_probe);
1455 module_init(sdma_module_init);
1457 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1458 MODULE_DESCRIPTION("i.MX SDMA driver");
1459 MODULE_LICENSE("GPL");