drivers/dma/ioat/dma.c

   1 /*
   2  * Intel I/OAT DMA Linux driver
   3  * Copyright(c) 2004 - 2009 Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  */
  22
  23 /*
  24  * This driver supports an Intel I/OAT DMA engine, which does asynchronous
  25  * copy operations.
  26  */
  27
  28 #include <linux/init.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/dmaengine.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/i7300_idle.h>
  37 #include "dma.h"
  38 #include "registers.h"
  39 #include "hw.h"
  40
  41 int ioat_pending_level = 4;
  42 module_param(ioat_pending_level, int, 0644);
  43 MODULE_PARM_DESC(ioat_pending_level,
  44                  "high-water mark for pushing ioat descriptors (default: 4)");
  45
  46 /* internal functions */
  47 static void ioat1_cleanup(struct ioat_dma_chan *ioat);
  48 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat);
  49
  50 /**
  51  * ioat_dma_do_interrupt - handler used for single vector interrupt mode
  52  * @irq: interrupt id
  53  * @data: interrupt data
  54  */
  55 static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
  56 {
  57         struct ioatdma_device *instance = data;
  58         struct ioat_chan_common *chan;
  59         unsigned long attnstatus;
  60         int bit;
  61         u8 intrctrl;
  62
  63         intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
  64
  65         if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
  66                 return IRQ_NONE;
  67
  68         if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
  69                 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
  70                 return IRQ_NONE;
  71         }
  72
  73         attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
  74         for_each_bit(bit, &attnstatus, BITS_PER_LONG) {
  75                 chan = ioat_chan_by_index(instance, bit);
  76                 tasklet_schedule(&chan->cleanup_task);
  77         }
  78
  79         writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
  80         return IRQ_HANDLED;
  81 }
  82
  83 /**
  84  * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
  85  * @irq: interrupt id
  86  * @data: interrupt data
  87  */
  88 static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
  89 {
  90         struct ioat_chan_common *chan = data;
  91
  92         tasklet_schedule(&chan->cleanup_task);
  93
  94         return IRQ_HANDLED;
  95 }
  96
  97 static void ioat1_cleanup_tasklet(unsigned long data);
  98
  99 /* common channel initialization */
 100 void ioat_init_channel(struct ioatdma_device *device,
 101                        struct ioat_chan_common *chan, int idx,
 102                        work_func_t work_fn, void (*tasklet)(unsigned long),
 103                        unsigned long tasklet_data)
 104 {
 105         struct dma_device *dma = &device->common;
 106
 107         chan->device = device;
 108         chan->reg_base = device->reg_base + (0x80 * (idx + 1));
 109         INIT_DELAYED_WORK(&chan->work, work_fn);
 110         spin_lock_init(&chan->cleanup_lock);
 111         chan->common.device = dma;
 112         list_add_tail(&chan->common.device_node, &dma->channels);
 113         device->idx[idx] = chan;
 114         tasklet_init(&chan->cleanup_task, tasklet, tasklet_data);
 115         tasklet_disable(&chan->cleanup_task);
 116 }
 117
 118 static void ioat1_reset_part2(struct work_struct *work);
 119
 120 /**
 121  * ioat1_dma_enumerate_channels - find and initialize the device's channels
 122  * @device: the device to be enumerated
 123  */
 124 static int ioat1_enumerate_channels(struct ioatdma_device *device)
 125 {
 126         u8 xfercap_scale;
 127         u32 xfercap;
 128         int i;
 129         struct ioat_dma_chan *ioat;
 130         struct device *dev = &device->pdev->dev;
 131         struct dma_device *dma = &device->common;
 132
 133         INIT_LIST_HEAD(&dma->channels);
 134         dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
 135         xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
 136         xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
 137
 138 #ifdef  CONFIG_I7300_IDLE_IOAT_CHANNEL
 139         if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
 140                 dma->chancnt--;
 141 #endif
 142         for (i = 0; i < dma->chancnt; i++) {
 143                 ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
 144                 if (!ioat)
 145                         break;
 146
 147                 ioat_init_channel(device, &ioat->base, i,
 148                                   ioat1_reset_part2,
 149                                   ioat1_cleanup_tasklet,
 150                                   (unsigned long) ioat);
 151                 ioat->xfercap = xfercap;
 152                 spin_lock_init(&ioat->desc_lock);
 153                 INIT_LIST_HEAD(&ioat->free_desc);
 154                 INIT_LIST_HEAD(&ioat->used_desc);
 155         }
 156         dma->chancnt = i;
 157         return i;
 158 }
 159
 160 /**
 161  * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
 162  *                                 descriptors to hw
 163  * @chan: DMA channel handle
 164  */
 165 static inline void
 166 __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat)
 167 {
 168         void __iomem *reg_base = ioat->base.reg_base;
 169
 170         ioat->pending = 0;
 171         writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET);
 172 }
 173
 174 static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
 175 {
 176         struct ioat_dma_chan *ioat = to_ioat_chan(chan);
 177
 178         if (ioat->pending > 0) {
 179                 spin_lock_bh(&ioat->desc_lock);
 180                 __ioat1_dma_memcpy_issue_pending(ioat);
 181                 spin_unlock_bh(&ioat->desc_lock);
 182         }
 183 }
 184
 185 /**
 186  * ioat1_reset_part2 - reinit the channel after a reset
 187  */
 188 static void ioat1_reset_part2(struct work_struct *work)
 189 {
 190         struct ioat_chan_common *chan;
 191         struct ioat_dma_chan *ioat;
 192         struct ioat_desc_sw *desc;
 193         int dmacount;
 194         bool start_null = false;
 195
 196         chan = container_of(work, struct ioat_chan_common, work.work);
 197         ioat = container_of(chan, struct ioat_dma_chan, base);
 198         spin_lock_bh(&chan->cleanup_lock);
 199         spin_lock_bh(&ioat->desc_lock);
 200
 201         chan->completion_virt->low = 0;
 202         chan->completion_virt->high = 0;
 203         ioat->pending = 0;
 204
 205         /* count the descriptors waiting */
 206         dmacount = 0;
 207         if (ioat->used_desc.prev) {
 208                 desc = to_ioat_desc(ioat->used_desc.prev);
 209                 do {
 210                         dmacount++;
 211                         desc = to_ioat_desc(desc->node.next);
 212                 } while (&desc->node != ioat->used_desc.next);
 213         }
 214
 215         if (dmacount) {
 216                 /*
 217                  * write the new starting descriptor address
 218                  * this puts channel engine into ARMED state
 219                  */
 220                 desc = to_ioat_desc(ioat->used_desc.prev);
 221                 writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF,
 222                        chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
 223                 writel(((u64) desc->txd.phys) >> 32,
 224                        chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
 225
 226                 writeb(IOAT_CHANCMD_START, chan->reg_base
 227                         + IOAT_CHANCMD_OFFSET(chan->device->version));
 228         } else
 229                 start_null = true;
 230         spin_unlock_bh(&ioat->desc_lock);
 231         spin_unlock_bh(&chan->cleanup_lock);
 232
 233         dev_err(to_dev(chan),
 234                 "chan%d reset - %d descs waiting, %d total desc\n",
 235                 chan_num(chan), dmacount, ioat->desccount);
 236
 237         if (start_null)
 238                 ioat1_dma_start_null_desc(ioat);
 239 }
 240
 241 /**
 242  * ioat1_reset_channel - restart a channel
 243  * @ioat: IOAT DMA channel handle
 244  */
 245 static void ioat1_reset_channel(struct ioat_dma_chan *ioat)
 246 {
 247         struct ioat_chan_common *chan = &ioat->base;
 248         void __iomem *reg_base = chan->reg_base;
 249         u32 chansts, chanerr;
 250
 251         if (!ioat->used_desc.prev)
 252                 return;
 253
 254         chanerr = readl(reg_base + IOAT_CHANERR_OFFSET);
 255         chansts = (chan->completion_virt->low
 256                                         & IOAT_CHANSTS_DMA_TRANSFER_STATUS);
 257         if (chanerr) {
 258                 dev_err(to_dev(chan),
 259                         "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
 260                         chan_num(chan), chansts, chanerr);
 261                 writel(chanerr, reg_base + IOAT_CHANERR_OFFSET);
 262         }
 263
 264         /*
 265          * whack it upside the head with a reset
 266          * and wait for things to settle out.
 267          * force the pending count to a really big negative
 268          * to make sure no one forces an issue_pending
 269          * while we're waiting.
 270          */
 271
 272         spin_lock_bh(&ioat->desc_lock);
 273         ioat->pending = INT_MIN;
 274         writeb(IOAT_CHANCMD_RESET,
 275                reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
 276         spin_unlock_bh(&ioat->desc_lock);
 277
 278         /* schedule the 2nd half instead of sleeping a long time */
 279         schedule_delayed_work(&chan->work, RESET_DELAY);
 280 }
 281
 282 /**
 283  * ioat1_chan_watchdog - watch for stuck channels
 284  */
 285 static void ioat1_chan_watchdog(struct work_struct *work)
 286 {
 287         struct ioatdma_device *device =
 288                 container_of(work, struct ioatdma_device, work.work);
 289         struct ioat_dma_chan *ioat;
 290         struct ioat_chan_common *chan;
 291         int i;
 292
 293         union {
 294                 u64 full;
 295                 struct {
 296                         u32 low;
 297                         u32 high;
 298                 };
 299         } completion_hw;
 300         unsigned long compl_desc_addr_hw;
 301
 302         for (i = 0; i < device->common.chancnt; i++) {
 303                 chan = ioat_chan_by_index(device, i);
 304                 ioat = container_of(chan, struct ioat_dma_chan, base);
 305
 306                 if (/* have we started processing anything yet */
 307                     chan->last_completion
 308                     /* have we completed any since last watchdog cycle? */
 309                     && (chan->last_completion == chan->watchdog_completion)
 310                     /* has TCP stuck on one cookie since last watchdog? */
 311                     && (chan->watchdog_tcp_cookie == chan->watchdog_last_tcp_cookie)
 312                     && (chan->watchdog_tcp_cookie != chan->completed_cookie)
 313                     /* is there something in the chain to be processed? */
 314                     /* CB1 chain always has at least the last one processed */
 315                     && (ioat->used_desc.prev != ioat->used_desc.next)
 316                     && ioat->pending == 0) {
 317
 318                         /*
 319                          * check CHANSTS register for completed
 320                          * descriptor address.
 321                          * if it is different than completion writeback,
 322                          * it is not zero
 323                          * and it has changed since the last watchdog
 324                          *     we can assume that channel
 325                          *     is still working correctly
 326                          *     and the problem is in completion writeback.
 327                          *     update completion writeback
 328                          *     with actual CHANSTS value
 329                          * else
 330                          *     try resetting the channel
 331                          */
 332
 333                         completion_hw.low = readl(chan->reg_base +
 334                                 IOAT_CHANSTS_OFFSET_LOW(chan->device->version));
 335                         completion_hw.high = readl(chan->reg_base +
 336                                 IOAT_CHANSTS_OFFSET_HIGH(chan->device->version));
 337 #if (BITS_PER_LONG == 64)
 338                         compl_desc_addr_hw =
 339                                 completion_hw.full
 340                                 & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
 341 #else
 342                         compl_desc_addr_hw =
 343                                 completion_hw.low & IOAT_LOW_COMPLETION_MASK;
 344 #endif
 345
 346                         if ((compl_desc_addr_hw != 0)
 347                            && (compl_desc_addr_hw != chan->watchdog_completion)
 348                            && (compl_desc_addr_hw != chan->last_compl_desc_addr_hw)) {
 349                                 chan->last_compl_desc_addr_hw = compl_desc_addr_hw;
 350                                 chan->completion_virt->low = completion_hw.low;
 351                                 chan->completion_virt->high = completion_hw.high;
 352                         } else {
 353                                 ioat1_reset_channel(ioat);
 354                                 chan->watchdog_completion = 0;
 355                                 chan->last_compl_desc_addr_hw = 0;
 356                         }
 357                 } else {
 358                         chan->last_compl_desc_addr_hw = 0;
 359                         chan->watchdog_completion = chan->last_completion;
 360                 }
 361
 362                 chan->watchdog_last_tcp_cookie = chan->watchdog_tcp_cookie;
 363         }
 364
 365         schedule_delayed_work(&device->work, WATCHDOG_DELAY);
 366 }
 367
 368 static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
 369 {
 370         struct dma_chan *c = tx->chan;
 371         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 372         struct ioat_desc_sw *desc = tx_to_ioat_desc(tx);
 373         struct ioat_desc_sw *first;
 374         struct ioat_desc_sw *chain_tail;
 375         dma_cookie_t cookie;
 376
 377         spin_lock_bh(&ioat->desc_lock);
 378         /* cookie incr and addition to used_list must be atomic */
 379         cookie = c->cookie;
 380         cookie++;
 381         if (cookie < 0)
 382                 cookie = 1;
 383         c->cookie = cookie;
 384         tx->cookie = cookie;
 385
 386         /* write address into NextDescriptor field of last desc in chain */
 387         first = to_ioat_desc(tx->tx_list.next);
 388         chain_tail = to_ioat_desc(ioat->used_desc.prev);
 389         /* make descriptor updates globally visible before chaining */
 390         wmb();
 391         chain_tail->hw->next = first->txd.phys;
 392         list_splice_tail_init(&tx->tx_list, &ioat->used_desc);
 393
 394         ioat->pending += desc->tx_cnt;
 395         if (ioat->pending >= ioat_pending_level)
 396                 __ioat1_dma_memcpy_issue_pending(ioat);
 397         spin_unlock_bh(&ioat->desc_lock);
 398
 399         return cookie;
 400 }
 401
 402 /**
 403  * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
 404  * @ioat: the channel supplying the memory pool for the descriptors
 405  * @flags: allocation flags
 406  */
 407 static struct ioat_desc_sw *
 408 ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags)
 409 {
 410         struct ioat_dma_descriptor *desc;
 411         struct ioat_desc_sw *desc_sw;
 412         struct ioatdma_device *ioatdma_device;
 413         dma_addr_t phys;
 414
 415         ioatdma_device = ioat->base.device;
 416         desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
 417         if (unlikely(!desc))
 418                 return NULL;
 419
 420         desc_sw = kzalloc(sizeof(*desc_sw), flags);
 421         if (unlikely(!desc_sw)) {
 422                 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
 423                 return NULL;
 424         }
 425
 426         memset(desc, 0, sizeof(*desc));
 427
 428         dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common);
 429         desc_sw->txd.tx_submit = ioat1_tx_submit;
 430         desc_sw->hw = desc;
 431         desc_sw->txd.phys = phys;
 432
 433         return desc_sw;
 434 }
 435
 436 static int ioat_initial_desc_count = 256;
 437 module_param(ioat_initial_desc_count, int, 0644);
 438 MODULE_PARM_DESC(ioat_initial_desc_count,
 439                  "ioat1: initial descriptors per channel (default: 256)");
 440 /**
 441  * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors
 442  * @chan: the channel to be filled out
 443  */
 444 static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
 445 {
 446         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 447         struct ioat_chan_common *chan = &ioat->base;
 448         struct ioat_desc_sw *desc;
 449         u16 chanctrl;
 450         u32 chanerr;
 451         int i;
 452         LIST_HEAD(tmp_list);
 453
 454         /* have we already been set up? */
 455         if (!list_empty(&ioat->free_desc))
 456                 return ioat->desccount;
 457
 458         /* Setup register to interrupt and write completion status on error */
 459         chanctrl = IOAT_CHANCTRL_ERR_INT_EN |
 460                 IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
 461                 IOAT_CHANCTRL_ERR_COMPLETION_EN;
 462         writew(chanctrl, chan->reg_base + IOAT_CHANCTRL_OFFSET);
 463
 464         chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
 465         if (chanerr) {
 466                 dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr);
 467                 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
 468         }
 469
 470         /* Allocate descriptors */
 471         for (i = 0; i < ioat_initial_desc_count; i++) {
 472                 desc = ioat_dma_alloc_descriptor(ioat, GFP_KERNEL);
 473                 if (!desc) {
 474                         dev_err(to_dev(chan), "Only %d initial descriptors\n", i);
 475                         break;
 476                 }
 477                 list_add_tail(&desc->node, &tmp_list);
 478         }
 479         spin_lock_bh(&ioat->desc_lock);
 480         ioat->desccount = i;
 481         list_splice(&tmp_list, &ioat->free_desc);
 482         spin_unlock_bh(&ioat->desc_lock);
 483
 484         /* allocate a completion writeback area */
 485         /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
 486         chan->completion_virt = pci_pool_alloc(chan->device->completion_pool,
 487                                                GFP_KERNEL,
 488                                                &chan->completion_addr);
 489         memset(chan->completion_virt, 0,
 490                sizeof(*chan->completion_virt));
 491         writel(((u64) chan->completion_addr) & 0x00000000FFFFFFFF,
 492                chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
 493         writel(((u64) chan->completion_addr) >> 32,
 494                chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
 495
 496         tasklet_enable(&chan->cleanup_task);
 497         ioat1_dma_start_null_desc(ioat);  /* give chain to dma device */
 498         return ioat->desccount;
 499 }
 500
 501 /**
 502  * ioat1_dma_free_chan_resources - release all the descriptors
 503  * @chan: the channel to be cleaned
 504  */
 505 static void ioat1_dma_free_chan_resources(struct dma_chan *c)
 506 {
 507         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 508         struct ioat_chan_common *chan = &ioat->base;
 509         struct ioatdma_device *ioatdma_device = chan->device;
 510         struct ioat_desc_sw *desc, *_desc;
 511         int in_use_descs = 0;
 512
 513         /* Before freeing channel resources first check
 514          * if they have been previously allocated for this channel.
 515          */
 516         if (ioat->desccount == 0)
 517                 return;
 518
 519         tasklet_disable(&chan->cleanup_task);
 520         ioat1_cleanup(ioat);
 521
 522         /* Delay 100ms after reset to allow internal DMA logic to quiesce
 523          * before removing DMA descriptor resources.
 524          */
 525         writeb(IOAT_CHANCMD_RESET,
 526                chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
 527         mdelay(100);
 528
 529         spin_lock_bh(&ioat->desc_lock);
 530         list_for_each_entry_safe(desc, _desc,
 531                                  &ioat->used_desc, node) {
 532                 in_use_descs++;
 533                 list_del(&desc->node);
 534                 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 535                               desc->txd.phys);
 536                 kfree(desc);
 537         }
 538         list_for_each_entry_safe(desc, _desc,
 539                                  &ioat->free_desc, node) {
 540                 list_del(&desc->node);
 541                 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 542                               desc->txd.phys);
 543                 kfree(desc);
 544         }
 545         spin_unlock_bh(&ioat->desc_lock);
 546
 547         pci_pool_free(ioatdma_device->completion_pool,
 548                       chan->completion_virt,
 549                       chan->completion_addr);
 550
 551         /* one is ok since we left it on there on purpose */
 552         if (in_use_descs > 1)
 553                 dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
 554                         in_use_descs - 1);
 555
 556         chan->last_completion = chan->completion_addr = 0;
 557         chan->watchdog_completion = 0;
 558         chan->last_compl_desc_addr_hw = 0;
 559         chan->watchdog_tcp_cookie = chan->watchdog_last_tcp_cookie = 0;
 560         ioat->pending = 0;
 561         ioat->desccount = 0;
 562 }
 563
 564 /**
 565  * ioat1_dma_get_next_descriptor - return the next available descriptor
 566  * @ioat: IOAT DMA channel handle
 567  *
 568  * Gets the next descriptor from the chain, and must be called with the
 569  * channel's desc_lock held.  Allocates more descriptors if the channel
 570  * has run out.
 571  */
 572 static struct ioat_desc_sw *
 573 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat)
 574 {
 575         struct ioat_desc_sw *new;
 576
 577         if (!list_empty(&ioat->free_desc)) {
 578                 new = to_ioat_desc(ioat->free_desc.next);
 579                 list_del(&new->node);
 580         } else {
 581                 /* try to get another desc */
 582                 new = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC);
 583                 if (!new) {
 584                         dev_err(to_dev(&ioat->base), "alloc failed\n");
 585                         return NULL;
 586                 }
 587         }
 588
 589         prefetch(new->hw);
 590         return new;
 591 }
 592
 593 static struct dma_async_tx_descriptor *
 594 ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
 595                       dma_addr_t dma_src, size_t len, unsigned long flags)
 596 {
 597         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 598         struct ioat_desc_sw *desc;
 599         size_t copy;
 600         LIST_HEAD(chain);
 601         dma_addr_t src = dma_src;
 602         dma_addr_t dest = dma_dest;
 603         size_t total_len = len;
 604         struct ioat_dma_descriptor *hw = NULL;
 605         int tx_cnt = 0;
 606
 607         spin_lock_bh(&ioat->desc_lock);
 608         desc = ioat1_dma_get_next_descriptor(ioat);
 609         do {
 610                 if (!desc)
 611                         break;
 612
 613                 tx_cnt++;
 614                 copy = min_t(size_t, len, ioat->xfercap);
 615
 616                 hw = desc->hw;
 617                 hw->size = copy;
 618                 hw->ctl = 0;
 619                 hw->src_addr = src;
 620                 hw->dst_addr = dest;
 621
 622                 list_add_tail(&desc->node, &chain);
 623
 624                 len -= copy;
 625                 dest += copy;
 626                 src += copy;
 627                 if (len) {
 628                         struct ioat_desc_sw *next;
 629
 630                         async_tx_ack(&desc->txd);
 631                         next = ioat1_dma_get_next_descriptor(ioat);
 632                         hw->next = next ? next->txd.phys : 0;
 633                         desc = next;
 634                 } else
 635                         hw->next = 0;
 636         } while (len);
 637
 638         if (!desc) {
 639                 struct ioat_chan_common *chan = &ioat->base;
 640
 641                 dev_err(to_dev(chan),
 642                         "chan%d - get_next_desc failed\n", chan_num(chan));
 643                 list_splice(&chain, &ioat->free_desc);
 644                 spin_unlock_bh(&ioat->desc_lock);
 645                 return NULL;
 646         }
 647         spin_unlock_bh(&ioat->desc_lock);
 648
 649         desc->txd.flags = flags;
 650         desc->tx_cnt = tx_cnt;
 651         desc->len = total_len;
 652         list_splice(&chain, &desc->txd.tx_list);
 653         hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
 654         hw->ctl_f.compl_write = 1;
 655
 656         return &desc->txd;
 657 }
 658
 659 static void ioat1_cleanup_tasklet(unsigned long data)
 660 {
 661         struct ioat_dma_chan *chan = (void *)data;
 662         ioat1_cleanup(chan);
 663         writew(IOAT_CHANCTRL_INT_DISABLE,
 664                chan->base.reg_base + IOAT_CHANCTRL_OFFSET);
 665 }
 666
 667 static void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len,
 668                        int direction, enum dma_ctrl_flags flags, bool dst)
 669 {
 670         if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) ||
 671             (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE)))
 672                 pci_unmap_single(pdev, addr, len, direction);
 673         else
 674                 pci_unmap_page(pdev, addr, len, direction);
 675 }
 676
 677
 678 void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
 679                     size_t len, struct ioat_dma_descriptor *hw)
 680 {
 681         struct pci_dev *pdev = chan->device->pdev;
 682         size_t offset = len - hw->size;
 683
 684         if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
 685                 ioat_unmap(pdev, hw->dst_addr - offset, len,
 686                            PCI_DMA_FROMDEVICE, flags, 1);
 687
 688         if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP))
 689                 ioat_unmap(pdev, hw->src_addr - offset, len,
 690                            PCI_DMA_TODEVICE, flags, 0);
 691 }
 692
 693 unsigned long ioat_get_current_completion(struct ioat_chan_common *chan)
 694 {
 695         unsigned long phys_complete;
 696
 697         /* The completion writeback can happen at any time,
 698            so reads by the driver need to be atomic operations
 699            The descriptor physical addresses are limited to 32-bits
 700            when the CPU can only do a 32-bit mov */
 701
 702 #if (BITS_PER_LONG == 64)
 703         phys_complete =
 704                 chan->completion_virt->full
 705                 & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
 706 #else
 707         phys_complete = chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK;
 708 #endif
 709
 710         if ((chan->completion_virt->full
 711                 & IOAT_CHANSTS_DMA_TRANSFER_STATUS) ==
 712                                 IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) {
 713                 dev_err(to_dev(chan), "Channel halted, chanerr = %x\n",
 714                         readl(chan->reg_base + IOAT_CHANERR_OFFSET));
 715
 716                 /* TODO do something to salvage the situation */
 717         }
 718
 719         return phys_complete;
 720 }
 721
 722 /**
 723  * ioat1_cleanup - cleanup up finished descriptors
 724  * @chan: ioat channel to be cleaned up
 725  */
 726 static void ioat1_cleanup(struct ioat_dma_chan *ioat)
 727 {
 728         struct ioat_chan_common *chan = &ioat->base;
 729         unsigned long phys_complete;
 730         struct ioat_desc_sw *desc, *_desc;
 731         dma_cookie_t cookie = 0;
 732         struct dma_async_tx_descriptor *tx;
 733
 734         prefetch(chan->completion_virt);
 735
 736         if (!spin_trylock_bh(&chan->cleanup_lock))
 737                 return;
 738
 739         phys_complete = ioat_get_current_completion(chan);
 740         if (phys_complete == chan->last_completion) {
 741                 spin_unlock_bh(&chan->cleanup_lock);
 742                 /*
 743                  * perhaps we're stuck so hard that the watchdog can't go off?
 744                  * try to catch it after 2 seconds
 745                  */
 746                 if (time_after(jiffies,
 747                                chan->last_completion_time + HZ*WATCHDOG_DELAY)) {
 748                         ioat1_chan_watchdog(&(chan->device->work.work));
 749                         chan->last_completion_time = jiffies;
 750                 }
 751                 return;
 752         }
 753         chan->last_completion_time = jiffies;
 754
 755         cookie = 0;
 756         if (!spin_trylock_bh(&ioat->desc_lock)) {
 757                 spin_unlock_bh(&chan->cleanup_lock);
 758                 return;
 759         }
 760
 761         list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) {
 762                 tx = &desc->txd;
 763                 /*
 764                  * Incoming DMA requests may use multiple descriptors,
 765                  * due to exceeding xfercap, perhaps. If so, only the
 766                  * last one will have a cookie, and require unmapping.
 767                  */
 768                 if (tx->cookie) {
 769                         cookie = tx->cookie;
 770                         ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
 771                         if (tx->callback) {
 772                                 tx->callback(tx->callback_param);
 773                                 tx->callback = NULL;
 774                         }
 775                 }
 776
 777                 if (tx->phys != phys_complete) {
 778                         /*
 779                          * a completed entry, but not the last, so clean
 780                          * up if the client is done with the descriptor
 781                          */
 782                         if (async_tx_test_ack(tx))
 783                                 list_move_tail(&desc->node, &ioat->free_desc);
 784                         else
 785                                 tx->cookie = 0;
 786                 } else {
 787                         /*
 788                          * last used desc. Do not remove, so we can
 789                          * append from it, but don't look at it next
 790                          * time, either
 791                          */
 792                         tx->cookie = 0;
 793
 794                         /* TODO check status bits? */
 795                         break;
 796                 }
 797         }
 798
 799         spin_unlock_bh(&ioat->desc_lock);
 800
 801         chan->last_completion = phys_complete;
 802         if (cookie != 0)
 803                 chan->completed_cookie = cookie;
 804
 805         spin_unlock_bh(&chan->cleanup_lock);
 806 }
 807
 808 static enum dma_status
 809 ioat1_dma_is_complete(struct dma_chan *c, dma_cookie_t cookie,
 810                       dma_cookie_t *done, dma_cookie_t *used)
 811 {
 812         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 813
 814         if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS)
 815                 return DMA_SUCCESS;
 816
 817         ioat1_cleanup(ioat);
 818
 819         return ioat_is_complete(c, cookie, done, used);
 820 }
 821
 822 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat)
 823 {
 824         struct ioat_chan_common *chan = &ioat->base;
 825         struct ioat_desc_sw *desc;
 826         struct ioat_dma_descriptor *hw;
 827
 828         spin_lock_bh(&ioat->desc_lock);
 829
 830         desc = ioat1_dma_get_next_descriptor(ioat);
 831
 832         if (!desc) {
 833                 dev_err(to_dev(chan),
 834                         "Unable to start null desc - get next desc failed\n");
 835                 spin_unlock_bh(&ioat->desc_lock);
 836                 return;
 837         }
 838
 839         hw = desc->hw;
 840         hw->ctl = 0;
 841         hw->ctl_f.null = 1;
 842         hw->ctl_f.int_en = 1;
 843         hw->ctl_f.compl_write = 1;
 844         /* set size to non-zero value (channel returns error when size is 0) */
 845         hw->size = NULL_DESC_BUFFER_SIZE;
 846         hw->src_addr = 0;
 847         hw->dst_addr = 0;
 848         async_tx_ack(&desc->txd);
 849         hw->next = 0;
 850         list_add_tail(&desc->node, &ioat->used_desc);
 851
 852         writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF,
 853                chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
 854         writel(((u64) desc->txd.phys) >> 32,
 855                chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
 856
 857         writeb(IOAT_CHANCMD_START, chan->reg_base
 858                 + IOAT_CHANCMD_OFFSET(chan->device->version));
 859         spin_unlock_bh(&ioat->desc_lock);
 860 }
 861
 862 /*
 863  * Perform a IOAT transaction to verify the HW works.
 864  */
 865 #define IOAT_TEST_SIZE 2000
 866
 867 static void ioat_dma_test_callback(void *dma_async_param)
 868 {
 869         struct completion *cmp = dma_async_param;
 870
 871         complete(cmp);
 872 }
 873
 874 /**
 875  * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
 876  * @device: device to be tested
 877  */
 878 static int ioat_dma_self_test(struct ioatdma_device *device)
 879 {
 880         int i;
 881         u8 *src;
 882         u8 *dest;
 883         struct dma_device *dma = &device->common;
 884         struct device *dev = &device->pdev->dev;
 885         struct dma_chan *dma_chan;
 886         struct dma_async_tx_descriptor *tx;
 887         dma_addr_t dma_dest, dma_src;
 888         dma_cookie_t cookie;
 889         int err = 0;
 890         struct completion cmp;
 891         unsigned long tmo;
 892         unsigned long flags;
 893
 894         src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
 895         if (!src)
 896                 return -ENOMEM;
 897         dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
 898         if (!dest) {
 899                 kfree(src);
 900                 return -ENOMEM;
 901         }
 902
 903         /* Fill in src buffer */
 904         for (i = 0; i < IOAT_TEST_SIZE; i++)
 905                 src[i] = (u8)i;
 906
 907         /* Start copy, using first DMA channel */
 908         dma_chan = container_of(dma->channels.next, struct dma_chan,
 909                                 device_node);
 910         if (dma->device_alloc_chan_resources(dma_chan) < 1) {
 911                 dev_err(dev, "selftest cannot allocate chan resource\n");
 912                 err = -ENODEV;
 913                 goto out;
 914         }
 915
 916         dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
 917         dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
 918         flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE |
 919                 DMA_PREP_INTERRUPT;
 920         tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
 921                                                    IOAT_TEST_SIZE, flags);
 922         if (!tx) {
 923                 dev_err(dev, "Self-test prep failed, disabling\n");
 924                 err = -ENODEV;
 925                 goto free_resources;
 926         }
 927
 928         async_tx_ack(tx);
 929         init_completion(&cmp);
 930         tx->callback = ioat_dma_test_callback;
 931         tx->callback_param = &cmp;
 932         cookie = tx->tx_submit(tx);
 933         if (cookie < 0) {
 934                 dev_err(dev, "Self-test setup failed, disabling\n");
 935                 err = -ENODEV;
 936                 goto free_resources;
 937         }
 938         dma->device_issue_pending(dma_chan);
 939
 940         tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
 941
 942         if (tmo == 0 ||
 943             dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL)
 944                                         != DMA_SUCCESS) {
 945                 dev_err(dev, "Self-test copy timed out, disabling\n");
 946                 err = -ENODEV;
 947                 goto free_resources;
 948         }
 949         if (memcmp(src, dest, IOAT_TEST_SIZE)) {
 950                 dev_err(dev, "Self-test copy failed compare, disabling\n");
 951                 err = -ENODEV;
 952                 goto free_resources;
 953         }
 954
 955 free_resources:
 956         dma->device_free_chan_resources(dma_chan);
 957 out:
 958         kfree(src);
 959         kfree(dest);
 960         return err;
 961 }
 962
 963 static char ioat_interrupt_style[32] = "msix";
 964 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
 965                     sizeof(ioat_interrupt_style), 0644);
 966 MODULE_PARM_DESC(ioat_interrupt_style,
 967                  "set ioat interrupt style: msix (default), "
 968                  "msix-single-vector, msi, intx)");
 969
 970 /**
 971  * ioat_dma_setup_interrupts - setup interrupt handler
 972  * @device: ioat device
 973  */
 974 static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
 975 {
 976         struct ioat_chan_common *chan;
 977         struct pci_dev *pdev = device->pdev;
 978         struct device *dev = &pdev->dev;
 979         struct msix_entry *msix;
 980         int i, j, msixcnt;
 981         int err = -EINVAL;
 982         u8 intrctrl = 0;
 983
 984         if (!strcmp(ioat_interrupt_style, "msix"))
 985                 goto msix;
 986         if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
 987                 goto msix_single_vector;
 988         if (!strcmp(ioat_interrupt_style, "msi"))
 989                 goto msi;
 990         if (!strcmp(ioat_interrupt_style, "intx"))
 991                 goto intx;
 992         dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
 993         goto err_no_irq;
 994
 995 msix:
 996         /* The number of MSI-X vectors should equal the number of channels */
 997         msixcnt = device->common.chancnt;
 998         for (i = 0; i < msixcnt; i++)
 999                 device->msix_entries[i].entry = i;
1000
1001         err = pci_enable_msix(pdev, device->msix_entries, msixcnt);
1002         if (err < 0)
1003                 goto msi;
1004         if (err > 0)
1005                 goto msix_single_vector;
1006
1007         for (i = 0; i < msixcnt; i++) {
1008                 msix = &device->msix_entries[i];
1009                 chan = ioat_chan_by_index(device, i);
1010                 err = devm_request_irq(dev, msix->vector,
1011                                        ioat_dma_do_interrupt_msix, 0,
1012                                        "ioat-msix", chan);
1013                 if (err) {
1014                         for (j = 0; j < i; j++) {
1015                                 msix = &device->msix_entries[j];
1016                                 chan = ioat_chan_by_index(device, j);
1017                                 devm_free_irq(dev, msix->vector, chan);
1018                         }
1019                         goto msix_single_vector;
1020                 }
1021         }
1022         intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
1023         goto done;
1024
1025 msix_single_vector:
1026         msix = &device->msix_entries[0];
1027         msix->entry = 0;
1028         err = pci_enable_msix(pdev, device->msix_entries, 1);
1029         if (err)
1030                 goto msi;
1031
1032         err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt, 0,
1033                                "ioat-msix", device);
1034         if (err) {
1035                 pci_disable_msix(pdev);
1036                 goto msi;
1037         }
1038         goto done;
1039
1040 msi:
1041         err = pci_enable_msi(pdev);
1042         if (err)
1043                 goto intx;
1044
1045         err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
1046                                "ioat-msi", device);
1047         if (err) {
1048                 pci_disable_msi(pdev);
1049                 goto intx;
1050         }
1051         goto done;
1052
1053 intx:
1054         err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
1055                                IRQF_SHARED, "ioat-intx", device);
1056         if (err)
1057                 goto err_no_irq;
1058
1059 done:
1060         if (device->intr_quirk)
1061                 device->intr_quirk(device);
1062         intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
1063         writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
1064         return 0;
1065
1066 err_no_irq:
1067         /* Disable all interrupt generation */
1068         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1069         dev_err(dev, "no usable interrupts\n");
1070         return err;
1071 }
1072
1073 static void ioat_disable_interrupts(struct ioatdma_device *device)
1074 {
1075         /* Disable all interrupt generation */
1076         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1077 }
1078
1079 int ioat_probe(struct ioatdma_device *device)
1080 {
1081         int err = -ENODEV;
1082         struct dma_device *dma = &device->common;
1083         struct pci_dev *pdev = device->pdev;
1084         struct device *dev = &pdev->dev;
1085
1086         /* DMA coherent memory pool for DMA descriptor allocations */
1087         device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
1088                                            sizeof(struct ioat_dma_descriptor),
1089                                            64, 0);
1090         if (!device->dma_pool) {
1091                 err = -ENOMEM;
1092                 goto err_dma_pool;
1093         }
1094
1095         device->completion_pool = pci_pool_create("completion_pool", pdev,
1096                                                   sizeof(u64), SMP_CACHE_BYTES,
1097                                                   SMP_CACHE_BYTES);
1098
1099         if (!device->completion_pool) {
1100                 err = -ENOMEM;
1101                 goto err_completion_pool;
1102         }
1103
1104         device->enumerate_channels(device);
1105
1106         dma_cap_set(DMA_MEMCPY, dma->cap_mask);
1107         dma->dev = &pdev->dev;
1108
1109         dev_err(dev, "Intel(R) I/OAT DMA Engine found,"
1110                 " %d channels, device version 0x%02x, driver version %s\n",
1111                 dma->chancnt, device->version, IOAT_DMA_VERSION);
1112
1113         if (!dma->chancnt) {
1114                 dev_err(dev, "Intel(R) I/OAT DMA Engine problem found: "
1115                         "zero channels detected\n");
1116                 goto err_setup_interrupts;
1117         }
1118
1119         err = ioat_dma_setup_interrupts(device);
1120         if (err)
1121                 goto err_setup_interrupts;
1122
1123         err = ioat_dma_self_test(device);
1124         if (err)
1125                 goto err_self_test;
1126
1127         return 0;
1128
1129 err_self_test:
1130         ioat_disable_interrupts(device);
1131 err_setup_interrupts:
1132         pci_pool_destroy(device->completion_pool);
1133 err_completion_pool:
1134         pci_pool_destroy(device->dma_pool);
1135 err_dma_pool:
1136         return err;
1137 }
1138
1139 int ioat_register(struct ioatdma_device *device)
1140 {
1141         int err = dma_async_device_register(&device->common);
1142
1143         if (err) {
1144                 ioat_disable_interrupts(device);
1145                 pci_pool_destroy(device->completion_pool);
1146                 pci_pool_destroy(device->dma_pool);
1147         }
1148
1149         return err;
1150 }
1151
1152 /* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */
1153 static void ioat1_intr_quirk(struct ioatdma_device *device)
1154 {
1155         struct pci_dev *pdev = device->pdev;
1156         u32 dmactrl;
1157
1158         pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
1159         if (pdev->msi_enabled)
1160                 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
1161         else
1162                 dmactrl &= ~IOAT_PCI_DMACTRL_MSI_EN;
1163         pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1164 }
1165
1166 int ioat1_dma_probe(struct ioatdma_device *device, int dca)
1167 {
1168         struct pci_dev *pdev = device->pdev;
1169         struct dma_device *dma;
1170         int err;
1171
1172         device->intr_quirk = ioat1_intr_quirk;
1173         device->enumerate_channels = ioat1_enumerate_channels;
1174         dma = &device->common;
1175         dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1176         dma->device_issue_pending = ioat1_dma_memcpy_issue_pending;
1177         dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources;
1178         dma->device_free_chan_resources = ioat1_dma_free_chan_resources;
1179         dma->device_is_tx_complete = ioat1_dma_is_complete;
1180
1181         err = ioat_probe(device);
1182         if (err)
1183                 return err;
1184         ioat_set_tcp_copy_break(4096);
1185         err = ioat_register(device);
1186         if (err)
1187                 return err;
1188         if (dca)
1189                 device->dca = ioat_dca_init(pdev, device->reg_base);
1190
1191         INIT_DELAYED_WORK(&device->work, ioat1_chan_watchdog);
1192         schedule_delayed_work(&device->work, WATCHDOG_DELAY);
1193
1194         return err;
1195 }
1196
1197 void ioat_dma_remove(struct ioatdma_device *device)
1198 {
1199         struct dma_device *dma = &device->common;
1200
1201         if (device->version != IOAT_VER_3_0)
1202                 cancel_delayed_work(&device->work);
1203
1204         ioat_disable_interrupts(device);
1205
1206         dma_async_device_unregister(dma);
1207
1208         pci_pool_destroy(device->dma_pool);
1209         pci_pool_destroy(device->completion_pool);
1210
1211         INIT_LIST_HEAD(&dma->channels);
1212 }