2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2015 Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in
15 * the file called "COPYING".
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/slab.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/dmaengine.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/workqueue.h>
28 #include <linux/prefetch.h>
29 #include <linux/dca.h>
31 #include "registers.h"
34 #include "../dmaengine.h"
36 MODULE_VERSION(IOAT_DMA_VERSION);
37 MODULE_LICENSE("Dual BSD/GPL");
38 MODULE_AUTHOR("Intel Corporation");
40 static struct pci_device_id ioat_pci_tbl[] = {
41 /* I/OAT v3 platforms */
42 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) },
43 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) },
44 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) },
45 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) },
46 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) },
47 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) },
48 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) },
49 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) },
51 /* I/OAT v3.2 platforms */
52 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) },
53 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) },
54 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) },
55 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) },
56 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) },
57 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) },
58 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) },
59 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) },
60 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) },
61 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) },
63 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) },
64 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) },
65 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) },
66 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) },
67 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) },
68 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) },
69 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) },
70 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) },
71 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) },
72 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) },
74 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) },
75 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) },
76 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) },
77 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) },
78 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) },
79 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) },
80 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) },
81 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) },
82 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) },
83 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) },
85 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) },
86 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) },
87 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) },
88 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) },
89 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) },
90 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) },
91 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) },
92 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) },
93 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) },
94 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) },
96 /* I/OAT v3.3 platforms */
97 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) },
98 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) },
99 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2) },
100 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3) },
102 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0) },
103 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1) },
104 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2) },
105 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3) },
109 MODULE_DEVICE_TABLE(pci, ioat_pci_tbl);
111 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
112 static void ioat_remove(struct pci_dev *pdev);
114 ioat_init_channel(struct ioatdma_device *ioat_dma,
115 struct ioatdma_chan *ioat_chan, int idx);
116 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma);
117 static int ioat_enumerate_channels(struct ioatdma_device *ioat_dma);
118 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma);
120 static int ioat_dca_enabled = 1;
121 module_param(ioat_dca_enabled, int, 0644);
122 MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)");
123 int ioat_pending_level = 4;
124 module_param(ioat_pending_level, int, 0644);
125 MODULE_PARM_DESC(ioat_pending_level,
126 "high-water mark for pushing ioat descriptors (default: 4)");
127 int ioat_ring_alloc_order = 8;
128 module_param(ioat_ring_alloc_order, int, 0644);
129 MODULE_PARM_DESC(ioat_ring_alloc_order,
130 "ioat+: allocate 2^n descriptors per channel (default: 8 max: 16)");
131 int ioat_ring_max_alloc_order = IOAT_MAX_ORDER;
132 module_param(ioat_ring_max_alloc_order, int, 0644);
133 MODULE_PARM_DESC(ioat_ring_max_alloc_order,
134 "ioat+: upper limit for ring size (default: 16)");
135 static char ioat_interrupt_style[32] = "msix";
136 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
137 sizeof(ioat_interrupt_style), 0644);
138 MODULE_PARM_DESC(ioat_interrupt_style,
139 "set ioat interrupt style: msix (default), msi, intx");
141 struct kmem_cache *ioat_cache;
142 struct kmem_cache *ioat_sed_cache;
144 static bool is_jf_ioat(struct pci_dev *pdev)
146 switch (pdev->device) {
147 case PCI_DEVICE_ID_INTEL_IOAT_JSF0:
148 case PCI_DEVICE_ID_INTEL_IOAT_JSF1:
149 case PCI_DEVICE_ID_INTEL_IOAT_JSF2:
150 case PCI_DEVICE_ID_INTEL_IOAT_JSF3:
151 case PCI_DEVICE_ID_INTEL_IOAT_JSF4:
152 case PCI_DEVICE_ID_INTEL_IOAT_JSF5:
153 case PCI_DEVICE_ID_INTEL_IOAT_JSF6:
154 case PCI_DEVICE_ID_INTEL_IOAT_JSF7:
155 case PCI_DEVICE_ID_INTEL_IOAT_JSF8:
156 case PCI_DEVICE_ID_INTEL_IOAT_JSF9:
163 static bool is_snb_ioat(struct pci_dev *pdev)
165 switch (pdev->device) {
166 case PCI_DEVICE_ID_INTEL_IOAT_SNB0:
167 case PCI_DEVICE_ID_INTEL_IOAT_SNB1:
168 case PCI_DEVICE_ID_INTEL_IOAT_SNB2:
169 case PCI_DEVICE_ID_INTEL_IOAT_SNB3:
170 case PCI_DEVICE_ID_INTEL_IOAT_SNB4:
171 case PCI_DEVICE_ID_INTEL_IOAT_SNB5:
172 case PCI_DEVICE_ID_INTEL_IOAT_SNB6:
173 case PCI_DEVICE_ID_INTEL_IOAT_SNB7:
174 case PCI_DEVICE_ID_INTEL_IOAT_SNB8:
175 case PCI_DEVICE_ID_INTEL_IOAT_SNB9:
182 static bool is_ivb_ioat(struct pci_dev *pdev)
184 switch (pdev->device) {
185 case PCI_DEVICE_ID_INTEL_IOAT_IVB0:
186 case PCI_DEVICE_ID_INTEL_IOAT_IVB1:
187 case PCI_DEVICE_ID_INTEL_IOAT_IVB2:
188 case PCI_DEVICE_ID_INTEL_IOAT_IVB3:
189 case PCI_DEVICE_ID_INTEL_IOAT_IVB4:
190 case PCI_DEVICE_ID_INTEL_IOAT_IVB5:
191 case PCI_DEVICE_ID_INTEL_IOAT_IVB6:
192 case PCI_DEVICE_ID_INTEL_IOAT_IVB7:
193 case PCI_DEVICE_ID_INTEL_IOAT_IVB8:
194 case PCI_DEVICE_ID_INTEL_IOAT_IVB9:
202 static bool is_hsw_ioat(struct pci_dev *pdev)
204 switch (pdev->device) {
205 case PCI_DEVICE_ID_INTEL_IOAT_HSW0:
206 case PCI_DEVICE_ID_INTEL_IOAT_HSW1:
207 case PCI_DEVICE_ID_INTEL_IOAT_HSW2:
208 case PCI_DEVICE_ID_INTEL_IOAT_HSW3:
209 case PCI_DEVICE_ID_INTEL_IOAT_HSW4:
210 case PCI_DEVICE_ID_INTEL_IOAT_HSW5:
211 case PCI_DEVICE_ID_INTEL_IOAT_HSW6:
212 case PCI_DEVICE_ID_INTEL_IOAT_HSW7:
213 case PCI_DEVICE_ID_INTEL_IOAT_HSW8:
214 case PCI_DEVICE_ID_INTEL_IOAT_HSW9:
222 static bool is_xeon_cb32(struct pci_dev *pdev)
224 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) ||
228 bool is_bwd_ioat(struct pci_dev *pdev)
230 switch (pdev->device) {
231 case PCI_DEVICE_ID_INTEL_IOAT_BWD0:
232 case PCI_DEVICE_ID_INTEL_IOAT_BWD1:
233 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
234 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
235 /* even though not Atom, BDX-DE has same DMA silicon */
236 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0:
237 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1:
238 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2:
239 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3:
246 static bool is_bwd_noraid(struct pci_dev *pdev)
248 switch (pdev->device) {
249 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
250 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
251 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0:
252 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1:
253 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2:
254 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3:
263 * Perform a IOAT transaction to verify the HW works.
265 #define IOAT_TEST_SIZE 2000
267 static void ioat_dma_test_callback(void *dma_async_param)
269 struct completion *cmp = dma_async_param;
275 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
276 * @ioat_dma: dma device to be tested
278 static int ioat_dma_self_test(struct ioatdma_device *ioat_dma)
283 struct dma_device *dma = &ioat_dma->dma_dev;
284 struct device *dev = &ioat_dma->pdev->dev;
285 struct dma_chan *dma_chan;
286 struct dma_async_tx_descriptor *tx;
287 dma_addr_t dma_dest, dma_src;
290 struct completion cmp;
294 src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
297 dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
303 /* Fill in src buffer */
304 for (i = 0; i < IOAT_TEST_SIZE; i++)
307 /* Start copy, using first DMA channel */
308 dma_chan = container_of(dma->channels.next, struct dma_chan,
310 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
311 dev_err(dev, "selftest cannot allocate chan resource\n");
316 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
317 if (dma_mapping_error(dev, dma_src)) {
318 dev_err(dev, "mapping src buffer failed\n");
321 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
322 if (dma_mapping_error(dev, dma_dest)) {
323 dev_err(dev, "mapping dest buffer failed\n");
326 flags = DMA_PREP_INTERRUPT;
327 tx = ioat_dma->dma_dev.device_prep_dma_memcpy(dma_chan, dma_dest,
328 dma_src, IOAT_TEST_SIZE,
331 dev_err(dev, "Self-test prep failed, disabling\n");
337 init_completion(&cmp);
338 tx->callback = ioat_dma_test_callback;
339 tx->callback_param = &cmp;
340 cookie = tx->tx_submit(tx);
342 dev_err(dev, "Self-test setup failed, disabling\n");
346 dma->device_issue_pending(dma_chan);
348 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
351 dma->device_tx_status(dma_chan, cookie, NULL)
353 dev_err(dev, "Self-test copy timed out, disabling\n");
357 if (memcmp(src, dest, IOAT_TEST_SIZE)) {
358 dev_err(dev, "Self-test copy failed compare, disabling\n");
364 dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
366 dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
368 dma->device_free_chan_resources(dma_chan);
376 * ioat_dma_setup_interrupts - setup interrupt handler
377 * @ioat_dma: ioat dma device
379 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma)
381 struct ioatdma_chan *ioat_chan;
382 struct pci_dev *pdev = ioat_dma->pdev;
383 struct device *dev = &pdev->dev;
384 struct msix_entry *msix;
389 if (!strcmp(ioat_interrupt_style, "msix"))
391 if (!strcmp(ioat_interrupt_style, "msi"))
393 if (!strcmp(ioat_interrupt_style, "intx"))
395 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
399 /* The number of MSI-X vectors should equal the number of channels */
400 msixcnt = ioat_dma->dma_dev.chancnt;
401 for (i = 0; i < msixcnt; i++)
402 ioat_dma->msix_entries[i].entry = i;
404 err = pci_enable_msix_exact(pdev, ioat_dma->msix_entries, msixcnt);
408 for (i = 0; i < msixcnt; i++) {
409 msix = &ioat_dma->msix_entries[i];
410 ioat_chan = ioat_chan_by_index(ioat_dma, i);
411 err = devm_request_irq(dev, msix->vector,
412 ioat_dma_do_interrupt_msix, 0,
413 "ioat-msix", ioat_chan);
415 for (j = 0; j < i; j++) {
416 msix = &ioat_dma->msix_entries[j];
417 ioat_chan = ioat_chan_by_index(ioat_dma, j);
418 devm_free_irq(dev, msix->vector, ioat_chan);
423 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
424 ioat_dma->irq_mode = IOAT_MSIX;
428 err = pci_enable_msi(pdev);
432 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
433 "ioat-msi", ioat_dma);
435 pci_disable_msi(pdev);
438 ioat_dma->irq_mode = IOAT_MSI;
442 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
443 IRQF_SHARED, "ioat-intx", ioat_dma);
447 ioat_dma->irq_mode = IOAT_INTX;
449 if (is_bwd_ioat(pdev))
450 ioat_intr_quirk(ioat_dma);
451 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
452 writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
456 /* Disable all interrupt generation */
457 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
458 ioat_dma->irq_mode = IOAT_NOIRQ;
459 dev_err(dev, "no usable interrupts\n");
463 static void ioat_disable_interrupts(struct ioatdma_device *ioat_dma)
465 /* Disable all interrupt generation */
466 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
469 static int ioat_probe(struct ioatdma_device *ioat_dma)
472 struct dma_device *dma = &ioat_dma->dma_dev;
473 struct pci_dev *pdev = ioat_dma->pdev;
474 struct device *dev = &pdev->dev;
476 /* DMA coherent memory pool for DMA descriptor allocations */
477 ioat_dma->dma_pool = pci_pool_create("dma_desc_pool", pdev,
478 sizeof(struct ioat_dma_descriptor),
480 if (!ioat_dma->dma_pool) {
485 ioat_dma->completion_pool = pci_pool_create("completion_pool", pdev,
490 if (!ioat_dma->completion_pool) {
492 goto err_completion_pool;
495 ioat_enumerate_channels(ioat_dma);
497 dma_cap_set(DMA_MEMCPY, dma->cap_mask);
498 dma->dev = &pdev->dev;
501 dev_err(dev, "channel enumeration error\n");
502 goto err_setup_interrupts;
505 err = ioat_dma_setup_interrupts(ioat_dma);
507 goto err_setup_interrupts;
509 err = ioat3_dma_self_test(ioat_dma);
516 ioat_disable_interrupts(ioat_dma);
517 err_setup_interrupts:
518 pci_pool_destroy(ioat_dma->completion_pool);
520 pci_pool_destroy(ioat_dma->dma_pool);
525 static int ioat_register(struct ioatdma_device *ioat_dma)
527 int err = dma_async_device_register(&ioat_dma->dma_dev);
530 ioat_disable_interrupts(ioat_dma);
531 pci_pool_destroy(ioat_dma->completion_pool);
532 pci_pool_destroy(ioat_dma->dma_pool);
538 static void ioat_dma_remove(struct ioatdma_device *ioat_dma)
540 struct dma_device *dma = &ioat_dma->dma_dev;
542 ioat_disable_interrupts(ioat_dma);
544 ioat_kobject_del(ioat_dma);
546 dma_async_device_unregister(dma);
548 pci_pool_destroy(ioat_dma->dma_pool);
549 pci_pool_destroy(ioat_dma->completion_pool);
551 INIT_LIST_HEAD(&dma->channels);
555 * ioat_enumerate_channels - find and initialize the device's channels
556 * @ioat_dma: the ioat dma device to be enumerated
558 static int ioat_enumerate_channels(struct ioatdma_device *ioat_dma)
560 struct ioatdma_chan *ioat_chan;
561 struct device *dev = &ioat_dma->pdev->dev;
562 struct dma_device *dma = &ioat_dma->dma_dev;
566 INIT_LIST_HEAD(&dma->channels);
567 dma->chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET);
568 dma->chancnt &= 0x1f; /* bits [4:0] valid */
569 if (dma->chancnt > ARRAY_SIZE(ioat_dma->idx)) {
570 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
571 dma->chancnt, ARRAY_SIZE(ioat_dma->idx));
572 dma->chancnt = ARRAY_SIZE(ioat_dma->idx);
574 xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET);
575 xfercap_log &= 0x1f; /* bits [4:0] valid */
576 if (xfercap_log == 0)
578 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
580 for (i = 0; i < dma->chancnt; i++) {
581 ioat_chan = devm_kzalloc(dev, sizeof(*ioat_chan), GFP_KERNEL);
585 ioat_init_channel(ioat_dma, ioat_chan, i);
586 ioat_chan->xfercap_log = xfercap_log;
587 spin_lock_init(&ioat_chan->prep_lock);
588 if (ioat_reset_hw(ioat_chan)) {
598 * ioat_free_chan_resources - release all the descriptors
599 * @chan: the channel to be cleaned
601 static void ioat_free_chan_resources(struct dma_chan *c)
603 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
604 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
605 struct ioat_ring_ent *desc;
606 const int total_descs = 1 << ioat_chan->alloc_order;
610 /* Before freeing channel resources first check
611 * if they have been previously allocated for this channel.
613 if (!ioat_chan->ring)
616 ioat_stop(ioat_chan);
617 ioat_reset_hw(ioat_chan);
619 spin_lock_bh(&ioat_chan->cleanup_lock);
620 spin_lock_bh(&ioat_chan->prep_lock);
621 descs = ioat_ring_space(ioat_chan);
622 dev_dbg(to_dev(ioat_chan), "freeing %d idle descriptors\n", descs);
623 for (i = 0; i < descs; i++) {
624 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head + i);
625 ioat_free_ring_ent(desc, c);
628 if (descs < total_descs)
629 dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n",
630 total_descs - descs);
632 for (i = 0; i < total_descs - descs; i++) {
633 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail + i);
634 dump_desc_dbg(ioat_chan, desc);
635 ioat_free_ring_ent(desc, c);
638 kfree(ioat_chan->ring);
639 ioat_chan->ring = NULL;
640 ioat_chan->alloc_order = 0;
641 pci_pool_free(ioat_dma->completion_pool, ioat_chan->completion,
642 ioat_chan->completion_dma);
643 spin_unlock_bh(&ioat_chan->prep_lock);
644 spin_unlock_bh(&ioat_chan->cleanup_lock);
646 ioat_chan->last_completion = 0;
647 ioat_chan->completion_dma = 0;
648 ioat_chan->dmacount = 0;
651 /* ioat_alloc_chan_resources - allocate/initialize ioat descriptor ring
652 * @chan: channel to be initialized
654 static int ioat_alloc_chan_resources(struct dma_chan *c)
656 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
657 struct ioat_ring_ent **ring;
663 /* have we already been set up? */
665 return 1 << ioat_chan->alloc_order;
667 /* Setup register to interrupt and write completion status on error */
668 writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
670 /* allocate a completion writeback area */
671 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
672 ioat_chan->completion =
673 pci_pool_alloc(ioat_chan->ioat_dma->completion_pool,
674 GFP_KERNEL, &ioat_chan->completion_dma);
675 if (!ioat_chan->completion)
678 memset(ioat_chan->completion, 0, sizeof(*ioat_chan->completion));
679 writel(((u64)ioat_chan->completion_dma) & 0x00000000FFFFFFFF,
680 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
681 writel(((u64)ioat_chan->completion_dma) >> 32,
682 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
684 order = ioat_get_alloc_order();
685 ring = ioat_alloc_ring(c, order, GFP_KERNEL);
689 spin_lock_bh(&ioat_chan->cleanup_lock);
690 spin_lock_bh(&ioat_chan->prep_lock);
691 ioat_chan->ring = ring;
693 ioat_chan->issued = 0;
695 ioat_chan->alloc_order = order;
696 set_bit(IOAT_RUN, &ioat_chan->state);
697 spin_unlock_bh(&ioat_chan->prep_lock);
698 spin_unlock_bh(&ioat_chan->cleanup_lock);
700 ioat_start_null_desc(ioat_chan);
702 /* check that we got off the ground */
705 status = ioat_chansts(ioat_chan);
706 } while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status));
708 if (is_ioat_active(status) || is_ioat_idle(status))
709 return 1 << ioat_chan->alloc_order;
711 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
713 dev_WARN(to_dev(ioat_chan),
714 "failed to start channel chanerr: %#x\n", chanerr);
715 ioat_free_chan_resources(c);
719 /* common channel initialization */
721 ioat_init_channel(struct ioatdma_device *ioat_dma,
722 struct ioatdma_chan *ioat_chan, int idx)
724 struct dma_device *dma = &ioat_dma->dma_dev;
725 struct dma_chan *c = &ioat_chan->dma_chan;
726 unsigned long data = (unsigned long) c;
728 ioat_chan->ioat_dma = ioat_dma;
729 ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1));
730 spin_lock_init(&ioat_chan->cleanup_lock);
731 ioat_chan->dma_chan.device = dma;
732 dma_cookie_init(&ioat_chan->dma_chan);
733 list_add_tail(&ioat_chan->dma_chan.device_node, &dma->channels);
734 ioat_dma->idx[idx] = ioat_chan;
735 init_timer(&ioat_chan->timer);
736 ioat_chan->timer.function = ioat_timer_event;
737 ioat_chan->timer.data = data;
738 tasklet_init(&ioat_chan->cleanup_task, ioat_cleanup_event, data);
741 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */
742 static int ioat_xor_val_self_test(struct ioatdma_device *ioat_dma)
746 struct page *xor_srcs[IOAT_NUM_SRC_TEST];
747 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1];
748 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1];
750 struct dma_async_tx_descriptor *tx;
751 struct dma_chan *dma_chan;
757 struct completion cmp;
759 struct device *dev = &ioat_dma->pdev->dev;
760 struct dma_device *dma = &ioat_dma->dma_dev;
763 dev_dbg(dev, "%s\n", __func__);
765 if (!dma_has_cap(DMA_XOR, dma->cap_mask))
768 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
769 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
770 if (!xor_srcs[src_idx]) {
772 __free_page(xor_srcs[src_idx]);
777 dest = alloc_page(GFP_KERNEL);
780 __free_page(xor_srcs[src_idx]);
784 /* Fill in src buffers */
785 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
786 u8 *ptr = page_address(xor_srcs[src_idx]);
788 for (i = 0; i < PAGE_SIZE; i++)
789 ptr[i] = (1 << src_idx);
792 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++)
793 cmp_byte ^= (u8) (1 << src_idx);
795 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
796 (cmp_byte << 8) | cmp_byte;
798 memset(page_address(dest), 0, PAGE_SIZE);
800 dma_chan = container_of(dma->channels.next, struct dma_chan,
802 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
810 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE);
811 if (dma_mapping_error(dev, dest_dma))
814 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
815 dma_srcs[i] = DMA_ERROR_CODE;
816 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) {
817 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE,
819 if (dma_mapping_error(dev, dma_srcs[i]))
822 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
823 IOAT_NUM_SRC_TEST, PAGE_SIZE,
827 dev_err(dev, "Self-test xor prep failed\n");
833 init_completion(&cmp);
834 tx->callback = ioat_dma_test_callback;
835 tx->callback_param = &cmp;
836 cookie = tx->tx_submit(tx);
838 dev_err(dev, "Self-test xor setup failed\n");
842 dma->device_issue_pending(dma_chan);
844 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
847 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
848 dev_err(dev, "Self-test xor timed out\n");
853 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
854 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
856 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
857 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
858 u32 *ptr = page_address(dest);
860 if (ptr[i] != cmp_word) {
861 dev_err(dev, "Self-test xor failed compare\n");
866 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
868 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
870 /* skip validate if the capability is not present */
871 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
874 op = IOAT_OP_XOR_VAL;
876 /* validate the sources with the destintation page */
877 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
878 xor_val_srcs[i] = xor_srcs[i];
879 xor_val_srcs[i] = dest;
883 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
884 dma_srcs[i] = DMA_ERROR_CODE;
885 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) {
886 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
888 if (dma_mapping_error(dev, dma_srcs[i]))
891 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
892 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
893 &xor_val_result, DMA_PREP_INTERRUPT);
895 dev_err(dev, "Self-test zero prep failed\n");
901 init_completion(&cmp);
902 tx->callback = ioat_dma_test_callback;
903 tx->callback_param = &cmp;
904 cookie = tx->tx_submit(tx);
906 dev_err(dev, "Self-test zero setup failed\n");
910 dma->device_issue_pending(dma_chan);
912 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
915 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
916 dev_err(dev, "Self-test validate timed out\n");
921 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
922 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
924 if (xor_val_result != 0) {
925 dev_err(dev, "Self-test validate failed compare\n");
930 memset(page_address(dest), 0, PAGE_SIZE);
932 /* test for non-zero parity sum */
933 op = IOAT_OP_XOR_VAL;
936 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
937 dma_srcs[i] = DMA_ERROR_CODE;
938 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) {
939 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
941 if (dma_mapping_error(dev, dma_srcs[i]))
944 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
945 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
946 &xor_val_result, DMA_PREP_INTERRUPT);
948 dev_err(dev, "Self-test 2nd zero prep failed\n");
954 init_completion(&cmp);
955 tx->callback = ioat_dma_test_callback;
956 tx->callback_param = &cmp;
957 cookie = tx->tx_submit(tx);
959 dev_err(dev, "Self-test 2nd zero setup failed\n");
963 dma->device_issue_pending(dma_chan);
965 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
968 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
969 dev_err(dev, "Self-test 2nd validate timed out\n");
974 if (xor_val_result != SUM_CHECK_P_RESULT) {
975 dev_err(dev, "Self-test validate failed compare\n");
980 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
981 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
985 if (op == IOAT_OP_XOR) {
986 if (dest_dma != DMA_ERROR_CODE)
987 dma_unmap_page(dev, dest_dma, PAGE_SIZE,
989 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
990 if (dma_srcs[i] != DMA_ERROR_CODE)
991 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
993 } else if (op == IOAT_OP_XOR_VAL) {
994 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
995 if (dma_srcs[i] != DMA_ERROR_CODE)
996 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1000 dma->device_free_chan_resources(dma_chan);
1002 src_idx = IOAT_NUM_SRC_TEST;
1004 __free_page(xor_srcs[src_idx]);
1009 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma)
1011 int rc = ioat_dma_self_test(ioat_dma);
1016 rc = ioat_xor_val_self_test(ioat_dma);
1023 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma)
1025 struct dma_device *dma;
1027 struct ioatdma_chan *ioat_chan;
1030 dma = &ioat_dma->dma_dev;
1033 * if we have descriptor write back error status, we mask the
1036 if (ioat_dma->cap & IOAT_CAP_DWBES) {
1037 list_for_each_entry(c, &dma->channels, device_node) {
1038 ioat_chan = to_ioat_chan(c);
1039 errmask = readl(ioat_chan->reg_base +
1040 IOAT_CHANERR_MASK_OFFSET);
1041 errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR |
1042 IOAT_CHANERR_XOR_Q_ERR;
1043 writel(errmask, ioat_chan->reg_base +
1044 IOAT_CHANERR_MASK_OFFSET);
1049 static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca)
1051 struct pci_dev *pdev = ioat_dma->pdev;
1052 int dca_en = system_has_dca_enabled(pdev);
1053 struct dma_device *dma;
1055 struct ioatdma_chan *ioat_chan;
1056 bool is_raid_device = false;
1059 dma = &ioat_dma->dma_dev;
1060 dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock;
1061 dma->device_issue_pending = ioat_issue_pending;
1062 dma->device_alloc_chan_resources = ioat_alloc_chan_resources;
1063 dma->device_free_chan_resources = ioat_free_chan_resources;
1065 dma_cap_set(DMA_INTERRUPT, dma->cap_mask);
1066 dma->device_prep_dma_interrupt = ioat_prep_interrupt_lock;
1068 ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET);
1070 if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev))
1072 ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS);
1074 /* dca is incompatible with raid operations */
1075 if (dca_en && (ioat_dma->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ)))
1076 ioat_dma->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ);
1078 if (ioat_dma->cap & IOAT_CAP_XOR) {
1079 is_raid_device = true;
1082 dma_cap_set(DMA_XOR, dma->cap_mask);
1083 dma->device_prep_dma_xor = ioat_prep_xor;
1085 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1086 dma->device_prep_dma_xor_val = ioat_prep_xor_val;
1089 if (ioat_dma->cap & IOAT_CAP_PQ) {
1090 is_raid_device = true;
1092 dma->device_prep_dma_pq = ioat_prep_pq;
1093 dma->device_prep_dma_pq_val = ioat_prep_pq_val;
1094 dma_cap_set(DMA_PQ, dma->cap_mask);
1095 dma_cap_set(DMA_PQ_VAL, dma->cap_mask);
1097 if (ioat_dma->cap & IOAT_CAP_RAID16SS)
1098 dma_set_maxpq(dma, 16, 0);
1100 dma_set_maxpq(dma, 8, 0);
1102 if (!(ioat_dma->cap & IOAT_CAP_XOR)) {
1103 dma->device_prep_dma_xor = ioat_prep_pqxor;
1104 dma->device_prep_dma_xor_val = ioat_prep_pqxor_val;
1105 dma_cap_set(DMA_XOR, dma->cap_mask);
1106 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1108 if (ioat_dma->cap & IOAT_CAP_RAID16SS)
1115 dma->device_tx_status = ioat_tx_status;
1117 /* starting with CB3.3 super extended descriptors are supported */
1118 if (ioat_dma->cap & IOAT_CAP_RAID16SS) {
1122 for (i = 0; i < MAX_SED_POOLS; i++) {
1123 snprintf(pool_name, 14, "ioat_hw%d_sed", i);
1125 /* allocate SED DMA pool */
1126 ioat_dma->sed_hw_pool[i] = dmam_pool_create(pool_name,
1128 SED_SIZE * (i + 1), 64, 0);
1129 if (!ioat_dma->sed_hw_pool[i])
1135 if (!(ioat_dma->cap & (IOAT_CAP_XOR | IOAT_CAP_PQ)))
1136 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
1138 err = ioat_probe(ioat_dma);
1142 list_for_each_entry(c, &dma->channels, device_node) {
1143 ioat_chan = to_ioat_chan(c);
1144 writel(IOAT_DMA_DCA_ANY_CPU,
1145 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
1148 err = ioat_register(ioat_dma);
1152 ioat_kobject_add(ioat_dma, &ioat_ktype);
1155 ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base);
1160 #define DRV_NAME "ioatdma"
1162 static struct pci_driver ioat_pci_driver = {
1164 .id_table = ioat_pci_tbl,
1165 .probe = ioat_pci_probe,
1166 .remove = ioat_remove,
1169 static struct ioatdma_device *
1170 alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase)
1172 struct device *dev = &pdev->dev;
1173 struct ioatdma_device *d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
1178 d->reg_base = iobase;
1182 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1184 void __iomem * const *iomap;
1185 struct device *dev = &pdev->dev;
1186 struct ioatdma_device *device;
1189 err = pcim_enable_device(pdev);
1193 err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME);
1196 iomap = pcim_iomap_table(pdev);
1200 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1202 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1206 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1208 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1212 device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]);
1215 pci_set_master(pdev);
1216 pci_set_drvdata(pdev, device);
1218 device->version = readb(device->reg_base + IOAT_VER_OFFSET);
1219 if (device->version >= IOAT_VER_3_0)
1220 err = ioat3_dma_probe(device, ioat_dca_enabled);
1225 dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n");
1232 static void ioat_remove(struct pci_dev *pdev)
1234 struct ioatdma_device *device = pci_get_drvdata(pdev);
1239 dev_err(&pdev->dev, "Removing dma and dca services\n");
1241 unregister_dca_provider(device->dca, &pdev->dev);
1242 free_dca_provider(device->dca);
1245 ioat_dma_remove(device);
1248 static int __init ioat_init_module(void)
1252 pr_info("%s: Intel(R) QuickData Technology Driver %s\n",
1253 DRV_NAME, IOAT_DMA_VERSION);
1255 ioat_cache = kmem_cache_create("ioat", sizeof(struct ioat_ring_ent),
1256 0, SLAB_HWCACHE_ALIGN, NULL);
1260 ioat_sed_cache = KMEM_CACHE(ioat_sed_ent, 0);
1261 if (!ioat_sed_cache)
1262 goto err_ioat_cache;
1264 err = pci_register_driver(&ioat_pci_driver);
1266 goto err_ioat3_cache;
1271 kmem_cache_destroy(ioat_sed_cache);
1274 kmem_cache_destroy(ioat_cache);
1278 module_init(ioat_init_module);
1280 static void __exit ioat_exit_module(void)
1282 pci_unregister_driver(&ioat_pci_driver);
1283 kmem_cache_destroy(ioat_cache);
1285 module_exit(ioat_exit_module);