2 * Driver for the TXx9 SoC DMA Controller
4 * Copyright (C) 2009 Atsushi Nemoto
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/dma-mapping.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/slab.h>
17 #include <linux/scatterlist.h>
19 #include "dmaengine.h"
22 static struct txx9dmac_chan *to_txx9dmac_chan(struct dma_chan *chan)
24 return container_of(chan, struct txx9dmac_chan, chan);
27 static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc)
32 static struct txx9dmac_cregs32 __iomem *__dma_regs32(
33 const struct txx9dmac_chan *dc)
38 #define channel64_readq(dc, name) \
39 __raw_readq(&(__dma_regs(dc)->name))
40 #define channel64_writeq(dc, name, val) \
41 __raw_writeq((val), &(__dma_regs(dc)->name))
42 #define channel64_readl(dc, name) \
43 __raw_readl(&(__dma_regs(dc)->name))
44 #define channel64_writel(dc, name, val) \
45 __raw_writel((val), &(__dma_regs(dc)->name))
47 #define channel32_readl(dc, name) \
48 __raw_readl(&(__dma_regs32(dc)->name))
49 #define channel32_writel(dc, name, val) \
50 __raw_writel((val), &(__dma_regs32(dc)->name))
52 #define channel_readq(dc, name) channel64_readq(dc, name)
53 #define channel_writeq(dc, name, val) channel64_writeq(dc, name, val)
54 #define channel_readl(dc, name) \
56 channel64_readl(dc, name) : channel32_readl(dc, name))
57 #define channel_writel(dc, name, val) \
59 channel64_writel(dc, name, val) : channel32_writel(dc, name, val))
61 static dma_addr_t channel64_read_CHAR(const struct txx9dmac_chan *dc)
63 if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
64 return channel64_readq(dc, CHAR);
66 return channel64_readl(dc, CHAR);
69 static void channel64_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
71 if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
72 channel64_writeq(dc, CHAR, val);
74 channel64_writel(dc, CHAR, val);
77 static void channel64_clear_CHAR(const struct txx9dmac_chan *dc)
79 #if defined(CONFIG_32BIT) && !defined(CONFIG_64BIT_PHYS_ADDR)
80 channel64_writel(dc, CHAR, 0);
81 channel64_writel(dc, __pad_CHAR, 0);
83 channel64_writeq(dc, CHAR, 0);
87 static dma_addr_t channel_read_CHAR(const struct txx9dmac_chan *dc)
90 return channel64_read_CHAR(dc);
92 return channel32_readl(dc, CHAR);
95 static void channel_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
98 channel64_write_CHAR(dc, val);
100 channel32_writel(dc, CHAR, val);
103 static struct txx9dmac_regs __iomem *__txx9dmac_regs(
104 const struct txx9dmac_dev *ddev)
109 static struct txx9dmac_regs32 __iomem *__txx9dmac_regs32(
110 const struct txx9dmac_dev *ddev)
115 #define dma64_readl(ddev, name) \
116 __raw_readl(&(__txx9dmac_regs(ddev)->name))
117 #define dma64_writel(ddev, name, val) \
118 __raw_writel((val), &(__txx9dmac_regs(ddev)->name))
120 #define dma32_readl(ddev, name) \
121 __raw_readl(&(__txx9dmac_regs32(ddev)->name))
122 #define dma32_writel(ddev, name, val) \
123 __raw_writel((val), &(__txx9dmac_regs32(ddev)->name))
125 #define dma_readl(ddev, name) \
126 (__is_dmac64(ddev) ? \
127 dma64_readl(ddev, name) : dma32_readl(ddev, name))
128 #define dma_writel(ddev, name, val) \
129 (__is_dmac64(ddev) ? \
130 dma64_writel(ddev, name, val) : dma32_writel(ddev, name, val))
132 static struct device *chan2dev(struct dma_chan *chan)
134 return &chan->dev->device;
136 static struct device *chan2parent(struct dma_chan *chan)
138 return chan->dev->device.parent;
141 static struct txx9dmac_desc *
142 txd_to_txx9dmac_desc(struct dma_async_tx_descriptor *txd)
144 return container_of(txd, struct txx9dmac_desc, txd);
147 static dma_addr_t desc_read_CHAR(const struct txx9dmac_chan *dc,
148 const struct txx9dmac_desc *desc)
150 return is_dmac64(dc) ? desc->hwdesc.CHAR : desc->hwdesc32.CHAR;
153 static void desc_write_CHAR(const struct txx9dmac_chan *dc,
154 struct txx9dmac_desc *desc, dma_addr_t val)
157 desc->hwdesc.CHAR = val;
159 desc->hwdesc32.CHAR = val;
162 #define TXX9_DMA_MAX_COUNT 0x04000000
164 #define TXX9_DMA_INITIAL_DESC_COUNT 64
166 static struct txx9dmac_desc *txx9dmac_first_active(struct txx9dmac_chan *dc)
168 return list_entry(dc->active_list.next,
169 struct txx9dmac_desc, desc_node);
172 static struct txx9dmac_desc *txx9dmac_last_active(struct txx9dmac_chan *dc)
174 return list_entry(dc->active_list.prev,
175 struct txx9dmac_desc, desc_node);
178 static struct txx9dmac_desc *txx9dmac_first_queued(struct txx9dmac_chan *dc)
180 return list_entry(dc->queue.next, struct txx9dmac_desc, desc_node);
183 static struct txx9dmac_desc *txx9dmac_last_child(struct txx9dmac_desc *desc)
185 if (!list_empty(&desc->tx_list))
186 desc = list_entry(desc->tx_list.prev, typeof(*desc), desc_node);
190 static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx);
192 static struct txx9dmac_desc *txx9dmac_desc_alloc(struct txx9dmac_chan *dc,
195 struct txx9dmac_dev *ddev = dc->ddev;
196 struct txx9dmac_desc *desc;
198 desc = kzalloc(sizeof(*desc), flags);
201 INIT_LIST_HEAD(&desc->tx_list);
202 dma_async_tx_descriptor_init(&desc->txd, &dc->chan);
203 desc->txd.tx_submit = txx9dmac_tx_submit;
204 /* txd.flags will be overwritten in prep funcs */
205 desc->txd.flags = DMA_CTRL_ACK;
206 desc->txd.phys = dma_map_single(chan2parent(&dc->chan), &desc->hwdesc,
207 ddev->descsize, DMA_TO_DEVICE);
211 static struct txx9dmac_desc *txx9dmac_desc_get(struct txx9dmac_chan *dc)
213 struct txx9dmac_desc *desc, *_desc;
214 struct txx9dmac_desc *ret = NULL;
217 spin_lock_bh(&dc->lock);
218 list_for_each_entry_safe(desc, _desc, &dc->free_list, desc_node) {
219 if (async_tx_test_ack(&desc->txd)) {
220 list_del(&desc->desc_node);
224 dev_dbg(chan2dev(&dc->chan), "desc %p not ACKed\n", desc);
227 spin_unlock_bh(&dc->lock);
229 dev_vdbg(chan2dev(&dc->chan), "scanned %u descriptors on freelist\n",
232 ret = txx9dmac_desc_alloc(dc, GFP_ATOMIC);
234 spin_lock_bh(&dc->lock);
235 dc->descs_allocated++;
236 spin_unlock_bh(&dc->lock);
238 dev_err(chan2dev(&dc->chan),
239 "not enough descriptors available\n");
244 static void txx9dmac_sync_desc_for_cpu(struct txx9dmac_chan *dc,
245 struct txx9dmac_desc *desc)
247 struct txx9dmac_dev *ddev = dc->ddev;
248 struct txx9dmac_desc *child;
250 list_for_each_entry(child, &desc->tx_list, desc_node)
251 dma_sync_single_for_cpu(chan2parent(&dc->chan),
252 child->txd.phys, ddev->descsize,
254 dma_sync_single_for_cpu(chan2parent(&dc->chan),
255 desc->txd.phys, ddev->descsize,
260 * Move a descriptor, including any children, to the free list.
261 * `desc' must not be on any lists.
263 static void txx9dmac_desc_put(struct txx9dmac_chan *dc,
264 struct txx9dmac_desc *desc)
267 struct txx9dmac_desc *child;
269 txx9dmac_sync_desc_for_cpu(dc, desc);
271 spin_lock_bh(&dc->lock);
272 list_for_each_entry(child, &desc->tx_list, desc_node)
273 dev_vdbg(chan2dev(&dc->chan),
274 "moving child desc %p to freelist\n",
276 list_splice_init(&desc->tx_list, &dc->free_list);
277 dev_vdbg(chan2dev(&dc->chan), "moving desc %p to freelist\n",
279 list_add(&desc->desc_node, &dc->free_list);
280 spin_unlock_bh(&dc->lock);
284 /*----------------------------------------------------------------------*/
286 static void txx9dmac_dump_regs(struct txx9dmac_chan *dc)
289 dev_err(chan2dev(&dc->chan),
290 " CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x"
291 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
292 (u64)channel64_read_CHAR(dc),
293 channel64_readq(dc, SAR),
294 channel64_readq(dc, DAR),
295 channel64_readl(dc, CNTR),
296 channel64_readl(dc, SAIR),
297 channel64_readl(dc, DAIR),
298 channel64_readl(dc, CCR),
299 channel64_readl(dc, CSR));
301 dev_err(chan2dev(&dc->chan),
302 " CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x"
303 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
304 channel32_readl(dc, CHAR),
305 channel32_readl(dc, SAR),
306 channel32_readl(dc, DAR),
307 channel32_readl(dc, CNTR),
308 channel32_readl(dc, SAIR),
309 channel32_readl(dc, DAIR),
310 channel32_readl(dc, CCR),
311 channel32_readl(dc, CSR));
314 static void txx9dmac_reset_chan(struct txx9dmac_chan *dc)
316 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST);
318 channel64_clear_CHAR(dc);
319 channel_writeq(dc, SAR, 0);
320 channel_writeq(dc, DAR, 0);
322 channel_writel(dc, CHAR, 0);
323 channel_writel(dc, SAR, 0);
324 channel_writel(dc, DAR, 0);
326 channel_writel(dc, CNTR, 0);
327 channel_writel(dc, SAIR, 0);
328 channel_writel(dc, DAIR, 0);
329 channel_writel(dc, CCR, 0);
333 /* Called with dc->lock held and bh disabled */
334 static void txx9dmac_dostart(struct txx9dmac_chan *dc,
335 struct txx9dmac_desc *first)
337 struct txx9dmac_slave *ds = dc->chan.private;
340 dev_vdbg(chan2dev(&dc->chan), "dostart %u %p\n",
341 first->txd.cookie, first);
342 /* ASSERT: channel is idle */
343 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
344 dev_err(chan2dev(&dc->chan),
345 "BUG: Attempted to start non-idle channel\n");
346 txx9dmac_dump_regs(dc);
347 /* The tasklet will hopefully advance the queue... */
352 channel64_writel(dc, CNTR, 0);
353 channel64_writel(dc, CSR, 0xffffffff);
366 channel64_writel(dc, SAIR, sai);
367 channel64_writel(dc, DAIR, dai);
368 /* All 64-bit DMAC supports SMPCHN */
369 channel64_writel(dc, CCR, dc->ccr);
370 /* Writing a non zero value to CHAR will assert XFACT */
371 channel64_write_CHAR(dc, first->txd.phys);
373 channel32_writel(dc, CNTR, 0);
374 channel32_writel(dc, CSR, 0xffffffff);
387 channel32_writel(dc, SAIR, sai);
388 channel32_writel(dc, DAIR, dai);
389 if (txx9_dma_have_SMPCHN()) {
390 channel32_writel(dc, CCR, dc->ccr);
391 /* Writing a non zero value to CHAR will assert XFACT */
392 channel32_writel(dc, CHAR, first->txd.phys);
394 channel32_writel(dc, CHAR, first->txd.phys);
395 channel32_writel(dc, CCR, dc->ccr);
400 /*----------------------------------------------------------------------*/
403 txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
404 struct txx9dmac_desc *desc)
406 dma_async_tx_callback callback;
408 struct dma_async_tx_descriptor *txd = &desc->txd;
409 struct txx9dmac_slave *ds = dc->chan.private;
411 dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
414 dma_cookie_complete(txd);
415 callback = txd->callback;
416 param = txd->callback_param;
418 txx9dmac_sync_desc_for_cpu(dc, desc);
419 list_splice_init(&desc->tx_list, &dc->free_list);
420 list_move(&desc->desc_node, &dc->free_list);
422 dma_descriptor_unmap(txd);
424 * The API requires that no submissions are done from a
425 * callback, so we don't need to drop the lock here
429 dma_run_dependencies(txd);
432 static void txx9dmac_dequeue(struct txx9dmac_chan *dc, struct list_head *list)
434 struct txx9dmac_dev *ddev = dc->ddev;
435 struct txx9dmac_desc *desc;
436 struct txx9dmac_desc *prev = NULL;
438 BUG_ON(!list_empty(list));
440 desc = txx9dmac_first_queued(dc);
442 desc_write_CHAR(dc, prev, desc->txd.phys);
443 dma_sync_single_for_device(chan2parent(&dc->chan),
444 prev->txd.phys, ddev->descsize,
447 prev = txx9dmac_last_child(desc);
448 list_move_tail(&desc->desc_node, list);
449 /* Make chain-completion interrupt happen */
450 if ((desc->txd.flags & DMA_PREP_INTERRUPT) &&
451 !txx9dmac_chan_INTENT(dc))
453 } while (!list_empty(&dc->queue));
456 static void txx9dmac_complete_all(struct txx9dmac_chan *dc)
458 struct txx9dmac_desc *desc, *_desc;
462 * Submit queued descriptors ASAP, i.e. before we go through
463 * the completed ones.
465 list_splice_init(&dc->active_list, &list);
466 if (!list_empty(&dc->queue)) {
467 txx9dmac_dequeue(dc, &dc->active_list);
468 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
471 list_for_each_entry_safe(desc, _desc, &list, desc_node)
472 txx9dmac_descriptor_complete(dc, desc);
475 static void txx9dmac_dump_desc(struct txx9dmac_chan *dc,
476 struct txx9dmac_hwdesc *desc)
479 #ifdef TXX9_DMA_USE_SIMPLE_CHAIN
480 dev_crit(chan2dev(&dc->chan),
481 " desc: ch%#llx s%#llx d%#llx c%#x\n",
482 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
484 dev_crit(chan2dev(&dc->chan),
485 " desc: ch%#llx s%#llx d%#llx c%#x"
486 " si%#x di%#x cc%#x cs%#x\n",
487 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR,
488 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR);
491 struct txx9dmac_hwdesc32 *d = (struct txx9dmac_hwdesc32 *)desc;
492 #ifdef TXX9_DMA_USE_SIMPLE_CHAIN
493 dev_crit(chan2dev(&dc->chan),
494 " desc: ch%#x s%#x d%#x c%#x\n",
495 d->CHAR, d->SAR, d->DAR, d->CNTR);
497 dev_crit(chan2dev(&dc->chan),
498 " desc: ch%#x s%#x d%#x c%#x"
499 " si%#x di%#x cc%#x cs%#x\n",
500 d->CHAR, d->SAR, d->DAR, d->CNTR,
501 d->SAIR, d->DAIR, d->CCR, d->CSR);
506 static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr)
508 struct txx9dmac_desc *bad_desc;
509 struct txx9dmac_desc *child;
513 * The descriptor currently at the head of the active list is
514 * borked. Since we don't have any way to report errors, we'll
515 * just have to scream loudly and try to carry on.
517 dev_crit(chan2dev(&dc->chan), "Abnormal Chain Completion\n");
518 txx9dmac_dump_regs(dc);
520 bad_desc = txx9dmac_first_active(dc);
521 list_del_init(&bad_desc->desc_node);
523 /* Clear all error flags and try to restart the controller */
524 errors = csr & (TXX9_DMA_CSR_ABCHC |
525 TXX9_DMA_CSR_CFERR | TXX9_DMA_CSR_CHERR |
526 TXX9_DMA_CSR_DESERR | TXX9_DMA_CSR_SORERR);
527 channel_writel(dc, CSR, errors);
529 if (list_empty(&dc->active_list) && !list_empty(&dc->queue))
530 txx9dmac_dequeue(dc, &dc->active_list);
531 if (!list_empty(&dc->active_list))
532 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
534 dev_crit(chan2dev(&dc->chan),
535 "Bad descriptor submitted for DMA! (cookie: %d)\n",
536 bad_desc->txd.cookie);
537 txx9dmac_dump_desc(dc, &bad_desc->hwdesc);
538 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
539 txx9dmac_dump_desc(dc, &child->hwdesc);
540 /* Pretend the descriptor completed successfully */
541 txx9dmac_descriptor_complete(dc, bad_desc);
544 static void txx9dmac_scan_descriptors(struct txx9dmac_chan *dc)
547 struct txx9dmac_desc *desc, *_desc;
548 struct txx9dmac_desc *child;
552 chain = channel64_read_CHAR(dc);
553 csr = channel64_readl(dc, CSR);
554 channel64_writel(dc, CSR, csr);
556 chain = channel32_readl(dc, CHAR);
557 csr = channel32_readl(dc, CSR);
558 channel32_writel(dc, CSR, csr);
560 /* For dynamic chain, we should look at XFACT instead of NCHNC */
561 if (!(csr & (TXX9_DMA_CSR_XFACT | TXX9_DMA_CSR_ABCHC))) {
562 /* Everything we've submitted is done */
563 txx9dmac_complete_all(dc);
566 if (!(csr & TXX9_DMA_CSR_CHNEN))
567 chain = 0; /* last descriptor of this chain */
569 dev_vdbg(chan2dev(&dc->chan), "scan_descriptors: char=%#llx\n",
572 list_for_each_entry_safe(desc, _desc, &dc->active_list, desc_node) {
573 if (desc_read_CHAR(dc, desc) == chain) {
574 /* This one is currently in progress */
575 if (csr & TXX9_DMA_CSR_ABCHC)
580 list_for_each_entry(child, &desc->tx_list, desc_node)
581 if (desc_read_CHAR(dc, child) == chain) {
582 /* Currently in progress */
583 if (csr & TXX9_DMA_CSR_ABCHC)
589 * No descriptors so far seem to be in progress, i.e.
590 * this one must be done.
592 txx9dmac_descriptor_complete(dc, desc);
595 if (csr & TXX9_DMA_CSR_ABCHC) {
596 txx9dmac_handle_error(dc, csr);
600 dev_err(chan2dev(&dc->chan),
601 "BUG: All descriptors done, but channel not idle!\n");
603 /* Try to continue after resetting the channel... */
604 txx9dmac_reset_chan(dc);
606 if (!list_empty(&dc->queue)) {
607 txx9dmac_dequeue(dc, &dc->active_list);
608 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
612 static void txx9dmac_chan_tasklet(unsigned long data)
616 struct txx9dmac_chan *dc;
618 dc = (struct txx9dmac_chan *)data;
619 csr = channel_readl(dc, CSR);
620 dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n", csr);
622 spin_lock(&dc->lock);
623 if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
624 TXX9_DMA_CSR_NTRNFC))
625 txx9dmac_scan_descriptors(dc);
626 spin_unlock(&dc->lock);
632 static irqreturn_t txx9dmac_chan_interrupt(int irq, void *dev_id)
634 struct txx9dmac_chan *dc = dev_id;
636 dev_vdbg(chan2dev(&dc->chan), "interrupt: status=%#x\n",
637 channel_readl(dc, CSR));
639 tasklet_schedule(&dc->tasklet);
641 * Just disable the interrupts. We'll turn them back on in the
644 disable_irq_nosync(irq);
649 static void txx9dmac_tasklet(unsigned long data)
653 struct txx9dmac_chan *dc;
655 struct txx9dmac_dev *ddev = (struct txx9dmac_dev *)data;
659 mcr = dma_readl(ddev, MCR);
660 dev_vdbg(ddev->chan[0]->dma.dev, "tasklet: mcr=%x\n", mcr);
661 for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
662 if ((mcr >> (24 + i)) & 0x11) {
664 csr = channel_readl(dc, CSR);
665 dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n",
667 spin_lock(&dc->lock);
668 if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
669 TXX9_DMA_CSR_NTRNFC))
670 txx9dmac_scan_descriptors(dc);
671 spin_unlock(&dc->lock);
679 static irqreturn_t txx9dmac_interrupt(int irq, void *dev_id)
681 struct txx9dmac_dev *ddev = dev_id;
683 dev_vdbg(ddev->chan[0]->dma.dev, "interrupt: status=%#x\n",
684 dma_readl(ddev, MCR));
686 tasklet_schedule(&ddev->tasklet);
688 * Just disable the interrupts. We'll turn them back on in the
691 disable_irq_nosync(irq);
696 /*----------------------------------------------------------------------*/
698 static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx)
700 struct txx9dmac_desc *desc = txd_to_txx9dmac_desc(tx);
701 struct txx9dmac_chan *dc = to_txx9dmac_chan(tx->chan);
704 spin_lock_bh(&dc->lock);
705 cookie = dma_cookie_assign(tx);
707 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u %p\n",
708 desc->txd.cookie, desc);
710 list_add_tail(&desc->desc_node, &dc->queue);
711 spin_unlock_bh(&dc->lock);
716 static struct dma_async_tx_descriptor *
717 txx9dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
718 size_t len, unsigned long flags)
720 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
721 struct txx9dmac_dev *ddev = dc->ddev;
722 struct txx9dmac_desc *desc;
723 struct txx9dmac_desc *first;
724 struct txx9dmac_desc *prev;
728 dev_vdbg(chan2dev(chan), "prep_dma_memcpy d%#llx s%#llx l%#zx f%#lx\n",
729 (u64)dest, (u64)src, len, flags);
731 if (unlikely(!len)) {
732 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
738 for (offset = 0; offset < len; offset += xfer_count) {
739 xfer_count = min_t(size_t, len - offset, TXX9_DMA_MAX_COUNT);
741 * Workaround for ERT-TX49H2-033, ERT-TX49H3-020,
742 * ERT-TX49H4-016 (slightly conservative)
744 if (__is_dmac64(ddev)) {
745 if (xfer_count > 0x100 &&
746 (xfer_count & 0xff) >= 0xfa &&
747 (xfer_count & 0xff) <= 0xff)
750 if (xfer_count > 0x80 &&
751 (xfer_count & 0x7f) >= 0x7e &&
752 (xfer_count & 0x7f) <= 0x7f)
756 desc = txx9dmac_desc_get(dc);
758 txx9dmac_desc_put(dc, first);
762 if (__is_dmac64(ddev)) {
763 desc->hwdesc.SAR = src + offset;
764 desc->hwdesc.DAR = dest + offset;
765 desc->hwdesc.CNTR = xfer_count;
766 txx9dmac_desc_set_nosimple(ddev, desc, 8, 8,
767 dc->ccr | TXX9_DMA_CCR_XFACT);
769 desc->hwdesc32.SAR = src + offset;
770 desc->hwdesc32.DAR = dest + offset;
771 desc->hwdesc32.CNTR = xfer_count;
772 txx9dmac_desc_set_nosimple(ddev, desc, 4, 4,
773 dc->ccr | TXX9_DMA_CCR_XFACT);
777 * The descriptors on tx_list are not reachable from
778 * the dc->queue list or dc->active_list after a
779 * submit. If we put all descriptors on active_list,
780 * calling of callback on the completion will be more
786 desc_write_CHAR(dc, prev, desc->txd.phys);
787 dma_sync_single_for_device(chan2parent(&dc->chan),
788 prev->txd.phys, ddev->descsize,
790 list_add_tail(&desc->desc_node, &first->tx_list);
795 /* Trigger interrupt after last block */
796 if (flags & DMA_PREP_INTERRUPT)
797 txx9dmac_desc_set_INTENT(ddev, prev);
799 desc_write_CHAR(dc, prev, 0);
800 dma_sync_single_for_device(chan2parent(&dc->chan),
801 prev->txd.phys, ddev->descsize,
804 first->txd.flags = flags;
810 static struct dma_async_tx_descriptor *
811 txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
812 unsigned int sg_len, enum dma_transfer_direction direction,
813 unsigned long flags, void *context)
815 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
816 struct txx9dmac_dev *ddev = dc->ddev;
817 struct txx9dmac_slave *ds = chan->private;
818 struct txx9dmac_desc *prev;
819 struct txx9dmac_desc *first;
821 struct scatterlist *sg;
823 dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
825 BUG_ON(!ds || !ds->reg_width);
827 BUG_ON(direction != DMA_MEM_TO_DEV);
829 BUG_ON(direction != DMA_DEV_TO_MEM);
830 if (unlikely(!sg_len))
835 for_each_sg(sgl, sg, sg_len, i) {
836 struct txx9dmac_desc *desc;
840 desc = txx9dmac_desc_get(dc);
842 txx9dmac_desc_put(dc, first);
846 mem = sg_dma_address(sg);
848 if (__is_dmac64(ddev)) {
849 if (direction == DMA_MEM_TO_DEV) {
850 desc->hwdesc.SAR = mem;
851 desc->hwdesc.DAR = ds->tx_reg;
853 desc->hwdesc.SAR = ds->rx_reg;
854 desc->hwdesc.DAR = mem;
856 desc->hwdesc.CNTR = sg_dma_len(sg);
858 if (direction == DMA_MEM_TO_DEV) {
859 desc->hwdesc32.SAR = mem;
860 desc->hwdesc32.DAR = ds->tx_reg;
862 desc->hwdesc32.SAR = ds->rx_reg;
863 desc->hwdesc32.DAR = mem;
865 desc->hwdesc32.CNTR = sg_dma_len(sg);
867 if (direction == DMA_MEM_TO_DEV) {
874 txx9dmac_desc_set_nosimple(ddev, desc, sai, dai,
875 dc->ccr | TXX9_DMA_CCR_XFACT);
880 desc_write_CHAR(dc, prev, desc->txd.phys);
881 dma_sync_single_for_device(chan2parent(&dc->chan),
885 list_add_tail(&desc->desc_node, &first->tx_list);
890 /* Trigger interrupt after last block */
891 if (flags & DMA_PREP_INTERRUPT)
892 txx9dmac_desc_set_INTENT(ddev, prev);
894 desc_write_CHAR(dc, prev, 0);
895 dma_sync_single_for_device(chan2parent(&dc->chan),
896 prev->txd.phys, ddev->descsize,
899 first->txd.flags = flags;
905 static int txx9dmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
908 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
909 struct txx9dmac_desc *desc, *_desc;
912 /* Only supports DMA_TERMINATE_ALL */
913 if (cmd != DMA_TERMINATE_ALL)
916 dev_vdbg(chan2dev(chan), "terminate_all\n");
917 spin_lock_bh(&dc->lock);
919 txx9dmac_reset_chan(dc);
921 /* active_list entries will end up before queued entries */
922 list_splice_init(&dc->queue, &list);
923 list_splice_init(&dc->active_list, &list);
925 spin_unlock_bh(&dc->lock);
927 /* Flush all pending and queued descriptors */
928 list_for_each_entry_safe(desc, _desc, &list, desc_node)
929 txx9dmac_descriptor_complete(dc, desc);
934 static enum dma_status
935 txx9dmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
936 struct dma_tx_state *txstate)
938 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
941 ret = dma_cookie_status(chan, cookie, txstate);
942 if (ret == DMA_COMPLETE)
945 spin_lock_bh(&dc->lock);
946 txx9dmac_scan_descriptors(dc);
947 spin_unlock_bh(&dc->lock);
949 return dma_cookie_status(chan, cookie, txstate);
952 static void txx9dmac_chain_dynamic(struct txx9dmac_chan *dc,
953 struct txx9dmac_desc *prev)
955 struct txx9dmac_dev *ddev = dc->ddev;
956 struct txx9dmac_desc *desc;
959 prev = txx9dmac_last_child(prev);
960 txx9dmac_dequeue(dc, &list);
961 desc = list_entry(list.next, struct txx9dmac_desc, desc_node);
962 desc_write_CHAR(dc, prev, desc->txd.phys);
963 dma_sync_single_for_device(chan2parent(&dc->chan),
964 prev->txd.phys, ddev->descsize,
967 if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) &&
968 channel_read_CHAR(dc) == prev->txd.phys)
969 /* Restart chain DMA */
970 channel_write_CHAR(dc, desc->txd.phys);
971 list_splice_tail(&list, &dc->active_list);
974 static void txx9dmac_issue_pending(struct dma_chan *chan)
976 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
978 spin_lock_bh(&dc->lock);
980 if (!list_empty(&dc->active_list))
981 txx9dmac_scan_descriptors(dc);
982 if (!list_empty(&dc->queue)) {
983 if (list_empty(&dc->active_list)) {
984 txx9dmac_dequeue(dc, &dc->active_list);
985 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
986 } else if (txx9_dma_have_SMPCHN()) {
987 struct txx9dmac_desc *prev = txx9dmac_last_active(dc);
989 if (!(prev->txd.flags & DMA_PREP_INTERRUPT) ||
990 txx9dmac_chan_INTENT(dc))
991 txx9dmac_chain_dynamic(dc, prev);
995 spin_unlock_bh(&dc->lock);
998 static int txx9dmac_alloc_chan_resources(struct dma_chan *chan)
1000 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1001 struct txx9dmac_slave *ds = chan->private;
1002 struct txx9dmac_desc *desc;
1005 dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
1007 /* ASSERT: channel is idle */
1008 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
1009 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1013 dma_cookie_init(chan);
1015 dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;
1016 txx9dmac_chan_set_SMPCHN(dc);
1017 if (!txx9_dma_have_SMPCHN() || (dc->ccr & TXX9_DMA_CCR_SMPCHN))
1018 dc->ccr |= TXX9_DMA_CCR_INTENC;
1019 if (chan->device->device_prep_dma_memcpy) {
1022 dc->ccr |= TXX9_DMA_CCR_XFSZ_X8;
1025 (ds->tx_reg && ds->rx_reg) || (!ds->tx_reg && !ds->rx_reg))
1027 dc->ccr |= TXX9_DMA_CCR_EXTRQ |
1028 TXX9_DMA_CCR_XFSZ(__ffs(ds->reg_width));
1029 txx9dmac_chan_set_INTENT(dc);
1032 spin_lock_bh(&dc->lock);
1033 i = dc->descs_allocated;
1034 while (dc->descs_allocated < TXX9_DMA_INITIAL_DESC_COUNT) {
1035 spin_unlock_bh(&dc->lock);
1037 desc = txx9dmac_desc_alloc(dc, GFP_KERNEL);
1039 dev_info(chan2dev(chan),
1040 "only allocated %d descriptors\n", i);
1041 spin_lock_bh(&dc->lock);
1044 txx9dmac_desc_put(dc, desc);
1046 spin_lock_bh(&dc->lock);
1047 i = ++dc->descs_allocated;
1049 spin_unlock_bh(&dc->lock);
1051 dev_dbg(chan2dev(chan),
1052 "alloc_chan_resources allocated %d descriptors\n", i);
1057 static void txx9dmac_free_chan_resources(struct dma_chan *chan)
1059 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1060 struct txx9dmac_dev *ddev = dc->ddev;
1061 struct txx9dmac_desc *desc, *_desc;
1064 dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
1065 dc->descs_allocated);
1067 /* ASSERT: channel is idle */
1068 BUG_ON(!list_empty(&dc->active_list));
1069 BUG_ON(!list_empty(&dc->queue));
1070 BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT);
1072 spin_lock_bh(&dc->lock);
1073 list_splice_init(&dc->free_list, &list);
1074 dc->descs_allocated = 0;
1075 spin_unlock_bh(&dc->lock);
1077 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1078 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1079 dma_unmap_single(chan2parent(chan), desc->txd.phys,
1080 ddev->descsize, DMA_TO_DEVICE);
1084 dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
1087 /*----------------------------------------------------------------------*/
1089 static void txx9dmac_off(struct txx9dmac_dev *ddev)
1091 dma_writel(ddev, MCR, 0);
1095 static int __init txx9dmac_chan_probe(struct platform_device *pdev)
1097 struct txx9dmac_chan_platform_data *cpdata =
1098 dev_get_platdata(&pdev->dev);
1099 struct platform_device *dmac_dev = cpdata->dmac_dev;
1100 struct txx9dmac_platform_data *pdata = dev_get_platdata(&dmac_dev->dev);
1101 struct txx9dmac_chan *dc;
1103 int ch = pdev->id % TXX9_DMA_MAX_NR_CHANNELS;
1106 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1110 dc->dma.dev = &pdev->dev;
1111 dc->dma.device_alloc_chan_resources = txx9dmac_alloc_chan_resources;
1112 dc->dma.device_free_chan_resources = txx9dmac_free_chan_resources;
1113 dc->dma.device_control = txx9dmac_control;
1114 dc->dma.device_tx_status = txx9dmac_tx_status;
1115 dc->dma.device_issue_pending = txx9dmac_issue_pending;
1116 if (pdata && pdata->memcpy_chan == ch) {
1117 dc->dma.device_prep_dma_memcpy = txx9dmac_prep_dma_memcpy;
1118 dma_cap_set(DMA_MEMCPY, dc->dma.cap_mask);
1120 dc->dma.device_prep_slave_sg = txx9dmac_prep_slave_sg;
1121 dma_cap_set(DMA_SLAVE, dc->dma.cap_mask);
1122 dma_cap_set(DMA_PRIVATE, dc->dma.cap_mask);
1125 INIT_LIST_HEAD(&dc->dma.channels);
1126 dc->ddev = platform_get_drvdata(dmac_dev);
1127 if (dc->ddev->irq < 0) {
1128 irq = platform_get_irq(pdev, 0);
1131 tasklet_init(&dc->tasklet, txx9dmac_chan_tasklet,
1134 err = devm_request_irq(&pdev->dev, dc->irq,
1135 txx9dmac_chan_interrupt, 0, dev_name(&pdev->dev), dc);
1140 dc->ddev->chan[ch] = dc;
1141 dc->chan.device = &dc->dma;
1142 list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
1143 dma_cookie_init(&dc->chan);
1146 dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
1148 dc->ch_regs = &__txx9dmac_regs32(dc->ddev)->CHAN[ch];
1149 spin_lock_init(&dc->lock);
1151 INIT_LIST_HEAD(&dc->active_list);
1152 INIT_LIST_HEAD(&dc->queue);
1153 INIT_LIST_HEAD(&dc->free_list);
1155 txx9dmac_reset_chan(dc);
1157 platform_set_drvdata(pdev, dc);
1159 err = dma_async_device_register(&dc->dma);
1162 dev_dbg(&pdev->dev, "TXx9 DMA Channel (dma%d%s%s)\n",
1164 dma_has_cap(DMA_MEMCPY, dc->dma.cap_mask) ? " memcpy" : "",
1165 dma_has_cap(DMA_SLAVE, dc->dma.cap_mask) ? " slave" : "");
1170 static int txx9dmac_chan_remove(struct platform_device *pdev)
1172 struct txx9dmac_chan *dc = platform_get_drvdata(pdev);
1174 dma_async_device_unregister(&dc->dma);
1176 tasklet_kill(&dc->tasklet);
1177 dc->ddev->chan[pdev->id % TXX9_DMA_MAX_NR_CHANNELS] = NULL;
1181 static int __init txx9dmac_probe(struct platform_device *pdev)
1183 struct txx9dmac_platform_data *pdata = dev_get_platdata(&pdev->dev);
1184 struct resource *io;
1185 struct txx9dmac_dev *ddev;
1189 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1193 ddev = devm_kzalloc(&pdev->dev, sizeof(*ddev), GFP_KERNEL);
1197 if (!devm_request_mem_region(&pdev->dev, io->start, resource_size(io),
1198 dev_name(&pdev->dev)))
1201 ddev->regs = devm_ioremap(&pdev->dev, io->start, resource_size(io));
1204 ddev->have_64bit_regs = pdata->have_64bit_regs;
1205 if (__is_dmac64(ddev))
1206 ddev->descsize = sizeof(struct txx9dmac_hwdesc);
1208 ddev->descsize = sizeof(struct txx9dmac_hwdesc32);
1210 /* force dma off, just in case */
1213 ddev->irq = platform_get_irq(pdev, 0);
1214 if (ddev->irq >= 0) {
1215 tasklet_init(&ddev->tasklet, txx9dmac_tasklet,
1216 (unsigned long)ddev);
1217 err = devm_request_irq(&pdev->dev, ddev->irq,
1218 txx9dmac_interrupt, 0, dev_name(&pdev->dev), ddev);
1223 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1224 if (pdata && pdata->memcpy_chan >= 0)
1225 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1226 dma_writel(ddev, MCR, mcr);
1228 platform_set_drvdata(pdev, ddev);
1232 static int txx9dmac_remove(struct platform_device *pdev)
1234 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1238 tasklet_kill(&ddev->tasklet);
1242 static void txx9dmac_shutdown(struct platform_device *pdev)
1244 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1249 static int txx9dmac_suspend_noirq(struct device *dev)
1251 struct platform_device *pdev = to_platform_device(dev);
1252 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1258 static int txx9dmac_resume_noirq(struct device *dev)
1260 struct platform_device *pdev = to_platform_device(dev);
1261 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1262 struct txx9dmac_platform_data *pdata = dev_get_platdata(&pdev->dev);
1265 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1266 if (pdata && pdata->memcpy_chan >= 0)
1267 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1268 dma_writel(ddev, MCR, mcr);
1273 static const struct dev_pm_ops txx9dmac_dev_pm_ops = {
1274 .suspend_noirq = txx9dmac_suspend_noirq,
1275 .resume_noirq = txx9dmac_resume_noirq,
1278 static struct platform_driver txx9dmac_chan_driver = {
1279 .remove = txx9dmac_chan_remove,
1281 .name = "txx9dmac-chan",
1285 static struct platform_driver txx9dmac_driver = {
1286 .remove = txx9dmac_remove,
1287 .shutdown = txx9dmac_shutdown,
1290 .pm = &txx9dmac_dev_pm_ops,
1294 static int __init txx9dmac_init(void)
1298 rc = platform_driver_probe(&txx9dmac_driver, txx9dmac_probe);
1300 rc = platform_driver_probe(&txx9dmac_chan_driver,
1301 txx9dmac_chan_probe);
1303 platform_driver_unregister(&txx9dmac_driver);
1307 module_init(txx9dmac_init);
1309 static void __exit txx9dmac_exit(void)
1311 platform_driver_unregister(&txx9dmac_chan_driver);
1312 platform_driver_unregister(&txx9dmac_driver);
1314 module_exit(txx9dmac_exit);
1316 MODULE_LICENSE("GPL");
1317 MODULE_DESCRIPTION("TXx9 DMA Controller driver");
1318 MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
1319 MODULE_ALIAS("platform:txx9dmac");
1320 MODULE_ALIAS("platform:txx9dmac-chan");