2 * Copyright (c) 2011 Jamie Iles
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * All enquiries to support@picochip.com
10 #include <linux/acpi.h>
11 #include <linux/gpio/driver.h>
12 /* FIXME: for gpio_get_value(), replace this with direct register read */
13 #include <linux/gpio.h>
14 #include <linux/err.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/module.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/property.h>
27 #include <linux/spinlock.h>
28 #include <linux/platform_data/gpio-dwapb.h>
29 #include <linux/slab.h>
33 #define GPIO_SWPORTA_DR 0x00
34 #define GPIO_SWPORTA_DDR 0x04
35 #define GPIO_SWPORTB_DR 0x0c
36 #define GPIO_SWPORTB_DDR 0x10
37 #define GPIO_SWPORTC_DR 0x18
38 #define GPIO_SWPORTC_DDR 0x1c
39 #define GPIO_SWPORTD_DR 0x24
40 #define GPIO_SWPORTD_DDR 0x28
41 #define GPIO_INTEN 0x30
42 #define GPIO_INTMASK 0x34
43 #define GPIO_INTTYPE_LEVEL 0x38
44 #define GPIO_INT_POLARITY 0x3c
45 #define GPIO_INTSTATUS 0x40
46 #define GPIO_PORTA_DEBOUNCE 0x48
47 #define GPIO_PORTA_EOI 0x4c
48 #define GPIO_EXT_PORTA 0x50
49 #define GPIO_EXT_PORTB 0x54
50 #define GPIO_EXT_PORTC 0x58
51 #define GPIO_EXT_PORTD 0x5c
53 #define DWAPB_MAX_PORTS 4
54 #define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA)
55 #define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
56 #define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)
60 #ifdef CONFIG_PM_SLEEP
61 /* Store GPIO context across system-wide suspend/resume transitions */
62 struct dwapb_context {
74 struct dwapb_gpio_port {
77 struct dwapb_gpio *gpio;
78 #ifdef CONFIG_PM_SLEEP
79 struct dwapb_context *ctx;
87 struct dwapb_gpio_port *ports;
88 unsigned int nr_ports;
89 struct irq_domain *domain;
92 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
94 struct gpio_chip *gc = &gpio->ports[0].gc;
95 void __iomem *reg_base = gpio->regs;
97 return gc->read_reg(reg_base + offset);
100 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
103 struct gpio_chip *gc = &gpio->ports[0].gc;
104 void __iomem *reg_base = gpio->regs;
106 gc->write_reg(reg_base + offset, val);
109 static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
111 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
112 struct dwapb_gpio *gpio = port->gpio;
114 return irq_find_mapping(gpio->domain, offset);
117 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
119 u32 v = dwapb_read(gpio, GPIO_INT_POLARITY);
121 if (gpio_get_value(gpio->ports[0].gc.base + offs))
126 dwapb_write(gpio, GPIO_INT_POLARITY, v);
129 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
131 u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);
132 u32 ret = irq_status;
135 int hwirq = fls(irq_status) - 1;
136 int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
138 generic_handle_irq(gpio_irq);
139 irq_status &= ~BIT(hwirq);
141 if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
142 == IRQ_TYPE_EDGE_BOTH)
143 dwapb_toggle_trigger(gpio, hwirq);
149 static void dwapb_irq_handler(struct irq_desc *desc)
151 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
152 struct irq_chip *chip = irq_desc_get_chip(desc);
157 chip->irq_eoi(irq_desc_get_irq_data(desc));
160 static void dwapb_irq_enable(struct irq_data *d)
162 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
163 struct dwapb_gpio *gpio = igc->private;
164 struct gpio_chip *gc = &gpio->ports[0].gc;
168 spin_lock_irqsave(&gc->bgpio_lock, flags);
169 val = dwapb_read(gpio, GPIO_INTEN);
170 val |= BIT(d->hwirq);
171 dwapb_write(gpio, GPIO_INTEN, val);
172 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
175 static void dwapb_irq_disable(struct irq_data *d)
177 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
178 struct dwapb_gpio *gpio = igc->private;
179 struct gpio_chip *gc = &gpio->ports[0].gc;
183 spin_lock_irqsave(&gc->bgpio_lock, flags);
184 val = dwapb_read(gpio, GPIO_INTEN);
185 val &= ~BIT(d->hwirq);
186 dwapb_write(gpio, GPIO_INTEN, val);
187 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
190 static int dwapb_irq_reqres(struct irq_data *d)
192 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
193 struct dwapb_gpio *gpio = igc->private;
194 struct gpio_chip *gc = &gpio->ports[0].gc;
196 if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) {
197 dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
204 static void dwapb_irq_relres(struct irq_data *d)
206 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
207 struct dwapb_gpio *gpio = igc->private;
208 struct gpio_chip *gc = &gpio->ports[0].gc;
210 gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
213 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
215 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
216 struct dwapb_gpio *gpio = igc->private;
217 struct gpio_chip *gc = &gpio->ports[0].gc;
219 unsigned long level, polarity, flags;
221 if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
222 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
225 spin_lock_irqsave(&gc->bgpio_lock, flags);
226 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
227 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
230 case IRQ_TYPE_EDGE_BOTH:
232 dwapb_toggle_trigger(gpio, bit);
234 case IRQ_TYPE_EDGE_RISING:
236 polarity |= BIT(bit);
238 case IRQ_TYPE_EDGE_FALLING:
240 polarity &= ~BIT(bit);
242 case IRQ_TYPE_LEVEL_HIGH:
244 polarity |= BIT(bit);
246 case IRQ_TYPE_LEVEL_LOW:
248 polarity &= ~BIT(bit);
252 irq_setup_alt_chip(d, type);
254 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
255 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
256 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
261 static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
262 unsigned offset, unsigned debounce)
264 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
265 struct dwapb_gpio *gpio = port->gpio;
266 unsigned long flags, val_deb;
267 unsigned long mask = gc->pin2mask(gc, offset);
269 spin_lock_irqsave(&gc->bgpio_lock, flags);
271 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
273 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
275 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
277 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
282 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
283 unsigned long config)
287 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
290 debounce = pinconf_to_config_argument(config);
291 return dwapb_gpio_set_debounce(gc, offset, debounce);
294 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
297 struct dwapb_gpio *gpio = dev_id;
299 worked = dwapb_do_irq(gpio);
301 return worked ? IRQ_HANDLED : IRQ_NONE;
304 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
305 struct dwapb_gpio_port *port,
306 struct dwapb_port_property *pp)
308 struct gpio_chip *gc = &port->gc;
309 struct fwnode_handle *fwnode = pp->fwnode;
310 struct irq_chip_generic *irq_gc = NULL;
311 unsigned int hwirq, ngpio = gc->ngpio;
312 struct irq_chip_type *ct;
315 gpio->domain = irq_domain_create_linear(fwnode, ngpio,
316 &irq_generic_chip_ops, gpio);
320 err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
321 "gpio-dwapb", handle_level_irq,
323 IRQ_GC_INIT_NESTED_LOCK);
325 dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
326 irq_domain_remove(gpio->domain);
331 irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
333 irq_domain_remove(gpio->domain);
338 irq_gc->reg_base = gpio->regs;
339 irq_gc->private = gpio;
341 for (i = 0; i < 2; i++) {
342 ct = &irq_gc->chip_types[i];
343 ct->chip.irq_ack = irq_gc_ack_set_bit;
344 ct->chip.irq_mask = irq_gc_mask_set_bit;
345 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
346 ct->chip.irq_set_type = dwapb_irq_set_type;
347 ct->chip.irq_enable = dwapb_irq_enable;
348 ct->chip.irq_disable = dwapb_irq_disable;
349 ct->chip.irq_request_resources = dwapb_irq_reqres;
350 ct->chip.irq_release_resources = dwapb_irq_relres;
351 ct->regs.ack = GPIO_PORTA_EOI;
352 ct->regs.mask = GPIO_INTMASK;
353 ct->type = IRQ_TYPE_LEVEL_MASK;
356 irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
357 irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
358 irq_gc->chip_types[1].handler = handle_edge_irq;
360 if (!pp->irq_shared) {
361 irq_set_chained_handler_and_data(pp->irq, dwapb_irq_handler,
365 * Request a shared IRQ since where MFD would have devices
366 * using the same irq pin
368 err = devm_request_irq(gpio->dev, pp->irq,
369 dwapb_irq_handler_mfd,
370 IRQF_SHARED, "gpio-dwapb-mfd", gpio);
372 dev_err(gpio->dev, "error requesting IRQ\n");
373 irq_domain_remove(gpio->domain);
379 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
380 irq_create_mapping(gpio->domain, hwirq);
382 port->gc.to_irq = dwapb_gpio_to_irq;
385 static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
387 struct dwapb_gpio_port *port = &gpio->ports[0];
388 struct gpio_chip *gc = &port->gc;
389 unsigned int ngpio = gc->ngpio;
390 irq_hw_number_t hwirq;
395 for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
396 irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
398 irq_domain_remove(gpio->domain);
402 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
403 struct dwapb_port_property *pp,
406 struct dwapb_gpio_port *port;
407 void __iomem *dat, *set, *dirout;
410 port = &gpio->ports[offs];
414 #ifdef CONFIG_PM_SLEEP
415 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
420 dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE);
421 set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE);
422 dirout = gpio->regs + GPIO_SWPORTA_DDR +
423 (pp->idx * GPIO_SWPORT_DDR_SIZE);
425 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
428 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
433 #ifdef CONFIG_OF_GPIO
434 port->gc.of_node = to_of_node(pp->fwnode);
436 port->gc.ngpio = pp->ngpio;
437 port->gc.base = pp->gpio_base;
439 /* Only port A support debounce */
441 port->gc.set_config = dwapb_gpio_set_config;
444 dwapb_configure_irqs(gpio, port, pp);
446 err = gpiochip_add_data(&port->gc, port);
448 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
451 port->is_registered = true;
453 /* Add GPIO-signaled ACPI event support */
455 acpi_gpiochip_request_interrupts(&port->gc);
460 static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
464 for (m = 0; m < gpio->nr_ports; ++m)
465 if (gpio->ports[m].is_registered)
466 gpiochip_remove(&gpio->ports[m].gc);
469 static struct dwapb_platform_data *
470 dwapb_gpio_get_pdata(struct device *dev)
472 struct fwnode_handle *fwnode;
473 struct dwapb_platform_data *pdata;
474 struct dwapb_port_property *pp;
478 nports = device_get_child_node_count(dev);
480 return ERR_PTR(-ENODEV);
482 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
484 return ERR_PTR(-ENOMEM);
486 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
487 if (!pdata->properties)
488 return ERR_PTR(-ENOMEM);
490 pdata->nports = nports;
493 device_for_each_child_node(dev, fwnode) {
494 pp = &pdata->properties[i++];
497 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
498 pp->idx >= DWAPB_MAX_PORTS) {
500 "missing/invalid port index for port%d\n", i);
501 fwnode_handle_put(fwnode);
502 return ERR_PTR(-EINVAL);
505 if (fwnode_property_read_u32(fwnode, "snps,nr-gpios",
508 "failed to get number of gpios for port%d\n",
514 * Only port A can provide interrupts in all configurations of
517 if (dev->of_node && pp->idx == 0 &&
518 fwnode_property_read_bool(fwnode,
519 "interrupt-controller")) {
520 pp->irq = irq_of_parse_and_map(to_of_node(fwnode), 0);
522 dev_warn(dev, "no irq for port%d\n", pp->idx);
525 if (has_acpi_companion(dev) && pp->idx == 0)
526 pp->irq = platform_get_irq(to_platform_device(dev), 0);
528 pp->irq_shared = false;
535 static int dwapb_gpio_probe(struct platform_device *pdev)
538 struct resource *res;
539 struct dwapb_gpio *gpio;
541 struct device *dev = &pdev->dev;
542 struct dwapb_platform_data *pdata = dev_get_platdata(dev);
545 pdata = dwapb_gpio_get_pdata(dev);
547 return PTR_ERR(pdata);
553 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
557 gpio->dev = &pdev->dev;
558 gpio->nr_ports = pdata->nports;
560 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
561 sizeof(*gpio->ports), GFP_KERNEL);
565 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
566 gpio->regs = devm_ioremap_resource(&pdev->dev, res);
567 if (IS_ERR(gpio->regs))
568 return PTR_ERR(gpio->regs);
570 for (i = 0; i < gpio->nr_ports; i++) {
571 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
575 platform_set_drvdata(pdev, gpio);
580 dwapb_gpio_unregister(gpio);
581 dwapb_irq_teardown(gpio);
586 static int dwapb_gpio_remove(struct platform_device *pdev)
588 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
590 dwapb_gpio_unregister(gpio);
591 dwapb_irq_teardown(gpio);
596 static const struct of_device_id dwapb_of_match[] = {
597 { .compatible = "snps,dw-apb-gpio" },
600 MODULE_DEVICE_TABLE(of, dwapb_of_match);
602 static const struct acpi_device_id dwapb_acpi_match[] = {
607 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
609 #ifdef CONFIG_PM_SLEEP
610 static int dwapb_gpio_suspend(struct device *dev)
612 struct platform_device *pdev = to_platform_device(dev);
613 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
614 struct gpio_chip *gc = &gpio->ports[0].gc;
618 spin_lock_irqsave(&gc->bgpio_lock, flags);
619 for (i = 0; i < gpio->nr_ports; i++) {
621 unsigned int idx = gpio->ports[i].idx;
622 struct dwapb_context *ctx = gpio->ports[i].ctx;
626 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
627 ctx->dir = dwapb_read(gpio, offset);
629 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
630 ctx->data = dwapb_read(gpio, offset);
632 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
633 ctx->ext = dwapb_read(gpio, offset);
635 /* Only port A can provide interrupts */
637 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
638 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
639 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
640 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
641 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
643 /* Mask out interrupts */
644 dwapb_write(gpio, GPIO_INTMASK, 0xffffffff);
647 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
652 static int dwapb_gpio_resume(struct device *dev)
654 struct platform_device *pdev = to_platform_device(dev);
655 struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
656 struct gpio_chip *gc = &gpio->ports[0].gc;
660 spin_lock_irqsave(&gc->bgpio_lock, flags);
661 for (i = 0; i < gpio->nr_ports; i++) {
663 unsigned int idx = gpio->ports[i].idx;
664 struct dwapb_context *ctx = gpio->ports[i].ctx;
668 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
669 dwapb_write(gpio, offset, ctx->data);
671 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
672 dwapb_write(gpio, offset, ctx->dir);
674 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
675 dwapb_write(gpio, offset, ctx->ext);
677 /* Only port A can provide interrupts */
679 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
680 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
681 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
682 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
683 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
685 /* Clear out spurious interrupts */
686 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
689 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
695 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
698 static struct platform_driver dwapb_gpio_driver = {
700 .name = "gpio-dwapb",
701 .pm = &dwapb_gpio_pm_ops,
702 .of_match_table = of_match_ptr(dwapb_of_match),
703 .acpi_match_table = ACPI_PTR(dwapb_acpi_match),
705 .probe = dwapb_gpio_probe,
706 .remove = dwapb_gpio_remove,
709 module_platform_driver(dwapb_gpio_driver);
711 MODULE_LICENSE("GPL");
712 MODULE_AUTHOR("Jamie Iles");
713 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");