2 * Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
4 * 2013 (c) Aeroflex Gaisler AB
6 * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
9 * Full documentation of the GRGPIO core can be found here:
10 * http://www.gaisler.com/products/grlib/grip.pdf
12 * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
13 * information on open firmware properties.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Contributors: Andreas Larsson <andreas@gaisler.com>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/spinlock.h>
29 #include <linux/of_gpio.h>
30 #include <linux/of_platform.h>
31 #include <linux/gpio.h>
32 #include <linux/slab.h>
33 #include <linux/err.h>
34 #include <linux/basic_mmio_gpio.h>
35 #include <linux/interrupt.h>
36 #include <linux/irq.h>
37 #include <linux/irqdomain.h>
39 #define GRGPIO_MAX_NGPIO 32
41 #define GRGPIO_DATA 0x00
42 #define GRGPIO_OUTPUT 0x04
43 #define GRGPIO_DIR 0x08
44 #define GRGPIO_IMASK 0x0c
45 #define GRGPIO_IPOL 0x10
46 #define GRGPIO_IEDGE 0x14
47 #define GRGPIO_BYPASS 0x18
48 #define GRGPIO_IMAP_BASE 0x20
50 /* Structure for an irq of the core - called an underlying irq */
52 u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
53 u8 uirq; /* Underlying irq of the gpio driver */
57 * Structure for an irq of a gpio line handed out by this driver. The index is
58 * used to map to the corresponding underlying irq.
61 s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
62 u8 irq; /* irq for the gpio line */
66 struct bgpio_chip bgc;
70 u32 imask; /* irq mask shadow register */
73 * The grgpio core can have multiple "underlying" irqs. The gpio lines
74 * can be mapped to any one or none of these underlying irqs
75 * independently of each other. This driver sets up an irq domain and
76 * hands out separate irqs to each gpio line
78 struct irq_domain *domain;
81 * This array contains information on each underlying irq, each
82 * irq of the grgpio core itself.
84 struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];
87 * This array contains information for each gpio line on the irqs
88 * obtains from this driver. An index value of -1 for a certain gpio
89 * line indicates that the line has no irq. Otherwise the index connects
90 * the irq to the underlying irq by pointing into the uirqs array.
92 struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
95 static inline struct grgpio_priv *grgpio_gc_to_priv(struct gpio_chip *gc)
97 struct bgpio_chip *bgc = to_bgpio_chip(gc);
99 return container_of(bgc, struct grgpio_priv, bgc);
102 static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
105 struct bgpio_chip *bgc = &priv->bgc;
106 unsigned long mask = bgc->pin2mask(bgc, offset);
109 spin_lock_irqsave(&bgc->lock, flags);
114 priv->imask &= ~mask;
115 bgc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
117 spin_unlock_irqrestore(&bgc->lock, flags);
120 static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
122 struct grgpio_priv *priv = grgpio_gc_to_priv(gc);
124 if (offset >= gc->ngpio)
127 if (priv->lirqs[offset].index < 0)
130 return irq_create_mapping(priv->domain, offset);
133 /* -------------------- IRQ chip functions -------------------- */
135 static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
137 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
139 u32 mask = BIT(d->hwirq);
146 case IRQ_TYPE_LEVEL_LOW:
150 case IRQ_TYPE_LEVEL_HIGH:
154 case IRQ_TYPE_EDGE_FALLING:
158 case IRQ_TYPE_EDGE_RISING:
166 spin_lock_irqsave(&priv->bgc.lock, flags);
168 ipol = priv->bgc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
169 iedge = priv->bgc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
171 priv->bgc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
172 priv->bgc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
174 spin_unlock_irqrestore(&priv->bgc.lock, flags);
179 static void grgpio_irq_mask(struct irq_data *d)
181 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
182 int offset = d->hwirq;
184 grgpio_set_imask(priv, offset, 0);
187 static void grgpio_irq_unmask(struct irq_data *d)
189 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
190 int offset = d->hwirq;
192 grgpio_set_imask(priv, offset, 1);
195 static struct irq_chip grgpio_irq_chip = {
197 .irq_mask = grgpio_irq_mask,
198 .irq_unmask = grgpio_irq_unmask,
199 .irq_set_type = grgpio_irq_set_type,
202 static irqreturn_t grgpio_irq_handler(int irq, void *dev)
204 struct grgpio_priv *priv = dev;
205 int ngpio = priv->bgc.gc.ngpio;
210 spin_lock_irqsave(&priv->bgc.lock, flags);
213 * For each gpio line, call its interrupt handler if it its underlying
214 * irq matches the current irq that is handled.
216 for (i = 0; i < ngpio; i++) {
217 struct grgpio_lirq *lirq = &priv->lirqs[i];
219 if (priv->imask & BIT(i) && lirq->index >= 0 &&
220 priv->uirqs[lirq->index].uirq == irq) {
221 generic_handle_irq(lirq->irq);
226 spin_unlock_irqrestore(&priv->bgc.lock, flags);
229 dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
235 * This function will be called as a consequence of the call to
236 * irq_create_mapping in grgpio_to_irq
238 static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
239 irq_hw_number_t hwirq)
241 struct grgpio_priv *priv = d->host_data;
242 struct grgpio_lirq *lirq;
243 struct grgpio_uirq *uirq;
251 lirq = &priv->lirqs[offset];
255 dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
258 spin_lock_irqsave(&priv->bgc.lock, flags);
260 /* Request underlying irq if not already requested */
262 uirq = &priv->uirqs[lirq->index];
263 if (uirq->refcnt == 0) {
264 ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
265 dev_name(priv->dev), priv);
268 "Could not request underlying irq %d\n",
271 spin_unlock_irqrestore(&priv->bgc.lock, flags);
278 spin_unlock_irqrestore(&priv->bgc.lock, flags);
281 irq_set_chip_data(irq, priv);
282 irq_set_chip_and_handler(irq, &grgpio_irq_chip,
284 irq_clear_status_flags(irq, IRQ_NOREQUEST);
286 set_irq_flags(irq, IRQF_VALID);
288 irq_set_noprobe(irq);
294 static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
296 struct grgpio_priv *priv = d->host_data;
298 struct grgpio_lirq *lirq;
299 struct grgpio_uirq *uirq;
301 int ngpio = priv->bgc.gc.ngpio;
305 set_irq_flags(irq, 0);
307 irq_set_chip_and_handler(irq, NULL, NULL);
308 irq_set_chip_data(irq, NULL);
310 spin_lock_irqsave(&priv->bgc.lock, flags);
312 /* Free underlying irq if last user unmapped */
314 for (i = 0; i < ngpio; i++) {
315 lirq = &priv->lirqs[i];
316 if (lirq->irq == irq) {
317 grgpio_set_imask(priv, i, 0);
326 uirq = &priv->uirqs[lirq->index];
328 if (uirq->refcnt == 0)
329 free_irq(uirq->uirq, priv);
332 spin_unlock_irqrestore(&priv->bgc.lock, flags);
335 static const struct irq_domain_ops grgpio_irq_domain_ops = {
336 .map = grgpio_irq_map,
337 .unmap = grgpio_irq_unmap,
340 /* ------------------------------------------------------------ */
342 static int grgpio_probe(struct platform_device *ofdev)
344 struct device_node *np = ofdev->dev.of_node;
346 struct gpio_chip *gc;
347 struct bgpio_chip *bgc;
348 struct grgpio_priv *priv;
349 struct resource *res;
356 priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
360 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
361 regs = devm_ioremap_resource(&ofdev->dev, res);
363 return PTR_ERR(regs);
366 err = bgpio_init(bgc, &ofdev->dev, 4, regs + GRGPIO_DATA,
367 regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
368 BGPIOF_BIG_ENDIAN_BYTE_ORDER);
370 dev_err(&ofdev->dev, "bgpio_init() failed\n");
375 priv->imask = bgc->read_reg(regs + GRGPIO_IMASK);
376 priv->dev = &ofdev->dev;
380 gc->owner = THIS_MODULE;
381 gc->to_irq = grgpio_to_irq;
382 gc->label = np->full_name;
385 err = of_property_read_u32(np, "nbits", &prop);
386 if (err || prop <= 0 || prop > GRGPIO_MAX_NGPIO) {
387 gc->ngpio = GRGPIO_MAX_NGPIO;
389 "No or invalid nbits property: assume %d\n", gc->ngpio);
395 * The irqmap contains the index values indicating which underlying irq,
396 * if anyone, is connected to that line
398 irqmap = (s32 *)of_get_property(np, "irqmap", &size);
400 if (size < gc->ngpio) {
402 "irqmap shorter than ngpio (%d < %d)\n",
407 priv->domain = irq_domain_add_linear(np, gc->ngpio,
408 &grgpio_irq_domain_ops,
411 dev_err(&ofdev->dev, "Could not add irq domain\n");
415 for (i = 0; i < gc->ngpio; i++) {
416 struct grgpio_lirq *lirq;
419 lirq = &priv->lirqs[i];
420 lirq->index = irqmap[i];
425 ret = platform_get_irq(ofdev, lirq->index);
428 * Continue without irq functionality for that
432 "Failed to get irq for offset %d\n", i);
435 priv->uirqs[lirq->index].uirq = ret;
439 platform_set_drvdata(ofdev, priv);
441 err = gpiochip_add(gc);
443 dev_err(&ofdev->dev, "Could not add gpiochip\n");
445 irq_domain_remove(priv->domain);
449 dev_info(&ofdev->dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
450 priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off");
455 static int grgpio_remove(struct platform_device *ofdev)
457 struct grgpio_priv *priv = platform_get_drvdata(ofdev);
462 spin_lock_irqsave(&priv->bgc.lock, flags);
465 for (i = 0; i < GRGPIO_MAX_NGPIO; i++) {
466 if (priv->uirqs[i].refcnt != 0) {
473 gpiochip_remove(&priv->bgc.gc);
476 irq_domain_remove(priv->domain);
479 spin_unlock_irqrestore(&priv->bgc.lock, flags);
484 static const struct of_device_id grgpio_match[] = {
485 {.name = "GAISLER_GPIO"},
490 MODULE_DEVICE_TABLE(of, grgpio_match);
492 static struct platform_driver grgpio_driver = {
495 .of_match_table = grgpio_match,
497 .probe = grgpio_probe,
498 .remove = grgpio_remove,
500 module_platform_driver(grgpio_driver);
502 MODULE_AUTHOR("Aeroflex Gaisler AB.");
503 MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
504 MODULE_LICENSE("GPL");