2 * Copyright (C) 2008, 2009 Provigent Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
10 * Data sheet: ARM DDI 0190B, September 2000
12 #include <linux/spinlock.h>
13 #include <linux/errno.h>
14 #include <linux/module.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/irqchip/chained_irq.h>
19 #include <linux/bitops.h>
20 #include <linux/gpio.h>
21 #include <linux/device.h>
22 #include <linux/amba/bus.h>
23 #include <linux/amba/pl061.h>
24 #include <linux/slab.h>
25 #include <linux/pinctrl/consumer.h>
37 #define PL061_GPIO_NR 8
40 struct pl061_context_save_regs {
58 struct pl061_context_save_regs csave_regs;
62 static int pl061_gpio_request(struct gpio_chip *gc, unsigned offset)
65 * Map back to global GPIO space and request muxing, the direction
66 * parameter does not matter for this controller.
68 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
69 int gpio = gc->base + offset;
71 if (chip->uses_pinctrl)
72 return pinctrl_request_gpio(gpio);
76 static void pl061_gpio_free(struct gpio_chip *gc, unsigned offset)
78 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
79 int gpio = gc->base + offset;
81 if (chip->uses_pinctrl)
82 pinctrl_free_gpio(gpio);
85 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
87 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
89 unsigned char gpiodir;
91 if (offset >= gc->ngpio)
94 spin_lock_irqsave(&chip->lock, flags);
95 gpiodir = readb(chip->base + GPIODIR);
96 gpiodir &= ~(BIT(offset));
97 writeb(gpiodir, chip->base + GPIODIR);
98 spin_unlock_irqrestore(&chip->lock, flags);
103 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
106 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
108 unsigned char gpiodir;
110 if (offset >= gc->ngpio)
113 spin_lock_irqsave(&chip->lock, flags);
114 writeb(!!value << offset, chip->base + (BIT(offset + 2)));
115 gpiodir = readb(chip->base + GPIODIR);
116 gpiodir |= BIT(offset);
117 writeb(gpiodir, chip->base + GPIODIR);
120 * gpio value is set again, because pl061 doesn't allow to set value of
121 * a gpio pin before configuring it in OUT mode.
123 writeb(!!value << offset, chip->base + (BIT(offset + 2)));
124 spin_unlock_irqrestore(&chip->lock, flags);
129 static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
131 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
133 return !!readb(chip->base + (BIT(offset + 2)));
136 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
138 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
140 writeb(!!value << offset, chip->base + (BIT(offset + 2)));
143 static int pl061_irq_type(struct irq_data *d, unsigned trigger)
145 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
146 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
147 int offset = irqd_to_hwirq(d);
149 u8 gpiois, gpioibe, gpioiev;
150 u8 bit = BIT(offset);
152 if (offset < 0 || offset >= PL061_GPIO_NR)
155 spin_lock_irqsave(&chip->lock, flags);
157 gpioiev = readb(chip->base + GPIOIEV);
158 gpiois = readb(chip->base + GPIOIS);
159 gpioibe = readb(chip->base + GPIOIBE);
161 if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
162 (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
165 "trying to configure line %d for both level and edge "
166 "detection, choose one!\n",
171 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
172 bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
174 /* Disable edge detection */
176 /* Enable level detection */
178 /* Select polarity */
184 dev_dbg(gc->dev, "line %d: IRQ on %s level\n",
186 polarity ? "HIGH" : "LOW");
187 } else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
188 /* Disable level detection */
190 /* Select both edges, setting this makes GPIOEV be ignored */
193 dev_dbg(gc->dev, "line %d: IRQ on both edges\n", offset);
194 } else if ((trigger & IRQ_TYPE_EDGE_RISING) ||
195 (trigger & IRQ_TYPE_EDGE_FALLING)) {
196 bool rising = trigger & IRQ_TYPE_EDGE_RISING;
198 /* Disable level detection */
200 /* Clear detection on both edges */
208 dev_dbg(gc->dev, "line %d: IRQ on %s edge\n",
210 rising ? "RISING" : "FALLING");
212 /* No trigger: disable everything */
216 dev_warn(gc->dev, "no trigger selected for line %d\n",
220 writeb(gpiois, chip->base + GPIOIS);
221 writeb(gpioibe, chip->base + GPIOIBE);
222 writeb(gpioiev, chip->base + GPIOIEV);
224 spin_unlock_irqrestore(&chip->lock, flags);
229 static void pl061_irq_handler(struct irq_desc *desc)
231 unsigned long pending;
233 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
234 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
235 struct irq_chip *irqchip = irq_desc_get_chip(desc);
237 chained_irq_enter(irqchip, desc);
239 pending = readb(chip->base + GPIOMIS);
240 writeb(pending, chip->base + GPIOIC);
242 for_each_set_bit(offset, &pending, PL061_GPIO_NR)
243 generic_handle_irq(irq_find_mapping(gc->irqdomain,
247 chained_irq_exit(irqchip, desc);
250 static void pl061_irq_mask(struct irq_data *d)
252 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
253 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
254 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
257 spin_lock(&chip->lock);
258 gpioie = readb(chip->base + GPIOIE) & ~mask;
259 writeb(gpioie, chip->base + GPIOIE);
260 spin_unlock(&chip->lock);
263 static void pl061_irq_unmask(struct irq_data *d)
265 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
266 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
267 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
270 spin_lock(&chip->lock);
271 gpioie = readb(chip->base + GPIOIE) | mask;
272 writeb(gpioie, chip->base + GPIOIE);
273 spin_unlock(&chip->lock);
276 static struct irq_chip pl061_irqchip = {
278 .irq_mask = pl061_irq_mask,
279 .irq_unmask = pl061_irq_unmask,
280 .irq_set_type = pl061_irq_type,
283 static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
285 struct device *dev = &adev->dev;
286 struct pl061_platform_data *pdata = dev_get_platdata(dev);
287 struct pl061_gpio *chip;
288 int ret, irq, i, irq_base;
290 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
295 chip->gc.base = pdata->gpio_base;
296 irq_base = pdata->irq_base;
298 dev_err(&adev->dev, "invalid IRQ base in pdata\n");
306 chip->base = devm_ioremap_resource(dev, &adev->res);
307 if (IS_ERR(chip->base))
308 return PTR_ERR(chip->base);
310 spin_lock_init(&chip->lock);
311 if (of_property_read_bool(dev->of_node, "gpio-ranges"))
312 chip->uses_pinctrl = true;
314 chip->gc.request = pl061_gpio_request;
315 chip->gc.free = pl061_gpio_free;
316 chip->gc.direction_input = pl061_direction_input;
317 chip->gc.direction_output = pl061_direction_output;
318 chip->gc.get = pl061_get_value;
319 chip->gc.set = pl061_set_value;
320 chip->gc.ngpio = PL061_GPIO_NR;
321 chip->gc.label = dev_name(dev);
323 chip->gc.owner = THIS_MODULE;
325 ret = gpiochip_add(&chip->gc);
332 writeb(0, chip->base + GPIOIE); /* disable irqs */
335 dev_err(&adev->dev, "invalid IRQ\n");
339 ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip,
340 irq_base, handle_simple_irq,
343 dev_info(&adev->dev, "could not add irqchip\n");
346 gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip,
347 irq, pl061_irq_handler);
349 for (i = 0; i < PL061_GPIO_NR; i++) {
351 if (pdata->directions & (BIT(i)))
352 pl061_direction_output(&chip->gc, i,
353 pdata->values & (BIT(i)));
355 pl061_direction_input(&chip->gc, i);
359 amba_set_drvdata(adev, chip);
360 dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
367 static int pl061_suspend(struct device *dev)
369 struct pl061_gpio *chip = dev_get_drvdata(dev);
372 chip->csave_regs.gpio_data = 0;
373 chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
374 chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
375 chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
376 chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
377 chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
379 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
380 if (chip->csave_regs.gpio_dir & (BIT(offset)))
381 chip->csave_regs.gpio_data |=
382 pl061_get_value(&chip->gc, offset) << offset;
388 static int pl061_resume(struct device *dev)
390 struct pl061_gpio *chip = dev_get_drvdata(dev);
393 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
394 if (chip->csave_regs.gpio_dir & (BIT(offset)))
395 pl061_direction_output(&chip->gc, offset,
396 chip->csave_regs.gpio_data &
399 pl061_direction_input(&chip->gc, offset);
402 writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
403 writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
404 writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
405 writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
410 static const struct dev_pm_ops pl061_dev_pm_ops = {
411 .suspend = pl061_suspend,
412 .resume = pl061_resume,
413 .freeze = pl061_suspend,
414 .restore = pl061_resume,
418 static struct amba_id pl061_ids[] = {
426 MODULE_DEVICE_TABLE(amba, pl061_ids);
428 static struct amba_driver pl061_gpio_driver = {
430 .name = "pl061_gpio",
432 .pm = &pl061_dev_pm_ops,
435 .id_table = pl061_ids,
436 .probe = pl061_probe,
439 static int __init pl061_gpio_init(void)
441 return amba_driver_register(&pl061_gpio_driver);
443 module_init(pl061_gpio_init);
445 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
446 MODULE_DESCRIPTION("PL061 GPIO driver");
447 MODULE_LICENSE("GPL");