2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * SAMSUNG - GPIOlib support
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/of_address.h>
30 #ifdef CONFIG_ARCH_S3C24XX
31 #include <linux/platform_data/gpio-samsung-s3c24xx.h>
33 #ifdef CONFIG_ARCH_S3C64XX
34 #include <linux/platform_data/gpio-samsung-s3c64xx.h>
39 #include <mach/hardware.h>
41 #include <mach/regs-gpio.h>
44 #include <plat/gpio-core.h>
45 #include <plat/gpio-cfg.h>
46 #include <plat/gpio-cfg-helpers.h>
49 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
50 unsigned int off, samsung_gpio_pull_t pull)
52 void __iomem *reg = chip->base + 0x08;
56 pup = __raw_readl(reg);
59 __raw_writel(pup, reg);
64 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
67 void __iomem *reg = chip->base + 0x08;
69 u32 pup = __raw_readl(reg);
74 return (__force samsung_gpio_pull_t)pup;
77 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
78 unsigned int off, samsung_gpio_pull_t pull)
81 case S3C_GPIO_PULL_NONE:
84 case S3C_GPIO_PULL_UP:
87 case S3C_GPIO_PULL_DOWN:
91 return samsung_gpio_setpull_updown(chip, off, pull);
94 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
97 samsung_gpio_pull_t pull;
99 pull = samsung_gpio_getpull_updown(chip, off);
103 pull = S3C_GPIO_PULL_UP;
107 pull = S3C_GPIO_PULL_NONE;
110 pull = S3C_GPIO_PULL_DOWN;
117 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
118 unsigned int off, samsung_gpio_pull_t pull,
119 samsung_gpio_pull_t updown)
121 void __iomem *reg = chip->base + 0x08;
122 u32 pup = __raw_readl(reg);
126 else if (pull == S3C_GPIO_PULL_NONE)
131 __raw_writel(pup, reg);
135 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
137 samsung_gpio_pull_t updown)
139 void __iomem *reg = chip->base + 0x08;
140 u32 pup = __raw_readl(reg);
143 return pup ? S3C_GPIO_PULL_NONE : updown;
146 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
149 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
152 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
153 unsigned int off, samsung_gpio_pull_t pull)
155 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
158 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
161 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
164 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
165 unsigned int off, samsung_gpio_pull_t pull)
167 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
171 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
172 * @chip: The gpio chip that is being configured.
173 * @off: The offset for the GPIO being configured.
174 * @cfg: The configuration value to set.
176 * This helper deal with the GPIO cases where the control register
177 * has two bits of configuration per gpio, which have the following
181 * 1x = special function
184 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
185 unsigned int off, unsigned int cfg)
187 void __iomem *reg = chip->base;
188 unsigned int shift = off * 2;
191 if (samsung_gpio_is_cfg_special(cfg)) {
199 con = __raw_readl(reg);
200 con &= ~(0x3 << shift);
202 __raw_writel(con, reg);
208 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
209 * @chip: The gpio chip that is being configured.
210 * @off: The offset for the GPIO being configured.
212 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
213 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
214 * S3C_GPIO_SPECIAL() macro.
217 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
222 con = __raw_readl(chip->base);
226 /* this conversion works for IN and OUT as well as special mode */
227 return S3C_GPIO_SPECIAL(con);
231 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
232 * @chip: The gpio chip that is being configured.
233 * @off: The offset for the GPIO being configured.
234 * @cfg: The configuration value to set.
236 * This helper deal with the GPIO cases where the control register has 4 bits
237 * of control per GPIO, generally in the form of:
240 * others = Special functions (dependent on bank)
242 * Note, since the code to deal with the case where there are two control
243 * registers instead of one, we do not have a separate set of functions for
247 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
248 unsigned int off, unsigned int cfg)
250 void __iomem *reg = chip->base;
251 unsigned int shift = (off & 7) * 4;
254 if (off < 8 && chip->chip.ngpio > 8)
257 if (samsung_gpio_is_cfg_special(cfg)) {
262 con = __raw_readl(reg);
263 con &= ~(0xf << shift);
265 __raw_writel(con, reg);
271 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
272 * @chip: The gpio chip that is being configured.
273 * @off: The offset for the GPIO being configured.
275 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
276 * register setting into a value the software can use, such as could be passed
277 * to samsung_gpio_setcfg_4bit().
279 * @sa samsung_gpio_getcfg_2bit
282 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
285 void __iomem *reg = chip->base;
286 unsigned int shift = (off & 7) * 4;
289 if (off < 8 && chip->chip.ngpio > 8)
292 con = __raw_readl(reg);
296 /* this conversion works for IN and OUT as well as special mode */
297 return S3C_GPIO_SPECIAL(con);
300 #ifdef CONFIG_PLAT_S3C24XX
302 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
303 * @chip: The gpio chip that is being configured.
304 * @off: The offset for the GPIO being configured.
305 * @cfg: The configuration value to set.
307 * This helper deal with the GPIO cases where the control register
308 * has one bit of configuration for the gpio, where setting the bit
309 * means the pin is in special function mode and unset means output.
312 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
313 unsigned int off, unsigned int cfg)
315 void __iomem *reg = chip->base;
316 unsigned int shift = off;
319 if (samsung_gpio_is_cfg_special(cfg)) {
322 /* Map output to 0, and SFN2 to 1 */
330 con = __raw_readl(reg);
331 con &= ~(0x1 << shift);
333 __raw_writel(con, reg);
339 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
340 * @chip: The gpio chip that is being configured.
341 * @off: The offset for the GPIO being configured.
343 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
344 * GPIO configuration value.
346 * @sa samsung_gpio_getcfg_2bit
347 * @sa samsung_gpio_getcfg_4bit
350 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
355 con = __raw_readl(chip->base);
360 return S3C_GPIO_SFN(con);
364 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
365 static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
366 unsigned int off, unsigned int cfg)
368 void __iomem *reg = chip->base;
379 shift = (off & 7) * 4;
383 shift = ((off + 1) & 7) * 4;
386 shift = ((off + 1) & 7) * 4;
390 if (samsung_gpio_is_cfg_special(cfg)) {
395 con = __raw_readl(reg);
396 con &= ~(0xf << shift);
398 __raw_writel(con, reg);
404 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
407 for (; nr_chips > 0; nr_chips--, chipcfg++) {
408 if (!chipcfg->set_config)
409 chipcfg->set_config = samsung_gpio_setcfg_4bit;
410 if (!chipcfg->get_config)
411 chipcfg->get_config = samsung_gpio_getcfg_4bit;
412 if (!chipcfg->set_pull)
413 chipcfg->set_pull = samsung_gpio_setpull_updown;
414 if (!chipcfg->get_pull)
415 chipcfg->get_pull = samsung_gpio_getpull_updown;
419 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
420 .set_config = samsung_gpio_setcfg_2bit,
421 .get_config = samsung_gpio_getcfg_2bit,
424 #ifdef CONFIG_PLAT_S3C24XX
425 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
426 .set_config = s3c24xx_gpio_setcfg_abank,
427 .get_config = s3c24xx_gpio_getcfg_abank,
431 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
432 static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
434 .set_config = s5p64x0_gpio_setcfg_rbank,
435 .get_config = samsung_gpio_getcfg_4bit,
436 .set_pull = samsung_gpio_setpull_updown,
437 .get_pull = samsung_gpio_getpull_updown,
441 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
456 .set_config = samsung_gpio_setcfg_2bit,
457 .get_config = samsung_gpio_getcfg_2bit,
461 .set_config = samsung_gpio_setcfg_2bit,
462 .get_config = samsung_gpio_getcfg_2bit,
466 .set_config = samsung_gpio_setcfg_2bit,
467 .get_config = samsung_gpio_getcfg_2bit,
470 .set_config = samsung_gpio_setcfg_2bit,
471 .get_config = samsung_gpio_getcfg_2bit,
476 * Default routines for controlling GPIO, based on the original S3C24XX
477 * GPIO functions which deal with the case where each gpio bank of the
478 * chip is as following:
480 * base + 0x00: Control register, 2 bits per gpio
481 * gpio n: 2 bits starting at (2*n)
482 * 00 = input, 01 = output, others mean special-function
483 * base + 0x04: Data register, 1 bit per gpio
487 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
489 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
490 void __iomem *base = ourchip->base;
494 samsung_gpio_lock(ourchip, flags);
496 con = __raw_readl(base + 0x00);
497 con &= ~(3 << (offset * 2));
499 __raw_writel(con, base + 0x00);
501 samsung_gpio_unlock(ourchip, flags);
505 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
506 unsigned offset, int value)
508 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
509 void __iomem *base = ourchip->base;
514 samsung_gpio_lock(ourchip, flags);
516 dat = __raw_readl(base + 0x04);
517 dat &= ~(1 << offset);
520 __raw_writel(dat, base + 0x04);
522 con = __raw_readl(base + 0x00);
523 con &= ~(3 << (offset * 2));
524 con |= 1 << (offset * 2);
526 __raw_writel(con, base + 0x00);
527 __raw_writel(dat, base + 0x04);
529 samsung_gpio_unlock(ourchip, flags);
534 * The samsung_gpiolib_4bit routines are to control the gpio banks where
535 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
538 * base + 0x00: Control register, 4 bits per gpio
539 * gpio n: 4 bits starting at (4*n)
540 * 0000 = input, 0001 = output, others mean special-function
541 * base + 0x04: Data register, 1 bit per gpio
544 * Note, since the data register is one bit per gpio and is at base + 0x4
545 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
546 * state of the output.
549 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
552 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
553 void __iomem *base = ourchip->base;
556 con = __raw_readl(base + GPIOCON_OFF);
557 if (ourchip->bitmap_gpio_int & BIT(offset))
558 con |= 0xf << con_4bit_shift(offset);
560 con &= ~(0xf << con_4bit_shift(offset));
561 __raw_writel(con, base + GPIOCON_OFF);
563 pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
568 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
569 unsigned int offset, int value)
571 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
572 void __iomem *base = ourchip->base;
576 con = __raw_readl(base + GPIOCON_OFF);
577 con &= ~(0xf << con_4bit_shift(offset));
578 con |= 0x1 << con_4bit_shift(offset);
580 dat = __raw_readl(base + GPIODAT_OFF);
585 dat &= ~(1 << offset);
587 __raw_writel(dat, base + GPIODAT_OFF);
588 __raw_writel(con, base + GPIOCON_OFF);
589 __raw_writel(dat, base + GPIODAT_OFF);
591 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
597 * The next set of routines are for the case where the GPIO configuration
598 * registers are 4 bits per GPIO but there is more than one register (the
599 * bank has more than 8 GPIOs.
601 * This case is the similar to the 4 bit case, but the registers are as
604 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
605 * gpio n: 4 bits starting at (4*n)
606 * 0000 = input, 0001 = output, others mean special-function
607 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
608 * gpio n: 4 bits starting at (4*n)
609 * 0000 = input, 0001 = output, others mean special-function
610 * base + 0x08: Data register, 1 bit per gpio
613 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
614 * routines we store the 'base + 0x4' address so that these routines see
615 * the data register at ourchip->base + 0x04.
618 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
621 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
622 void __iomem *base = ourchip->base;
623 void __iomem *regcon = base;
631 con = __raw_readl(regcon);
632 con &= ~(0xf << con_4bit_shift(offset));
633 __raw_writel(con, regcon);
635 pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
640 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
641 unsigned int offset, int value)
643 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
644 void __iomem *base = ourchip->base;
645 void __iomem *regcon = base;
648 unsigned con_offset = offset;
655 con = __raw_readl(regcon);
656 con &= ~(0xf << con_4bit_shift(con_offset));
657 con |= 0x1 << con_4bit_shift(con_offset);
659 dat = __raw_readl(base + GPIODAT_OFF);
664 dat &= ~(1 << offset);
666 __raw_writel(dat, base + GPIODAT_OFF);
667 __raw_writel(con, regcon);
668 __raw_writel(dat, base + GPIODAT_OFF);
670 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
675 #ifdef CONFIG_PLAT_S3C24XX
676 /* The next set of routines are for the case of s3c24xx bank a */
678 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
683 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
684 unsigned offset, int value)
686 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
687 void __iomem *base = ourchip->base;
692 local_irq_save(flags);
694 con = __raw_readl(base + 0x00);
695 dat = __raw_readl(base + 0x04);
697 dat &= ~(1 << offset);
701 __raw_writel(dat, base + 0x04);
703 con &= ~(1 << offset);
705 __raw_writel(con, base + 0x00);
706 __raw_writel(dat, base + 0x04);
708 local_irq_restore(flags);
713 /* The next set of routines are for the case of s5p64x0 bank r */
715 static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
718 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
719 void __iomem *base = ourchip->base;
720 void __iomem *regcon = base;
740 samsung_gpio_lock(ourchip, flags);
742 con = __raw_readl(regcon);
743 con &= ~(0xf << con_4bit_shift(offset));
744 __raw_writel(con, regcon);
746 samsung_gpio_unlock(ourchip, flags);
751 static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
752 unsigned int offset, int value)
754 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
755 void __iomem *base = ourchip->base;
756 void __iomem *regcon = base;
760 unsigned con_offset = offset;
762 switch (con_offset) {
778 samsung_gpio_lock(ourchip, flags);
780 con = __raw_readl(regcon);
781 con &= ~(0xf << con_4bit_shift(con_offset));
782 con |= 0x1 << con_4bit_shift(con_offset);
784 dat = __raw_readl(base + GPIODAT_OFF);
788 dat &= ~(1 << offset);
790 __raw_writel(con, regcon);
791 __raw_writel(dat, base + GPIODAT_OFF);
793 samsung_gpio_unlock(ourchip, flags);
798 static void samsung_gpiolib_set(struct gpio_chip *chip,
799 unsigned offset, int value)
801 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
802 void __iomem *base = ourchip->base;
806 samsung_gpio_lock(ourchip, flags);
808 dat = __raw_readl(base + 0x04);
809 dat &= ~(1 << offset);
812 __raw_writel(dat, base + 0x04);
814 samsung_gpio_unlock(ourchip, flags);
817 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
819 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
822 val = __raw_readl(ourchip->base + 0x04);
830 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
831 * for use with the configuration calls, and other parts of the s3c gpiolib
834 * Not all s3c support code will need this, as some configurations of cpu
835 * may only support one or two different configuration options and have an
836 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
837 * the machine support file should provide its own samsung_gpiolib_getchip()
838 * and any other necessary functions.
841 #ifdef CONFIG_S3C_GPIO_TRACK
842 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
844 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
849 gpn = chip->chip.base;
850 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
851 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
852 s3c_gpios[gpn] = chip;
855 #endif /* CONFIG_S3C_GPIO_TRACK */
858 * samsung_gpiolib_add() - add the Samsung gpio_chip.
859 * @chip: The chip to register
861 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
862 * information and makes the necessary alterations for the platform and
863 * notes the information for use with the configuration systems and any
864 * other parts of the system.
867 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
869 struct gpio_chip *gc = &chip->chip;
876 spin_lock_init(&chip->lock);
878 if (!gc->direction_input)
879 gc->direction_input = samsung_gpiolib_2bit_input;
880 if (!gc->direction_output)
881 gc->direction_output = samsung_gpiolib_2bit_output;
883 gc->set = samsung_gpiolib_set;
885 gc->get = samsung_gpiolib_get;
888 if (chip->pm != NULL) {
889 if (!chip->pm->save || !chip->pm->resume)
890 pr_err("gpio: %s has missing PM functions\n",
893 pr_err("gpio: %s has no PM function\n", gc->label);
896 /* gpiochip_add() prints own failure message on error. */
897 ret = gpiochip_add(gc);
899 s3c_gpiolib_track(chip);
902 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
903 int nr_chips, void __iomem *base)
906 struct gpio_chip *gc = &chip->chip;
908 for (i = 0 ; i < nr_chips; i++, chip++) {
909 /* skip banks not present on SoC */
910 if (chip->chip.base >= S3C_GPIO_END)
914 chip->config = &s3c24xx_gpiocfg_default;
916 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
917 if ((base != NULL) && (chip->base == NULL))
918 chip->base = base + ((i) * 0x10);
920 if (!gc->direction_input)
921 gc->direction_input = samsung_gpiolib_2bit_input;
922 if (!gc->direction_output)
923 gc->direction_output = samsung_gpiolib_2bit_output;
925 samsung_gpiolib_add(chip);
929 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
930 int nr_chips, void __iomem *base,
935 for (i = 0 ; i < nr_chips; i++, chip++) {
936 chip->chip.direction_input = samsung_gpiolib_2bit_input;
937 chip->chip.direction_output = samsung_gpiolib_2bit_output;
940 chip->config = &samsung_gpio_cfgs[7];
942 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
943 if ((base != NULL) && (chip->base == NULL))
944 chip->base = base + ((i) * offset);
946 samsung_gpiolib_add(chip);
951 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
952 * @chip: The gpio chip that is being configured.
953 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
955 * This helper deal with the GPIO cases where the control register has 4 bits
956 * of control per GPIO, generally in the form of:
959 * others = Special functions (dependent on bank)
961 * Note, since the code to deal with the case where there are two control
962 * registers instead of one, we do not have a separate set of function
963 * (samsung_gpiolib_add_4bit2_chips)for each case.
966 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
967 int nr_chips, void __iomem *base)
971 for (i = 0 ; i < nr_chips; i++, chip++) {
972 chip->chip.direction_input = samsung_gpiolib_4bit_input;
973 chip->chip.direction_output = samsung_gpiolib_4bit_output;
976 chip->config = &samsung_gpio_cfgs[2];
978 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
979 if ((base != NULL) && (chip->base == NULL))
980 chip->base = base + ((i) * 0x20);
982 chip->bitmap_gpio_int = 0;
984 samsung_gpiolib_add(chip);
988 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
991 for (; nr_chips > 0; nr_chips--, chip++) {
992 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
993 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
996 chip->config = &samsung_gpio_cfgs[2];
998 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1000 samsung_gpiolib_add(chip);
1004 static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1007 for (; nr_chips > 0; nr_chips--, chip++) {
1008 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1009 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1012 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1014 samsung_gpiolib_add(chip);
1018 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1020 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
1022 return samsung_chip->irq_base + offset;
1025 #ifdef CONFIG_PLAT_S3C24XX
1026 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1029 if (soc_is_s3c2412())
1030 return IRQ_EINT0_2412 + offset;
1032 return IRQ_EINT0 + offset;
1036 return IRQ_EINT4 + offset - 4;
1042 #ifdef CONFIG_ARCH_S3C64XX
1043 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
1045 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
1048 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
1050 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
1054 struct samsung_gpio_chip s3c24xx_gpios[] = {
1055 #ifdef CONFIG_PLAT_S3C24XX
1057 .config = &s3c24xx_gpiocfg_banka,
1059 .base = S3C2410_GPA(0),
1060 .owner = THIS_MODULE,
1063 .direction_input = s3c24xx_gpiolib_banka_input,
1064 .direction_output = s3c24xx_gpiolib_banka_output,
1068 .base = S3C2410_GPB(0),
1069 .owner = THIS_MODULE,
1075 .base = S3C2410_GPC(0),
1076 .owner = THIS_MODULE,
1082 .base = S3C2410_GPD(0),
1083 .owner = THIS_MODULE,
1089 .base = S3C2410_GPE(0),
1091 .owner = THIS_MODULE,
1096 .base = S3C2410_GPF(0),
1097 .owner = THIS_MODULE,
1100 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
1103 .irq_base = IRQ_EINT8,
1105 .base = S3C2410_GPG(0),
1106 .owner = THIS_MODULE,
1109 .to_irq = samsung_gpiolib_to_irq,
1113 .base = S3C2410_GPH(0),
1114 .owner = THIS_MODULE,
1119 /* GPIOS for the S3C2443 and later devices. */
1121 .base = S3C2440_GPJCON,
1123 .base = S3C2410_GPJ(0),
1124 .owner = THIS_MODULE,
1129 .base = S3C2443_GPKCON,
1131 .base = S3C2410_GPK(0),
1132 .owner = THIS_MODULE,
1137 .base = S3C2443_GPLCON,
1139 .base = S3C2410_GPL(0),
1140 .owner = THIS_MODULE,
1145 .base = S3C2443_GPMCON,
1147 .base = S3C2410_GPM(0),
1148 .owner = THIS_MODULE,
1157 * GPIO bank summary:
1159 * Bank GPIOs Style SlpCon ExtInt Group
1165 * F 16 2Bit Yes 4 [1]
1167 * H 10 4Bit[2] Yes 6
1168 * I 16 2Bit Yes None
1169 * J 12 2Bit Yes None
1170 * K 16 4Bit[2] No None
1171 * L 15 4Bit[2] No None
1172 * M 6 4Bit No IRQ_EINT
1173 * N 16 2Bit No IRQ_EINT
1178 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1179 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1182 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1183 #ifdef CONFIG_ARCH_S3C64XX
1186 .base = S3C64XX_GPA(0),
1187 .ngpio = S3C64XX_GPIO_A_NR,
1192 .base = S3C64XX_GPB(0),
1193 .ngpio = S3C64XX_GPIO_B_NR,
1198 .base = S3C64XX_GPC(0),
1199 .ngpio = S3C64XX_GPIO_C_NR,
1204 .base = S3C64XX_GPD(0),
1205 .ngpio = S3C64XX_GPIO_D_NR,
1209 .config = &samsung_gpio_cfgs[0],
1211 .base = S3C64XX_GPE(0),
1212 .ngpio = S3C64XX_GPIO_E_NR,
1216 .base = S3C64XX_GPG_BASE,
1218 .base = S3C64XX_GPG(0),
1219 .ngpio = S3C64XX_GPIO_G_NR,
1223 .base = S3C64XX_GPM_BASE,
1224 .config = &samsung_gpio_cfgs[1],
1226 .base = S3C64XX_GPM(0),
1227 .ngpio = S3C64XX_GPIO_M_NR,
1229 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1235 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1236 #ifdef CONFIG_ARCH_S3C64XX
1238 .base = S3C64XX_GPH_BASE + 0x4,
1240 .base = S3C64XX_GPH(0),
1241 .ngpio = S3C64XX_GPIO_H_NR,
1245 .base = S3C64XX_GPK_BASE + 0x4,
1246 .config = &samsung_gpio_cfgs[0],
1248 .base = S3C64XX_GPK(0),
1249 .ngpio = S3C64XX_GPIO_K_NR,
1253 .base = S3C64XX_GPL_BASE + 0x4,
1254 .config = &samsung_gpio_cfgs[1],
1256 .base = S3C64XX_GPL(0),
1257 .ngpio = S3C64XX_GPIO_L_NR,
1259 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1265 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1266 #ifdef CONFIG_ARCH_S3C64XX
1268 .base = S3C64XX_GPF_BASE,
1269 .config = &samsung_gpio_cfgs[6],
1271 .base = S3C64XX_GPF(0),
1272 .ngpio = S3C64XX_GPIO_F_NR,
1276 .config = &samsung_gpio_cfgs[7],
1278 .base = S3C64XX_GPI(0),
1279 .ngpio = S3C64XX_GPIO_I_NR,
1283 .config = &samsung_gpio_cfgs[7],
1285 .base = S3C64XX_GPJ(0),
1286 .ngpio = S3C64XX_GPIO_J_NR,
1290 .config = &samsung_gpio_cfgs[6],
1292 .base = S3C64XX_GPO(0),
1293 .ngpio = S3C64XX_GPIO_O_NR,
1297 .config = &samsung_gpio_cfgs[6],
1299 .base = S3C64XX_GPP(0),
1300 .ngpio = S3C64XX_GPIO_P_NR,
1304 .config = &samsung_gpio_cfgs[6],
1306 .base = S3C64XX_GPQ(0),
1307 .ngpio = S3C64XX_GPIO_Q_NR,
1311 .base = S3C64XX_GPN_BASE,
1312 .irq_base = IRQ_EINT(0),
1313 .config = &samsung_gpio_cfgs[5],
1315 .base = S3C64XX_GPN(0),
1316 .ngpio = S3C64XX_GPIO_N_NR,
1318 .to_irq = samsung_gpiolib_to_irq,
1325 * S5P6440 GPIO bank summary:
1327 * Bank GPIOs Style SlpCon ExtInt Group
1331 * F 2 2Bit Yes 4 [1]
1333 * H 10 4Bit[2] Yes 6
1334 * I 16 2Bit Yes None
1335 * J 12 2Bit Yes None
1336 * N 16 2Bit No IRQ_EINT
1338 * R 15 4Bit[2] Yes 8
1341 static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1342 #ifdef CONFIG_CPU_S5P6440
1345 .base = S5P6440_GPA(0),
1346 .ngpio = S5P6440_GPIO_A_NR,
1351 .base = S5P6440_GPB(0),
1352 .ngpio = S5P6440_GPIO_B_NR,
1357 .base = S5P6440_GPC(0),
1358 .ngpio = S5P6440_GPIO_C_NR,
1362 .base = S5P64X0_GPG_BASE,
1364 .base = S5P6440_GPG(0),
1365 .ngpio = S5P6440_GPIO_G_NR,
1372 static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1373 #ifdef CONFIG_CPU_S5P6440
1375 .base = S5P64X0_GPH_BASE + 0x4,
1377 .base = S5P6440_GPH(0),
1378 .ngpio = S5P6440_GPIO_H_NR,
1385 static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1386 #ifdef CONFIG_CPU_S5P6440
1388 .base = S5P64X0_GPR_BASE + 0x4,
1389 .config = &s5p64x0_gpio_cfg_rbank,
1391 .base = S5P6440_GPR(0),
1392 .ngpio = S5P6440_GPIO_R_NR,
1399 static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1400 #ifdef CONFIG_CPU_S5P6440
1402 .base = S5P64X0_GPF_BASE,
1403 .config = &samsung_gpio_cfgs[6],
1405 .base = S5P6440_GPF(0),
1406 .ngpio = S5P6440_GPIO_F_NR,
1410 .base = S5P64X0_GPI_BASE,
1411 .config = &samsung_gpio_cfgs[4],
1413 .base = S5P6440_GPI(0),
1414 .ngpio = S5P6440_GPIO_I_NR,
1418 .base = S5P64X0_GPJ_BASE,
1419 .config = &samsung_gpio_cfgs[4],
1421 .base = S5P6440_GPJ(0),
1422 .ngpio = S5P6440_GPIO_J_NR,
1426 .base = S5P64X0_GPN_BASE,
1427 .config = &samsung_gpio_cfgs[5],
1429 .base = S5P6440_GPN(0),
1430 .ngpio = S5P6440_GPIO_N_NR,
1434 .base = S5P64X0_GPP_BASE,
1435 .config = &samsung_gpio_cfgs[6],
1437 .base = S5P6440_GPP(0),
1438 .ngpio = S5P6440_GPIO_P_NR,
1446 * S5P6450 GPIO bank summary:
1448 * Bank GPIOs Style SlpCon ExtInt Group
1454 * G 14 4Bit[2] Yes 5
1455 * H 10 4Bit[2] Yes 6
1456 * I 16 2Bit Yes None
1457 * J 12 2Bit Yes None
1459 * N 16 2Bit No IRQ_EINT
1461 * Q 14 2Bit Yes None
1462 * R 15 4Bit[2] Yes None
1465 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1466 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1469 static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1470 #ifdef CONFIG_CPU_S5P6450
1473 .base = S5P6450_GPA(0),
1474 .ngpio = S5P6450_GPIO_A_NR,
1479 .base = S5P6450_GPB(0),
1480 .ngpio = S5P6450_GPIO_B_NR,
1485 .base = S5P6450_GPC(0),
1486 .ngpio = S5P6450_GPIO_C_NR,
1491 .base = S5P6450_GPD(0),
1492 .ngpio = S5P6450_GPIO_D_NR,
1496 .base = S5P6450_GPK_BASE,
1498 .base = S5P6450_GPK(0),
1499 .ngpio = S5P6450_GPIO_K_NR,
1506 static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1507 #ifdef CONFIG_CPU_S5P6450
1509 .base = S5P64X0_GPG_BASE + 0x4,
1511 .base = S5P6450_GPG(0),
1512 .ngpio = S5P6450_GPIO_G_NR,
1516 .base = S5P64X0_GPH_BASE + 0x4,
1518 .base = S5P6450_GPH(0),
1519 .ngpio = S5P6450_GPIO_H_NR,
1526 static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1527 #ifdef CONFIG_CPU_S5P6450
1529 .base = S5P64X0_GPR_BASE + 0x4,
1530 .config = &s5p64x0_gpio_cfg_rbank,
1532 .base = S5P6450_GPR(0),
1533 .ngpio = S5P6450_GPIO_R_NR,
1540 static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1541 #ifdef CONFIG_CPU_S5P6450
1543 .base = S5P64X0_GPF_BASE,
1544 .config = &samsung_gpio_cfgs[6],
1546 .base = S5P6450_GPF(0),
1547 .ngpio = S5P6450_GPIO_F_NR,
1551 .base = S5P64X0_GPI_BASE,
1552 .config = &samsung_gpio_cfgs[4],
1554 .base = S5P6450_GPI(0),
1555 .ngpio = S5P6450_GPIO_I_NR,
1559 .base = S5P64X0_GPJ_BASE,
1560 .config = &samsung_gpio_cfgs[4],
1562 .base = S5P6450_GPJ(0),
1563 .ngpio = S5P6450_GPIO_J_NR,
1567 .base = S5P64X0_GPN_BASE,
1568 .config = &samsung_gpio_cfgs[5],
1570 .base = S5P6450_GPN(0),
1571 .ngpio = S5P6450_GPIO_N_NR,
1575 .base = S5P64X0_GPP_BASE,
1576 .config = &samsung_gpio_cfgs[6],
1578 .base = S5P6450_GPP(0),
1579 .ngpio = S5P6450_GPIO_P_NR,
1583 .base = S5P6450_GPQ_BASE,
1584 .config = &samsung_gpio_cfgs[5],
1586 .base = S5P6450_GPQ(0),
1587 .ngpio = S5P6450_GPIO_Q_NR,
1591 .base = S5P6450_GPS_BASE,
1592 .config = &samsung_gpio_cfgs[6],
1594 .base = S5P6450_GPS(0),
1595 .ngpio = S5P6450_GPIO_S_NR,
1603 * S5PC100 GPIO bank summary:
1605 * Bank GPIOs Style INT Type
1606 * A0 8 4Bit GPIO_INT0
1607 * A1 5 4Bit GPIO_INT1
1608 * B 8 4Bit GPIO_INT2
1609 * C 5 4Bit GPIO_INT3
1610 * D 7 4Bit GPIO_INT4
1611 * E0 8 4Bit GPIO_INT5
1612 * E1 6 4Bit GPIO_INT6
1613 * F0 8 4Bit GPIO_INT7
1614 * F1 8 4Bit GPIO_INT8
1615 * F2 8 4Bit GPIO_INT9
1616 * F3 4 4Bit GPIO_INT10
1617 * G0 8 4Bit GPIO_INT11
1618 * G1 3 4Bit GPIO_INT12
1619 * G2 7 4Bit GPIO_INT13
1620 * G3 7 4Bit GPIO_INT14
1621 * H0 8 4Bit WKUP_INT
1622 * H1 8 4Bit WKUP_INT
1623 * H2 8 4Bit WKUP_INT
1624 * H3 8 4Bit WKUP_INT
1625 * I 8 4Bit GPIO_INT15
1626 * J0 8 4Bit GPIO_INT16
1627 * J1 5 4Bit GPIO_INT17
1628 * J2 8 4Bit GPIO_INT18
1629 * J3 8 4Bit GPIO_INT19
1630 * J4 4 4Bit GPIO_INT20
1641 static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1642 #ifdef CONFIG_CPU_S5PC100
1645 .base = S5PC100_GPA0(0),
1646 .ngpio = S5PC100_GPIO_A0_NR,
1651 .base = S5PC100_GPA1(0),
1652 .ngpio = S5PC100_GPIO_A1_NR,
1657 .base = S5PC100_GPB(0),
1658 .ngpio = S5PC100_GPIO_B_NR,
1663 .base = S5PC100_GPC(0),
1664 .ngpio = S5PC100_GPIO_C_NR,
1669 .base = S5PC100_GPD(0),
1670 .ngpio = S5PC100_GPIO_D_NR,
1675 .base = S5PC100_GPE0(0),
1676 .ngpio = S5PC100_GPIO_E0_NR,
1681 .base = S5PC100_GPE1(0),
1682 .ngpio = S5PC100_GPIO_E1_NR,
1687 .base = S5PC100_GPF0(0),
1688 .ngpio = S5PC100_GPIO_F0_NR,
1693 .base = S5PC100_GPF1(0),
1694 .ngpio = S5PC100_GPIO_F1_NR,
1699 .base = S5PC100_GPF2(0),
1700 .ngpio = S5PC100_GPIO_F2_NR,
1705 .base = S5PC100_GPF3(0),
1706 .ngpio = S5PC100_GPIO_F3_NR,
1711 .base = S5PC100_GPG0(0),
1712 .ngpio = S5PC100_GPIO_G0_NR,
1717 .base = S5PC100_GPG1(0),
1718 .ngpio = S5PC100_GPIO_G1_NR,
1723 .base = S5PC100_GPG2(0),
1724 .ngpio = S5PC100_GPIO_G2_NR,
1729 .base = S5PC100_GPG3(0),
1730 .ngpio = S5PC100_GPIO_G3_NR,
1735 .base = S5PC100_GPI(0),
1736 .ngpio = S5PC100_GPIO_I_NR,
1741 .base = S5PC100_GPJ0(0),
1742 .ngpio = S5PC100_GPIO_J0_NR,
1747 .base = S5PC100_GPJ1(0),
1748 .ngpio = S5PC100_GPIO_J1_NR,
1753 .base = S5PC100_GPJ2(0),
1754 .ngpio = S5PC100_GPIO_J2_NR,
1759 .base = S5PC100_GPJ3(0),
1760 .ngpio = S5PC100_GPIO_J3_NR,
1765 .base = S5PC100_GPJ4(0),
1766 .ngpio = S5PC100_GPIO_J4_NR,
1771 .base = S5PC100_GPK0(0),
1772 .ngpio = S5PC100_GPIO_K0_NR,
1777 .base = S5PC100_GPK1(0),
1778 .ngpio = S5PC100_GPIO_K1_NR,
1783 .base = S5PC100_GPK2(0),
1784 .ngpio = S5PC100_GPIO_K2_NR,
1789 .base = S5PC100_GPK3(0),
1790 .ngpio = S5PC100_GPIO_K3_NR,
1795 .base = S5PC100_GPL0(0),
1796 .ngpio = S5PC100_GPIO_L0_NR,
1801 .base = S5PC100_GPL1(0),
1802 .ngpio = S5PC100_GPIO_L1_NR,
1807 .base = S5PC100_GPL2(0),
1808 .ngpio = S5PC100_GPIO_L2_NR,
1813 .base = S5PC100_GPL3(0),
1814 .ngpio = S5PC100_GPIO_L3_NR,
1819 .base = S5PC100_GPL4(0),
1820 .ngpio = S5PC100_GPIO_L4_NR,
1824 .base = (S5P_VA_GPIO + 0xC00),
1825 .irq_base = IRQ_EINT(0),
1827 .base = S5PC100_GPH0(0),
1828 .ngpio = S5PC100_GPIO_H0_NR,
1830 .to_irq = samsung_gpiolib_to_irq,
1833 .base = (S5P_VA_GPIO + 0xC20),
1834 .irq_base = IRQ_EINT(8),
1836 .base = S5PC100_GPH1(0),
1837 .ngpio = S5PC100_GPIO_H1_NR,
1839 .to_irq = samsung_gpiolib_to_irq,
1842 .base = (S5P_VA_GPIO + 0xC40),
1843 .irq_base = IRQ_EINT(16),
1845 .base = S5PC100_GPH2(0),
1846 .ngpio = S5PC100_GPIO_H2_NR,
1848 .to_irq = samsung_gpiolib_to_irq,
1851 .base = (S5P_VA_GPIO + 0xC60),
1852 .irq_base = IRQ_EINT(24),
1854 .base = S5PC100_GPH3(0),
1855 .ngpio = S5PC100_GPIO_H3_NR,
1857 .to_irq = samsung_gpiolib_to_irq,
1864 * Followings are the gpio banks in S5PV210/S5PC110
1866 * The 'config' member when left to NULL, is initialized to the default
1867 * structure samsung_gpio_cfgs[3] in the init function below.
1869 * The 'base' member is also initialized in the init function below.
1870 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1871 * uses the above macro and depends on the banks being listed in order here.
1874 static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1875 #ifdef CONFIG_CPU_S5PV210
1878 .base = S5PV210_GPA0(0),
1879 .ngpio = S5PV210_GPIO_A0_NR,
1884 .base = S5PV210_GPA1(0),
1885 .ngpio = S5PV210_GPIO_A1_NR,
1890 .base = S5PV210_GPB(0),
1891 .ngpio = S5PV210_GPIO_B_NR,
1896 .base = S5PV210_GPC0(0),
1897 .ngpio = S5PV210_GPIO_C0_NR,
1902 .base = S5PV210_GPC1(0),
1903 .ngpio = S5PV210_GPIO_C1_NR,
1908 .base = S5PV210_GPD0(0),
1909 .ngpio = S5PV210_GPIO_D0_NR,
1914 .base = S5PV210_GPD1(0),
1915 .ngpio = S5PV210_GPIO_D1_NR,
1920 .base = S5PV210_GPE0(0),
1921 .ngpio = S5PV210_GPIO_E0_NR,
1926 .base = S5PV210_GPE1(0),
1927 .ngpio = S5PV210_GPIO_E1_NR,
1932 .base = S5PV210_GPF0(0),
1933 .ngpio = S5PV210_GPIO_F0_NR,
1938 .base = S5PV210_GPF1(0),
1939 .ngpio = S5PV210_GPIO_F1_NR,
1944 .base = S5PV210_GPF2(0),
1945 .ngpio = S5PV210_GPIO_F2_NR,
1950 .base = S5PV210_GPF3(0),
1951 .ngpio = S5PV210_GPIO_F3_NR,
1956 .base = S5PV210_GPG0(0),
1957 .ngpio = S5PV210_GPIO_G0_NR,
1962 .base = S5PV210_GPG1(0),
1963 .ngpio = S5PV210_GPIO_G1_NR,
1968 .base = S5PV210_GPG2(0),
1969 .ngpio = S5PV210_GPIO_G2_NR,
1974 .base = S5PV210_GPG3(0),
1975 .ngpio = S5PV210_GPIO_G3_NR,
1980 .base = S5PV210_GPI(0),
1981 .ngpio = S5PV210_GPIO_I_NR,
1986 .base = S5PV210_GPJ0(0),
1987 .ngpio = S5PV210_GPIO_J0_NR,
1992 .base = S5PV210_GPJ1(0),
1993 .ngpio = S5PV210_GPIO_J1_NR,
1998 .base = S5PV210_GPJ2(0),
1999 .ngpio = S5PV210_GPIO_J2_NR,
2004 .base = S5PV210_GPJ3(0),
2005 .ngpio = S5PV210_GPIO_J3_NR,
2010 .base = S5PV210_GPJ4(0),
2011 .ngpio = S5PV210_GPIO_J4_NR,
2016 .base = S5PV210_MP01(0),
2017 .ngpio = S5PV210_GPIO_MP01_NR,
2022 .base = S5PV210_MP02(0),
2023 .ngpio = S5PV210_GPIO_MP02_NR,
2028 .base = S5PV210_MP03(0),
2029 .ngpio = S5PV210_GPIO_MP03_NR,
2034 .base = S5PV210_MP04(0),
2035 .ngpio = S5PV210_GPIO_MP04_NR,
2040 .base = S5PV210_MP05(0),
2041 .ngpio = S5PV210_GPIO_MP05_NR,
2045 .base = (S5P_VA_GPIO + 0xC00),
2046 .irq_base = IRQ_EINT(0),
2048 .base = S5PV210_GPH0(0),
2049 .ngpio = S5PV210_GPIO_H0_NR,
2051 .to_irq = samsung_gpiolib_to_irq,
2054 .base = (S5P_VA_GPIO + 0xC20),
2055 .irq_base = IRQ_EINT(8),
2057 .base = S5PV210_GPH1(0),
2058 .ngpio = S5PV210_GPIO_H1_NR,
2060 .to_irq = samsung_gpiolib_to_irq,
2063 .base = (S5P_VA_GPIO + 0xC40),
2064 .irq_base = IRQ_EINT(16),
2066 .base = S5PV210_GPH2(0),
2067 .ngpio = S5PV210_GPIO_H2_NR,
2069 .to_irq = samsung_gpiolib_to_irq,
2072 .base = (S5P_VA_GPIO + 0xC60),
2073 .irq_base = IRQ_EINT(24),
2075 .base = S5PV210_GPH3(0),
2076 .ngpio = S5PV210_GPIO_H3_NR,
2078 .to_irq = samsung_gpiolib_to_irq,
2084 /* TODO: cleanup soc_is_* */
2085 static __init int samsung_gpiolib_init(void)
2087 struct samsung_gpio_chip *chip;
2092 * Currently there are two drivers that can provide GPIO support for
2093 * Samsung SoCs. For device tree enabled platforms, the new
2094 * pinctrl-samsung driver is used, providing both GPIO and pin control
2095 * interfaces. For legacy (non-DT) platforms this driver is used.
2097 if (of_have_populated_dt())
2100 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
2102 if (soc_is_s3c24xx()) {
2103 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
2104 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
2105 } else if (soc_is_s3c64xx()) {
2106 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
2107 ARRAY_SIZE(s3c64xx_gpios_2bit),
2108 S3C64XX_VA_GPIO + 0xE0, 0x20);
2109 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
2110 ARRAY_SIZE(s3c64xx_gpios_4bit),
2112 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
2113 ARRAY_SIZE(s3c64xx_gpios_4bit2));
2114 } else if (soc_is_s5p6440()) {
2115 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
2116 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
2117 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
2118 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
2119 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
2120 ARRAY_SIZE(s5p6440_gpios_4bit2));
2121 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
2122 ARRAY_SIZE(s5p6440_gpios_rbank));
2123 } else if (soc_is_s5p6450()) {
2124 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
2125 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
2126 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
2127 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
2128 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
2129 ARRAY_SIZE(s5p6450_gpios_4bit2));
2130 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
2131 ARRAY_SIZE(s5p6450_gpios_rbank));
2132 } else if (soc_is_s5pc100()) {
2134 chip = s5pc100_gpios_4bit;
2135 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
2137 for (i = 0; i < nr_chips; i++, chip++) {
2138 if (!chip->config) {
2139 chip->config = &samsung_gpio_cfgs[3];
2140 chip->group = group++;
2143 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
2144 #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
2145 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2147 } else if (soc_is_s5pv210()) {
2149 chip = s5pv210_gpios_4bit;
2150 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
2152 for (i = 0; i < nr_chips; i++, chip++) {
2153 if (!chip->config) {
2154 chip->config = &samsung_gpio_cfgs[3];
2155 chip->group = group++;
2158 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
2159 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
2160 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2163 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
2169 core_initcall(samsung_gpiolib_init);
2171 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
2173 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2174 unsigned long flags;
2181 offset = pin - chip->chip.base;
2183 samsung_gpio_lock(chip, flags);
2184 ret = samsung_gpio_do_setcfg(chip, offset, config);
2185 samsung_gpio_unlock(chip, flags);
2189 EXPORT_SYMBOL(s3c_gpio_cfgpin);
2191 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
2196 for (; nr > 0; nr--, start++) {
2197 ret = s3c_gpio_cfgpin(start, cfg);
2204 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
2206 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
2207 unsigned int cfg, samsung_gpio_pull_t pull)
2211 for (; nr > 0; nr--, start++) {
2212 s3c_gpio_setpull(start, pull);
2213 ret = s3c_gpio_cfgpin(start, cfg);
2220 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
2222 unsigned s3c_gpio_getcfg(unsigned int pin)
2224 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2225 unsigned long flags;
2230 offset = pin - chip->chip.base;
2232 samsung_gpio_lock(chip, flags);
2233 ret = samsung_gpio_do_getcfg(chip, offset);
2234 samsung_gpio_unlock(chip, flags);
2239 EXPORT_SYMBOL(s3c_gpio_getcfg);
2241 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
2243 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2244 unsigned long flags;
2250 offset = pin - chip->chip.base;
2252 samsung_gpio_lock(chip, flags);
2253 ret = samsung_gpio_do_setpull(chip, offset, pull);
2254 samsung_gpio_unlock(chip, flags);
2258 EXPORT_SYMBOL(s3c_gpio_setpull);
2260 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
2262 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2263 unsigned long flags;
2268 offset = pin - chip->chip.base;
2270 samsung_gpio_lock(chip, flags);
2271 pup = samsung_gpio_do_getpull(chip, offset);
2272 samsung_gpio_unlock(chip, flags);
2275 return (__force samsung_gpio_pull_t)pup;
2277 EXPORT_SYMBOL(s3c_gpio_getpull);
2279 #ifdef CONFIG_S5P_GPIO_DRVSTR
2280 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
2282 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2291 off = pin - chip->chip.base;
2293 reg = chip->base + 0x0C;
2295 drvstr = __raw_readl(reg);
2296 drvstr = drvstr >> shift;
2299 return (__force s5p_gpio_drvstr_t)drvstr;
2301 EXPORT_SYMBOL(s5p_gpio_get_drvstr);
2303 int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
2305 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2314 off = pin - chip->chip.base;
2316 reg = chip->base + 0x0C;
2318 tmp = __raw_readl(reg);
2319 tmp &= ~(0x3 << shift);
2320 tmp |= drvstr << shift;
2322 __raw_writel(tmp, reg);
2326 EXPORT_SYMBOL(s5p_gpio_set_drvstr);
2327 #endif /* CONFIG_S5P_GPIO_DRVSTR */
2329 #ifdef CONFIG_PLAT_S3C24XX
2330 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
2332 unsigned long flags;
2333 unsigned long misccr;
2335 local_irq_save(flags);
2336 misccr = __raw_readl(S3C24XX_MISCCR);
2339 __raw_writel(misccr, S3C24XX_MISCCR);
2340 local_irq_restore(flags);
2344 EXPORT_SYMBOL(s3c2410_modify_misccr);