2 * Copyright 2015 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "amd_shared.h"
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include "amdgpu_pm.h"
31 #include <drm/amdgpu_drm.h>
32 #include "amdgpu_powerplay.h"
36 static int amdgpu_powerplay_init(struct amdgpu_device *adev)
39 struct amd_powerplay *amd_pp;
41 amd_pp = &(adev->powerplay);
43 if (adev->pp_enabled) {
44 #ifdef CONFIG_DRM_AMD_POWERPLAY
45 struct amd_pp_init *pp_init;
47 pp_init = kzalloc(sizeof(struct amd_pp_init), GFP_KERNEL);
52 pp_init->chip_family = adev->family;
53 pp_init->chip_id = adev->asic_type;
54 pp_init->device = amdgpu_cgs_create_device(adev);
56 ret = amd_powerplay_init(pp_init, amd_pp);
60 amd_pp->pp_handle = (void *)adev;
62 switch (adev->asic_type) {
63 #ifdef CONFIG_DRM_AMDGPU_CIK
66 amd_pp->ip_funcs = &ci_dpm_ip_funcs;
71 amd_pp->ip_funcs = &kv_dpm_ip_funcs;
75 amd_pp->ip_funcs = &iceland_dpm_ip_funcs;
78 amd_pp->ip_funcs = &tonga_dpm_ip_funcs;
81 amd_pp->ip_funcs = &fiji_dpm_ip_funcs;
85 amd_pp->ip_funcs = &cz_dpm_ip_funcs;
95 static int amdgpu_pp_early_init(void *handle)
97 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
100 #ifdef CONFIG_DRM_AMD_POWERPLAY
101 switch (adev->asic_type) {
104 adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
108 adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
110 /* These chips don't have powerplay implemenations */
118 adev->pp_enabled = false;
122 adev->pp_enabled = false;
125 ret = amdgpu_powerplay_init(adev);
129 if (adev->powerplay.ip_funcs->early_init)
130 ret = adev->powerplay.ip_funcs->early_init(
131 adev->powerplay.pp_handle);
136 static int amdgpu_pp_late_init(void *handle)
139 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
141 if (adev->powerplay.ip_funcs->late_init)
142 ret = adev->powerplay.ip_funcs->late_init(
143 adev->powerplay.pp_handle);
145 #ifdef CONFIG_DRM_AMD_POWERPLAY
146 if (adev->pp_enabled) {
147 amdgpu_pm_sysfs_init(adev);
148 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
154 static int amdgpu_pp_sw_init(void *handle)
157 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
159 if (adev->powerplay.ip_funcs->sw_init)
160 ret = adev->powerplay.ip_funcs->sw_init(
161 adev->powerplay.pp_handle);
163 #ifdef CONFIG_DRM_AMD_POWERPLAY
164 if (adev->pp_enabled) {
166 adev->pm.dpm_enabled = false;
168 adev->pm.dpm_enabled = true;
175 static int amdgpu_pp_sw_fini(void *handle)
178 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
180 if (adev->powerplay.ip_funcs->sw_fini)
181 ret = adev->powerplay.ip_funcs->sw_fini(
182 adev->powerplay.pp_handle);
186 #ifdef CONFIG_DRM_AMD_POWERPLAY
187 if (adev->pp_enabled) {
188 amdgpu_pm_sysfs_fini(adev);
189 amd_powerplay_fini(adev->powerplay.pp_handle);
196 static int amdgpu_pp_hw_init(void *handle)
199 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
201 if (adev->pp_enabled && adev->firmware.smu_load)
202 amdgpu_ucode_init_bo(adev);
204 if (adev->powerplay.ip_funcs->hw_init)
205 ret = adev->powerplay.ip_funcs->hw_init(
206 adev->powerplay.pp_handle);
211 static int amdgpu_pp_hw_fini(void *handle)
214 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
216 if (adev->powerplay.ip_funcs->hw_fini)
217 ret = adev->powerplay.ip_funcs->hw_fini(
218 adev->powerplay.pp_handle);
220 if (adev->pp_enabled && adev->firmware.smu_load)
221 amdgpu_ucode_fini_bo(adev);
226 static int amdgpu_pp_suspend(void *handle)
229 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
231 if (adev->powerplay.ip_funcs->suspend)
232 ret = adev->powerplay.ip_funcs->suspend(
233 adev->powerplay.pp_handle);
237 static int amdgpu_pp_resume(void *handle)
240 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
242 if (adev->powerplay.ip_funcs->resume)
243 ret = adev->powerplay.ip_funcs->resume(
244 adev->powerplay.pp_handle);
248 static int amdgpu_pp_set_clockgating_state(void *handle,
249 enum amd_clockgating_state state)
252 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
254 if (adev->powerplay.ip_funcs->set_clockgating_state)
255 ret = adev->powerplay.ip_funcs->set_clockgating_state(
256 adev->powerplay.pp_handle, state);
260 static int amdgpu_pp_set_powergating_state(void *handle,
261 enum amd_powergating_state state)
264 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
266 if (adev->powerplay.ip_funcs->set_powergating_state)
267 ret = adev->powerplay.ip_funcs->set_powergating_state(
268 adev->powerplay.pp_handle, state);
273 static bool amdgpu_pp_is_idle(void *handle)
276 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
278 if (adev->powerplay.ip_funcs->is_idle)
279 ret = adev->powerplay.ip_funcs->is_idle(
280 adev->powerplay.pp_handle);
284 static int amdgpu_pp_wait_for_idle(void *handle)
287 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
289 if (adev->powerplay.ip_funcs->wait_for_idle)
290 ret = adev->powerplay.ip_funcs->wait_for_idle(
291 adev->powerplay.pp_handle);
295 static int amdgpu_pp_soft_reset(void *handle)
298 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
300 if (adev->powerplay.ip_funcs->soft_reset)
301 ret = adev->powerplay.ip_funcs->soft_reset(
302 adev->powerplay.pp_handle);
306 static void amdgpu_pp_print_status(void *handle)
308 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
310 if (adev->powerplay.ip_funcs->print_status)
311 adev->powerplay.ip_funcs->print_status(
312 adev->powerplay.pp_handle);
315 const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
316 .early_init = amdgpu_pp_early_init,
317 .late_init = amdgpu_pp_late_init,
318 .sw_init = amdgpu_pp_sw_init,
319 .sw_fini = amdgpu_pp_sw_fini,
320 .hw_init = amdgpu_pp_hw_init,
321 .hw_fini = amdgpu_pp_hw_fini,
322 .suspend = amdgpu_pp_suspend,
323 .resume = amdgpu_pp_resume,
324 .is_idle = amdgpu_pp_is_idle,
325 .wait_for_idle = amdgpu_pp_wait_for_idle,
326 .soft_reset = amdgpu_pp_soft_reset,
327 .print_status = amdgpu_pp_print_status,
328 .set_clockgating_state = amdgpu_pp_set_clockgating_state,
329 .set_powergating_state = amdgpu_pp_set_powergating_state,