2 * Copyright 2011 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
32 * We store the last allocated bo in "hole", we always try to allocate
33 * after the last allocated bo. Principle is that in a linear GPU ring
34 * progression was is after last is the oldest bo we allocated and thus
35 * the first one that should no longer be in use by the GPU.
37 * If it's not the case we skip over the bo after last to the closest
38 * done bo if such one exist. If none exist and we are not asked to
39 * block we report failure to allocate.
41 * If we are asked to block we wait on all the oldest fence of all
42 * rings. We just wait for any of those fence to complete.
47 static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo);
48 static void amdgpu_sa_bo_try_free(struct amdgpu_sa_manager *sa_manager);
50 int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
51 struct amdgpu_sa_manager *sa_manager,
52 unsigned size, u32 align, u32 domain)
56 init_waitqueue_head(&sa_manager->wq);
57 sa_manager->bo = NULL;
58 sa_manager->size = size;
59 sa_manager->domain = domain;
60 sa_manager->align = align;
61 sa_manager->hole = &sa_manager->olist;
62 INIT_LIST_HEAD(&sa_manager->olist);
63 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
64 INIT_LIST_HEAD(&sa_manager->flist[i]);
67 r = amdgpu_bo_create(adev, size, align, true,
68 domain, 0, NULL, &sa_manager->bo);
70 dev_err(adev->dev, "(%d) failed to allocate bo for manager\n", r);
77 void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
78 struct amdgpu_sa_manager *sa_manager)
80 struct amdgpu_sa_bo *sa_bo, *tmp;
82 if (!list_empty(&sa_manager->olist)) {
83 sa_manager->hole = &sa_manager->olist,
84 amdgpu_sa_bo_try_free(sa_manager);
85 if (!list_empty(&sa_manager->olist)) {
86 dev_err(adev->dev, "sa_manager is not empty, clearing anyway\n");
89 list_for_each_entry_safe(sa_bo, tmp, &sa_manager->olist, olist) {
90 amdgpu_sa_bo_remove_locked(sa_bo);
92 amdgpu_bo_unref(&sa_manager->bo);
96 int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
97 struct amdgpu_sa_manager *sa_manager)
101 if (sa_manager->bo == NULL) {
102 dev_err(adev->dev, "no bo for sa manager\n");
107 r = amdgpu_bo_reserve(sa_manager->bo, false);
109 dev_err(adev->dev, "(%d) failed to reserve manager bo\n", r);
112 r = amdgpu_bo_pin(sa_manager->bo, sa_manager->domain, &sa_manager->gpu_addr);
114 amdgpu_bo_unreserve(sa_manager->bo);
115 dev_err(adev->dev, "(%d) failed to pin manager bo\n", r);
118 r = amdgpu_bo_kmap(sa_manager->bo, &sa_manager->cpu_ptr);
119 amdgpu_bo_unreserve(sa_manager->bo);
123 int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
124 struct amdgpu_sa_manager *sa_manager)
128 if (sa_manager->bo == NULL) {
129 dev_err(adev->dev, "no bo for sa manager\n");
133 r = amdgpu_bo_reserve(sa_manager->bo, false);
135 amdgpu_bo_kunmap(sa_manager->bo);
136 amdgpu_bo_unpin(sa_manager->bo);
137 amdgpu_bo_unreserve(sa_manager->bo);
142 static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo)
144 struct amdgpu_sa_manager *sa_manager = sa_bo->manager;
145 if (sa_manager->hole == &sa_bo->olist) {
146 sa_manager->hole = sa_bo->olist.prev;
148 list_del_init(&sa_bo->olist);
149 list_del_init(&sa_bo->flist);
150 amdgpu_fence_unref(&sa_bo->fence);
154 static void amdgpu_sa_bo_try_free(struct amdgpu_sa_manager *sa_manager)
156 struct amdgpu_sa_bo *sa_bo, *tmp;
158 if (sa_manager->hole->next == &sa_manager->olist)
161 sa_bo = list_entry(sa_manager->hole->next, struct amdgpu_sa_bo, olist);
162 list_for_each_entry_safe_from(sa_bo, tmp, &sa_manager->olist, olist) {
163 if (sa_bo->fence == NULL ||
164 !fence_is_signaled(&sa_bo->fence->base)) {
167 amdgpu_sa_bo_remove_locked(sa_bo);
171 static inline unsigned amdgpu_sa_bo_hole_soffset(struct amdgpu_sa_manager *sa_manager)
173 struct list_head *hole = sa_manager->hole;
175 if (hole != &sa_manager->olist) {
176 return list_entry(hole, struct amdgpu_sa_bo, olist)->eoffset;
181 static inline unsigned amdgpu_sa_bo_hole_eoffset(struct amdgpu_sa_manager *sa_manager)
183 struct list_head *hole = sa_manager->hole;
185 if (hole->next != &sa_manager->olist) {
186 return list_entry(hole->next, struct amdgpu_sa_bo, olist)->soffset;
188 return sa_manager->size;
191 static bool amdgpu_sa_bo_try_alloc(struct amdgpu_sa_manager *sa_manager,
192 struct amdgpu_sa_bo *sa_bo,
193 unsigned size, unsigned align)
195 unsigned soffset, eoffset, wasted;
197 soffset = amdgpu_sa_bo_hole_soffset(sa_manager);
198 eoffset = amdgpu_sa_bo_hole_eoffset(sa_manager);
199 wasted = (align - (soffset % align)) % align;
201 if ((eoffset - soffset) >= (size + wasted)) {
204 sa_bo->manager = sa_manager;
205 sa_bo->soffset = soffset;
206 sa_bo->eoffset = soffset + size;
207 list_add(&sa_bo->olist, sa_manager->hole);
208 INIT_LIST_HEAD(&sa_bo->flist);
209 sa_manager->hole = &sa_bo->olist;
216 * amdgpu_sa_event - Check if we can stop waiting
218 * @sa_manager: pointer to the sa_manager
219 * @size: number of bytes we want to allocate
220 * @align: alignment we need to match
222 * Check if either there is a fence we can wait for or
223 * enough free memory to satisfy the allocation directly
225 static bool amdgpu_sa_event(struct amdgpu_sa_manager *sa_manager,
226 unsigned size, unsigned align)
228 unsigned soffset, eoffset, wasted;
231 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
232 if (!list_empty(&sa_manager->flist[i])) {
237 soffset = amdgpu_sa_bo_hole_soffset(sa_manager);
238 eoffset = amdgpu_sa_bo_hole_eoffset(sa_manager);
239 wasted = (align - (soffset % align)) % align;
241 if ((eoffset - soffset) >= (size + wasted)) {
248 static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager,
249 struct amdgpu_fence **fences,
252 struct amdgpu_sa_bo *best_bo = NULL;
253 unsigned i, soffset, best, tmp;
255 /* if hole points to the end of the buffer */
256 if (sa_manager->hole->next == &sa_manager->olist) {
257 /* try again with its beginning */
258 sa_manager->hole = &sa_manager->olist;
262 soffset = amdgpu_sa_bo_hole_soffset(sa_manager);
263 /* to handle wrap around we add sa_manager->size */
264 best = sa_manager->size * 2;
265 /* go over all fence list and try to find the closest sa_bo
266 * of the current last
268 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
269 struct amdgpu_sa_bo *sa_bo;
271 if (list_empty(&sa_manager->flist[i])) {
275 sa_bo = list_first_entry(&sa_manager->flist[i],
276 struct amdgpu_sa_bo, flist);
278 if (!fence_is_signaled(&sa_bo->fence->base)) {
279 fences[i] = sa_bo->fence;
283 /* limit the number of tries each ring gets */
288 tmp = sa_bo->soffset;
290 /* wrap around, pretend it's after */
291 tmp += sa_manager->size;
295 /* this sa bo is the closest one */
302 ++tries[best_bo->fence->ring->idx];
303 sa_manager->hole = best_bo->olist.prev;
305 /* we knew that this one is signaled,
306 so it's save to remote it */
307 amdgpu_sa_bo_remove_locked(best_bo);
313 int amdgpu_sa_bo_new(struct amdgpu_device *adev,
314 struct amdgpu_sa_manager *sa_manager,
315 struct amdgpu_sa_bo **sa_bo,
316 unsigned size, unsigned align)
318 struct amdgpu_fence *fences[AMDGPU_MAX_RINGS];
319 unsigned tries[AMDGPU_MAX_RINGS];
323 BUG_ON(align > sa_manager->align);
324 BUG_ON(size > sa_manager->size);
326 *sa_bo = kmalloc(sizeof(struct amdgpu_sa_bo), GFP_KERNEL);
327 if ((*sa_bo) == NULL) {
330 (*sa_bo)->manager = sa_manager;
331 (*sa_bo)->fence = NULL;
332 INIT_LIST_HEAD(&(*sa_bo)->olist);
333 INIT_LIST_HEAD(&(*sa_bo)->flist);
335 spin_lock(&sa_manager->wq.lock);
337 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
343 amdgpu_sa_bo_try_free(sa_manager);
345 if (amdgpu_sa_bo_try_alloc(sa_manager, *sa_bo,
347 spin_unlock(&sa_manager->wq.lock);
351 /* see if we can skip over some allocations */
352 } while (amdgpu_sa_bo_next_hole(sa_manager, fences, tries));
354 spin_unlock(&sa_manager->wq.lock);
355 t = amdgpu_fence_wait_multiple(adev, fences, AMDGPU_MAX_RINGS, false, false,
356 MAX_SCHEDULE_TIMEOUT);
358 spin_lock(&sa_manager->wq.lock);
359 /* if we have nothing to wait for block */
361 r = wait_event_interruptible_locked(
363 amdgpu_sa_event(sa_manager, size, align)
369 spin_unlock(&sa_manager->wq.lock);
375 void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo,
376 struct amdgpu_fence *fence)
378 struct amdgpu_sa_manager *sa_manager;
380 if (sa_bo == NULL || *sa_bo == NULL) {
384 sa_manager = (*sa_bo)->manager;
385 spin_lock(&sa_manager->wq.lock);
386 if (fence && !fence_is_signaled(&fence->base)) {
387 (*sa_bo)->fence = amdgpu_fence_ref(fence);
388 list_add_tail(&(*sa_bo)->flist,
389 &sa_manager->flist[fence->ring->idx]);
391 amdgpu_sa_bo_remove_locked(*sa_bo);
393 wake_up_all_locked(&sa_manager->wq);
394 spin_unlock(&sa_manager->wq.lock);
398 #if defined(CONFIG_DEBUG_FS)
399 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
402 struct amdgpu_sa_bo *i;
404 spin_lock(&sa_manager->wq.lock);
405 list_for_each_entry(i, &sa_manager->olist, olist) {
406 uint64_t soffset = i->soffset + sa_manager->gpu_addr;
407 uint64_t eoffset = i->eoffset + sa_manager->gpu_addr;
408 if (&i->olist == sa_manager->hole) {
413 seq_printf(m, "[0x%010llx 0x%010llx] size %8lld",
414 soffset, eoffset, eoffset - soffset);
416 seq_printf(m, " protected by 0x%016llx on ring %d",
417 i->fence->seq, i->fence->ring->idx);
421 spin_unlock(&sa_manager->wq.lock);