drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <christian.koenig@amd.com>
  29  */
  30
  31 #include <drm/drmP.h>
  32 #include "amdgpu.h"
  33 #include "amdgpu_trace.h"
  34
  35 struct amdgpu_sync_entry {
  36         struct hlist_node       node;
  37         struct fence            *fence;
  38 };
  39
  40 /**
  41  * amdgpu_sync_create - zero init sync object
  42  *
  43  * @sync: sync object to initialize
  44  *
  45  * Just clear the sync object for now.
  46  */
  47 void amdgpu_sync_create(struct amdgpu_sync *sync)
  48 {
  49         unsigned i;
  50
  51         for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
  52                 sync->semaphores[i] = NULL;
  53
  54         for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
  55                 sync->sync_to[i] = NULL;
  56
  57         hash_init(sync->fences);
  58         sync->last_vm_update = NULL;
  59 }
  60
  61 static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, struct fence *f)
  62 {
  63         struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
  64         struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
  65
  66         if (a_fence)
  67                 return a_fence->ring->adev == adev;
  68         if (s_fence)
  69                 return (struct amdgpu_device *)s_fence->scheduler->priv == adev;
  70         return false;
  71 }
  72
  73 static bool amdgpu_sync_test_owner(struct fence *f, void *owner)
  74 {
  75         struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
  76         struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
  77         if (s_fence)
  78                 return s_fence->owner == owner;
  79         if (a_fence)
  80                 return a_fence->owner == owner;
  81         return false;
  82 }
  83
  84 /**
  85  * amdgpu_sync_fence - remember to sync to this fence
  86  *
  87  * @sync: sync object to add fence to
  88  * @fence: fence to sync to
  89  *
  90  */
  91 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
  92                       struct fence *f)
  93 {
  94         struct amdgpu_sync_entry *e;
  95         struct amdgpu_fence *fence;
  96         struct amdgpu_fence *other;
  97         struct fence *tmp, *later;
  98
  99         if (!f)
 100                 return 0;
 101
 102         if (amdgpu_sync_same_dev(adev, f) &&
 103             amdgpu_sync_test_owner(f, AMDGPU_FENCE_OWNER_VM)) {
 104                 if (sync->last_vm_update) {
 105                         tmp = sync->last_vm_update;
 106                         BUG_ON(f->context != tmp->context);
 107                         later = (f->seqno - tmp->seqno <= INT_MAX) ? f : tmp;
 108                         sync->last_vm_update = fence_get(later);
 109                         fence_put(tmp);
 110                 } else
 111                         sync->last_vm_update = fence_get(f);
 112         }
 113
 114         fence = to_amdgpu_fence(f);
 115         if (!fence || fence->ring->adev != adev) {
 116                 hash_for_each_possible(sync->fences, e, node, f->context) {
 117                         struct fence *new;
 118                         if (unlikely(e->fence->context != f->context))
 119                                 continue;
 120                         new = fence_get(fence_later(e->fence, f));
 121                         if (new) {
 122                                 fence_put(e->fence);
 123                                 e->fence = new;
 124                         }
 125                         return 0;
 126                 }
 127
 128                 e = kmalloc(sizeof(struct amdgpu_sync_entry), GFP_KERNEL);
 129                 if (!e)
 130                         return -ENOMEM;
 131
 132                 hash_add(sync->fences, &e->node, f->context);
 133                 e->fence = fence_get(f);
 134                 return 0;
 135         }
 136
 137         other = sync->sync_to[fence->ring->idx];
 138         sync->sync_to[fence->ring->idx] = amdgpu_fence_ref(
 139                 amdgpu_fence_later(fence, other));
 140         amdgpu_fence_unref(&other);
 141
 142         return 0;
 143 }
 144
 145 /**
 146  * amdgpu_sync_resv - use the semaphores to sync to a reservation object
 147  *
 148  * @sync: sync object to add fences from reservation object to
 149  * @resv: reservation object with embedded fence
 150  * @shared: true if we should only sync to the exclusive fence
 151  *
 152  * Sync to the fence using the semaphore objects
 153  */
 154 int amdgpu_sync_resv(struct amdgpu_device *adev,
 155                      struct amdgpu_sync *sync,
 156                      struct reservation_object *resv,
 157                      void *owner)
 158 {
 159         struct reservation_object_list *flist;
 160         struct fence *f;
 161         struct amdgpu_fence *fence;
 162         unsigned i;
 163         int r = 0;
 164
 165         if (resv == NULL)
 166                 return -EINVAL;
 167
 168         /* always sync to the exclusive fence */
 169         f = reservation_object_get_excl(resv);
 170         r = amdgpu_sync_fence(adev, sync, f);
 171
 172         flist = reservation_object_get_list(resv);
 173         if (!flist || r)
 174                 return r;
 175
 176         for (i = 0; i < flist->shared_count; ++i) {
 177                 f = rcu_dereference_protected(flist->shared[i],
 178                                               reservation_object_held(resv));
 179                 fence = f ? to_amdgpu_fence(f) : NULL;
 180                 if (fence && fence->ring->adev == adev) {
 181                         /* VM updates are only interesting
 182                          * for other VM updates and moves.
 183                          */
 184                         if ((owner != AMDGPU_FENCE_OWNER_MOVE) &&
 185                             (fence->owner != AMDGPU_FENCE_OWNER_MOVE) &&
 186                             ((owner == AMDGPU_FENCE_OWNER_VM) !=
 187                              (fence->owner == AMDGPU_FENCE_OWNER_VM)))
 188                                 continue;
 189
 190                         /* Ignore fence from the same owner as
 191                          * long as it isn't undefined.
 192                          */
 193                         if (owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
 194                             fence->owner == owner)
 195                                 continue;
 196                 }
 197
 198                 r = amdgpu_sync_fence(adev, sync, f);
 199                 if (r)
 200                         break;
 201         }
 202         return r;
 203 }
 204
 205 int amdgpu_sync_wait(struct amdgpu_sync *sync)
 206 {
 207         struct amdgpu_sync_entry *e;
 208         struct hlist_node *tmp;
 209         int i, r;
 210
 211         hash_for_each_safe(sync->fences, i, tmp, e, node) {
 212                 r = fence_wait(e->fence, false);
 213                 if (r)
 214                         return r;
 215
 216                 hash_del(&e->node);
 217                 fence_put(e->fence);
 218                 kfree(e);
 219         }
 220         return 0;
 221 }
 222
 223 /**
 224  * amdgpu_sync_rings - sync ring to all registered fences
 225  *
 226  * @sync: sync object to use
 227  * @ring: ring that needs sync
 228  *
 229  * Ensure that all registered fences are signaled before letting
 230  * the ring continue. The caller must hold the ring lock.
 231  */
 232 int amdgpu_sync_rings(struct amdgpu_sync *sync,
 233                       struct amdgpu_ring *ring)
 234 {
 235         struct amdgpu_device *adev = ring->adev;
 236         unsigned count = 0;
 237         int i, r;
 238
 239         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 240                 struct amdgpu_fence *fence = sync->sync_to[i];
 241                 struct amdgpu_semaphore *semaphore;
 242                 struct amdgpu_ring *other = adev->rings[i];
 243
 244                 /* check if we really need to sync */
 245                 if (!amdgpu_fence_need_sync(fence, ring))
 246                         continue;
 247
 248                 /* prevent GPU deadlocks */
 249                 if (!other->ready) {
 250                         dev_err(adev->dev, "Syncing to a disabled ring!");
 251                         return -EINVAL;
 252                 }
 253
 254                 if (amdgpu_enable_scheduler || (count >= AMDGPU_NUM_SYNCS)) {
 255                         /* not enough room, wait manually */
 256                         r = fence_wait(&fence->base, false);
 257                         if (r)
 258                                 return r;
 259                         continue;
 260                 }
 261                 r = amdgpu_semaphore_create(adev, &semaphore);
 262                 if (r)
 263                         return r;
 264
 265                 sync->semaphores[count++] = semaphore;
 266
 267                 /* allocate enough space for sync command */
 268                 r = amdgpu_ring_alloc(other, 16);
 269                 if (r)
 270                         return r;
 271
 272                 /* emit the signal semaphore */
 273                 if (!amdgpu_semaphore_emit_signal(other, semaphore)) {
 274                         /* signaling wasn't successful wait manually */
 275                         amdgpu_ring_undo(other);
 276                         r = fence_wait(&fence->base, false);
 277                         if (r)
 278                                 return r;
 279                         continue;
 280                 }
 281
 282                 /* we assume caller has already allocated space on waiters ring */
 283                 if (!amdgpu_semaphore_emit_wait(ring, semaphore)) {
 284                         /* waiting wasn't successful wait manually */
 285                         amdgpu_ring_undo(other);
 286                         r = fence_wait(&fence->base, false);
 287                         if (r)
 288                                 return r;
 289                         continue;
 290                 }
 291
 292                 amdgpu_ring_commit(other);
 293                 amdgpu_fence_note_sync(fence, ring);
 294         }
 295
 296         return 0;
 297 }
 298
 299 /**
 300  * amdgpu_sync_free - free the sync object
 301  *
 302  * @adev: amdgpu_device pointer
 303  * @sync: sync object to use
 304  * @fence: fence to use for the free
 305  *
 306  * Free the sync object by freeing all semaphores in it.
 307  */
 308 void amdgpu_sync_free(struct amdgpu_device *adev,
 309                       struct amdgpu_sync *sync,
 310                       struct fence *fence)
 311 {
 312         struct amdgpu_sync_entry *e;
 313         struct hlist_node *tmp;
 314         unsigned i;
 315
 316         hash_for_each_safe(sync->fences, i, tmp, e, node) {
 317                 hash_del(&e->node);
 318                 fence_put(e->fence);
 319                 kfree(e);
 320         }
 321
 322         for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
 323                 amdgpu_semaphore_free(adev, &sync->semaphores[i], fence);
 324
 325         for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
 326                 amdgpu_fence_unref(&sync->sync_to[i]);
 327
 328         fence_put(sync->last_vm_update);
 329 }