drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <deathsimple@vodafone.de>
  29  */
  30
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm.h>
  35
  36 #include "amdgpu.h"
  37 #include "amdgpu_pm.h"
  38 #include "amdgpu_uvd.h"
  39 #include "cikd.h"
  40 #include "uvd/uvd_4_2_d.h"
  41
  42 /* 1 second timeout */
  43 #define UVD_IDLE_TIMEOUT_MS     1000
  44
  45 /* Firmware Names */
  46 #ifdef CONFIG_DRM_AMDGPU_CIK
  47 #define FIRMWARE_BONAIRE        "radeon/bonaire_uvd.bin"
  48 #define FIRMWARE_KABINI         "radeon/kabini_uvd.bin"
  49 #define FIRMWARE_KAVERI         "radeon/kaveri_uvd.bin"
  50 #define FIRMWARE_HAWAII         "radeon/hawaii_uvd.bin"
  51 #define FIRMWARE_MULLINS        "radeon/mullins_uvd.bin"
  52 #endif
  53 #define FIRMWARE_TONGA          "amdgpu/tonga_uvd.bin"
  54 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_uvd.bin"
  55 #define FIRMWARE_FIJI           "amdgpu/fiji_uvd.bin"
  56
  57 /**
  58  * amdgpu_uvd_cs_ctx - Command submission parser context
  59  *
  60  * Used for emulating virtual memory support on UVD 4.2.
  61  */
  62 struct amdgpu_uvd_cs_ctx {
  63         struct amdgpu_cs_parser *parser;
  64         unsigned reg, count;
  65         unsigned data0, data1;
  66         unsigned idx;
  67         unsigned ib_idx;
  68
  69         /* does the IB has a msg command */
  70         bool has_msg_cmd;
  71
  72         /* minimum buffer sizes */
  73         unsigned *buf_sizes;
  74 };
  75
  76 #ifdef CONFIG_DRM_AMDGPU_CIK
  77 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  78 MODULE_FIRMWARE(FIRMWARE_KABINI);
  79 MODULE_FIRMWARE(FIRMWARE_KAVERI);
  80 MODULE_FIRMWARE(FIRMWARE_HAWAII);
  81 MODULE_FIRMWARE(FIRMWARE_MULLINS);
  82 #endif
  83 MODULE_FIRMWARE(FIRMWARE_TONGA);
  84 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
  85 MODULE_FIRMWARE(FIRMWARE_FIJI);
  86
  87 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
  88 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
  89
  90 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
  91 {
  92         unsigned long bo_size;
  93         const char *fw_name;
  94         const struct common_firmware_header *hdr;
  95         unsigned version_major, version_minor, family_id;
  96         int i, r;
  97
  98         INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
  99
 100         switch (adev->asic_type) {
 101 #ifdef CONFIG_DRM_AMDGPU_CIK
 102         case CHIP_BONAIRE:
 103                 fw_name = FIRMWARE_BONAIRE;
 104                 break;
 105         case CHIP_KABINI:
 106                 fw_name = FIRMWARE_KABINI;
 107                 break;
 108         case CHIP_KAVERI:
 109                 fw_name = FIRMWARE_KAVERI;
 110                 break;
 111         case CHIP_HAWAII:
 112                 fw_name = FIRMWARE_HAWAII;
 113                 break;
 114         case CHIP_MULLINS:
 115                 fw_name = FIRMWARE_MULLINS;
 116                 break;
 117 #endif
 118         case CHIP_TONGA:
 119                 fw_name = FIRMWARE_TONGA;
 120                 break;
 121         case CHIP_FIJI:
 122                 fw_name = FIRMWARE_FIJI;
 123                 break;
 124         case CHIP_CARRIZO:
 125                 fw_name = FIRMWARE_CARRIZO;
 126                 break;
 127         default:
 128                 return -EINVAL;
 129         }
 130
 131         r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
 132         if (r) {
 133                 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
 134                         fw_name);
 135                 return r;
 136         }
 137
 138         r = amdgpu_ucode_validate(adev->uvd.fw);
 139         if (r) {
 140                 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
 141                         fw_name);
 142                 release_firmware(adev->uvd.fw);
 143                 adev->uvd.fw = NULL;
 144                 return r;
 145         }
 146
 147         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 148         family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 149         version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 150         version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 151         DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
 152                 version_major, version_minor, family_id);
 153
 154         bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
 155                  +  AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
 156         r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
 157                              AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->uvd.vcpu_bo);
 158         if (r) {
 159                 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
 160                 return r;
 161         }
 162
 163         r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
 164         if (r) {
 165                 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
 166                 dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r);
 167                 return r;
 168         }
 169
 170         r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
 171                           &adev->uvd.gpu_addr);
 172         if (r) {
 173                 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
 174                 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
 175                 dev_err(adev->dev, "(%d) UVD bo pin failed\n", r);
 176                 return r;
 177         }
 178
 179         r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr);
 180         if (r) {
 181                 dev_err(adev->dev, "(%d) UVD map failed\n", r);
 182                 return r;
 183         }
 184
 185         amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
 186
 187         for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
 188                 atomic_set(&adev->uvd.handles[i], 0);
 189                 adev->uvd.filp[i] = NULL;
 190         }
 191
 192         /* from uvd v5.0 HW addressing capacity increased to 64 bits */
 193         if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
 194                 adev->uvd.address_64_bit = true;
 195
 196         return 0;
 197 }
 198
 199 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 200 {
 201         int r;
 202
 203         if (adev->uvd.vcpu_bo == NULL)
 204                 return 0;
 205
 206         r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
 207         if (!r) {
 208                 amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
 209                 amdgpu_bo_unpin(adev->uvd.vcpu_bo);
 210                 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
 211         }
 212
 213         amdgpu_bo_unref(&adev->uvd.vcpu_bo);
 214
 215         amdgpu_ring_fini(&adev->uvd.ring);
 216
 217         release_firmware(adev->uvd.fw);
 218
 219         return 0;
 220 }
 221
 222 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
 223 {
 224         struct amdgpu_ring *ring = &adev->uvd.ring;
 225         int i, r;
 226
 227         if (adev->uvd.vcpu_bo == NULL)
 228                 return 0;
 229
 230         for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
 231                 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
 232                 if (handle != 0) {
 233                         struct fence *fence;
 234
 235                         amdgpu_uvd_note_usage(adev);
 236
 237                         r = amdgpu_uvd_get_destroy_msg(ring, handle, &fence);
 238                         if (r) {
 239                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 240                                 continue;
 241                         }
 242
 243                         fence_wait(fence, false);
 244                         fence_put(fence);
 245
 246                         adev->uvd.filp[i] = NULL;
 247                         atomic_set(&adev->uvd.handles[i], 0);
 248                 }
 249         }
 250
 251         return 0;
 252 }
 253
 254 int amdgpu_uvd_resume(struct amdgpu_device *adev)
 255 {
 256         unsigned size;
 257         void *ptr;
 258         const struct common_firmware_header *hdr;
 259         unsigned offset;
 260
 261         if (adev->uvd.vcpu_bo == NULL)
 262                 return -EINVAL;
 263
 264         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 265         offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 266         memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
 267                 (adev->uvd.fw->size) - offset);
 268
 269         size = amdgpu_bo_size(adev->uvd.vcpu_bo);
 270         size -= le32_to_cpu(hdr->ucode_size_bytes);
 271         ptr = adev->uvd.cpu_addr;
 272         ptr += le32_to_cpu(hdr->ucode_size_bytes);
 273
 274         memset(ptr, 0, size);
 275
 276         return 0;
 277 }
 278
 279 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 280 {
 281         struct amdgpu_ring *ring = &adev->uvd.ring;
 282         int i, r;
 283
 284         for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
 285                 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
 286                 if (handle != 0 && adev->uvd.filp[i] == filp) {
 287                         struct fence *fence;
 288
 289                         amdgpu_uvd_note_usage(adev);
 290
 291                         r = amdgpu_uvd_get_destroy_msg(ring, handle, &fence);
 292                         if (r) {
 293                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 294                                 continue;
 295                         }
 296
 297                         fence_wait(fence, false);
 298                         fence_put(fence);
 299
 300                         adev->uvd.filp[i] = NULL;
 301                         atomic_set(&adev->uvd.handles[i], 0);
 302                 }
 303         }
 304 }
 305
 306 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo)
 307 {
 308         int i;
 309         for (i = 0; i < rbo->placement.num_placement; ++i) {
 310                 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
 311                 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 312         }
 313 }
 314
 315 /**
 316  * amdgpu_uvd_cs_pass1 - first parsing round
 317  *
 318  * @ctx: UVD parser context
 319  *
 320  * Make sure UVD message and feedback buffers are in VRAM and
 321  * nobody is violating an 256MB boundary.
 322  */
 323 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
 324 {
 325         struct amdgpu_bo_va_mapping *mapping;
 326         struct amdgpu_bo *bo;
 327         uint32_t cmd, lo, hi;
 328         uint64_t addr;
 329         int r = 0;
 330
 331         lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
 332         hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
 333         addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
 334
 335         mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
 336         if (mapping == NULL) {
 337                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
 338                 return -EINVAL;
 339         }
 340
 341         if (!ctx->parser->adev->uvd.address_64_bit) {
 342                 /* check if it's a message or feedback command */
 343                 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 344                 if (cmd == 0x0 || cmd == 0x3) {
 345                         /* yes, force it into VRAM */
 346                         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 347                         amdgpu_ttm_placement_from_domain(bo, domain);
 348                 }
 349                 amdgpu_uvd_force_into_uvd_segment(bo);
 350
 351                 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 352         }
 353
 354         return r;
 355 }
 356
 357 /**
 358  * amdgpu_uvd_cs_msg_decode - handle UVD decode message
 359  *
 360  * @msg: pointer to message structure
 361  * @buf_sizes: returned buffer sizes
 362  *
 363  * Peek into the decode message and calculate the necessary buffer sizes.
 364  */
 365 static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
 366 {
 367         unsigned stream_type = msg[4];
 368         unsigned width = msg[6];
 369         unsigned height = msg[7];
 370         unsigned dpb_size = msg[9];
 371         unsigned pitch = msg[28];
 372         unsigned level = msg[57];
 373
 374         unsigned width_in_mb = width / 16;
 375         unsigned height_in_mb = ALIGN(height / 16, 2);
 376         unsigned fs_in_mb = width_in_mb * height_in_mb;
 377
 378         unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
 379         unsigned min_ctx_size = 0;
 380
 381         image_size = width * height;
 382         image_size += image_size / 2;
 383         image_size = ALIGN(image_size, 1024);
 384
 385         switch (stream_type) {
 386         case 0: /* H264 */
 387         case 7: /* H264 Perf */
 388                 switch(level) {
 389                 case 30:
 390                         num_dpb_buffer = 8100 / fs_in_mb;
 391                         break;
 392                 case 31:
 393                         num_dpb_buffer = 18000 / fs_in_mb;
 394                         break;
 395                 case 32:
 396                         num_dpb_buffer = 20480 / fs_in_mb;
 397                         break;
 398                 case 41:
 399                         num_dpb_buffer = 32768 / fs_in_mb;
 400                         break;
 401                 case 42:
 402                         num_dpb_buffer = 34816 / fs_in_mb;
 403                         break;
 404                 case 50:
 405                         num_dpb_buffer = 110400 / fs_in_mb;
 406                         break;
 407                 case 51:
 408                         num_dpb_buffer = 184320 / fs_in_mb;
 409                         break;
 410                 default:
 411                         num_dpb_buffer = 184320 / fs_in_mb;
 412                         break;
 413                 }
 414                 num_dpb_buffer++;
 415                 if (num_dpb_buffer > 17)
 416                         num_dpb_buffer = 17;
 417
 418                 /* reference picture buffer */
 419                 min_dpb_size = image_size * num_dpb_buffer;
 420
 421                 /* macroblock context buffer */
 422                 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
 423
 424                 /* IT surface buffer */
 425                 min_dpb_size += width_in_mb * height_in_mb * 32;
 426                 break;
 427
 428         case 1: /* VC1 */
 429
 430                 /* reference picture buffer */
 431                 min_dpb_size = image_size * 3;
 432
 433                 /* CONTEXT_BUFFER */
 434                 min_dpb_size += width_in_mb * height_in_mb * 128;
 435
 436                 /* IT surface buffer */
 437                 min_dpb_size += width_in_mb * 64;
 438
 439                 /* DB surface buffer */
 440                 min_dpb_size += width_in_mb * 128;
 441
 442                 /* BP */
 443                 tmp = max(width_in_mb, height_in_mb);
 444                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 445                 break;
 446
 447         case 3: /* MPEG2 */
 448
 449                 /* reference picture buffer */
 450                 min_dpb_size = image_size * 3;
 451                 break;
 452
 453         case 4: /* MPEG4 */
 454
 455                 /* reference picture buffer */
 456                 min_dpb_size = image_size * 3;
 457
 458                 /* CM */
 459                 min_dpb_size += width_in_mb * height_in_mb * 64;
 460
 461                 /* IT surface buffer */
 462                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 463                 break;
 464
 465         case 16: /* H265 */
 466                 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
 467                 image_size = ALIGN(image_size, 256);
 468
 469                 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
 470                 min_dpb_size = image_size * num_dpb_buffer;
 471                 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
 472                                            * 16 * num_dpb_buffer + 52 * 1024;
 473                 break;
 474
 475         default:
 476                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 477                 return -EINVAL;
 478         }
 479
 480         if (width > pitch) {
 481                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 482                 return -EINVAL;
 483         }
 484
 485         if (dpb_size < min_dpb_size) {
 486                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 487                           dpb_size, min_dpb_size);
 488                 return -EINVAL;
 489         }
 490
 491         buf_sizes[0x1] = dpb_size;
 492         buf_sizes[0x2] = image_size;
 493         buf_sizes[0x4] = min_ctx_size;
 494         return 0;
 495 }
 496
 497 /**
 498  * amdgpu_uvd_cs_msg - handle UVD message
 499  *
 500  * @ctx: UVD parser context
 501  * @bo: buffer object containing the message
 502  * @offset: offset into the buffer object
 503  *
 504  * Peek into the UVD message and extract the session id.
 505  * Make sure that we don't open up to many sessions.
 506  */
 507 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
 508                              struct amdgpu_bo *bo, unsigned offset)
 509 {
 510         struct amdgpu_device *adev = ctx->parser->adev;
 511         int32_t *msg, msg_type, handle;
 512         void *ptr;
 513         long r;
 514         int i;
 515
 516         if (offset & 0x3F) {
 517                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 518                 return -EINVAL;
 519         }
 520
 521         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false,
 522                                                 MAX_SCHEDULE_TIMEOUT);
 523         if (r < 0) {
 524                 DRM_ERROR("Failed waiting for UVD message (%ld)!\n", r);
 525                 return r;
 526         }
 527
 528         r = amdgpu_bo_kmap(bo, &ptr);
 529         if (r) {
 530                 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
 531                 return r;
 532         }
 533
 534         msg = ptr + offset;
 535
 536         msg_type = msg[1];
 537         handle = msg[2];
 538
 539         if (handle == 0) {
 540                 DRM_ERROR("Invalid UVD handle!\n");
 541                 return -EINVAL;
 542         }
 543
 544         if (msg_type == 1) {
 545                 /* it's a decode msg, calc buffer sizes */
 546                 r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes);
 547                 amdgpu_bo_kunmap(bo);
 548                 if (r)
 549                         return r;
 550
 551         } else if (msg_type == 2) {
 552                 /* it's a destroy msg, free the handle */
 553                 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
 554                         atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
 555                 amdgpu_bo_kunmap(bo);
 556                 return 0;
 557         } else {
 558                 /* it's a create msg */
 559                 amdgpu_bo_kunmap(bo);
 560
 561                 if (msg_type != 0) {
 562                         DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
 563                         return -EINVAL;
 564                 }
 565
 566                 /* it's a create msg, no special handling needed */
 567         }
 568
 569         /* create or decode, validate the handle */
 570         for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
 571                 if (atomic_read(&adev->uvd.handles[i]) == handle)
 572                         return 0;
 573         }
 574
 575         /* handle not found try to alloc a new one */
 576         for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
 577                 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
 578                         adev->uvd.filp[i] = ctx->parser->filp;
 579                         return 0;
 580                 }
 581         }
 582
 583         DRM_ERROR("No more free UVD handles!\n");
 584         return -EINVAL;
 585 }
 586
 587 /**
 588  * amdgpu_uvd_cs_pass2 - second parsing round
 589  *
 590  * @ctx: UVD parser context
 591  *
 592  * Patch buffer addresses, make sure buffer sizes are correct.
 593  */
 594 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
 595 {
 596         struct amdgpu_bo_va_mapping *mapping;
 597         struct amdgpu_bo *bo;
 598         struct amdgpu_ib *ib;
 599         uint32_t cmd, lo, hi;
 600         uint64_t start, end;
 601         uint64_t addr;
 602         int r;
 603
 604         lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
 605         hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
 606         addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
 607
 608         mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
 609         if (mapping == NULL)
 610                 return -EINVAL;
 611
 612         start = amdgpu_bo_gpu_offset(bo);
 613
 614         end = (mapping->it.last + 1 - mapping->it.start);
 615         end = end * AMDGPU_GPU_PAGE_SIZE + start;
 616
 617         addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
 618         start += addr;
 619
 620         ib = &ctx->parser->ibs[ctx->ib_idx];
 621         ib->ptr[ctx->data0] = start & 0xFFFFFFFF;
 622         ib->ptr[ctx->data1] = start >> 32;
 623
 624         cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 625         if (cmd < 0x4) {
 626                 if ((end - start) < ctx->buf_sizes[cmd]) {
 627                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 628                                   (unsigned)(end - start),
 629                                   ctx->buf_sizes[cmd]);
 630                         return -EINVAL;
 631                 }
 632
 633         } else if (cmd == 0x206) {
 634                 if ((end - start) < ctx->buf_sizes[4]) {
 635                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 636                                           (unsigned)(end - start),
 637                                           ctx->buf_sizes[4]);
 638                         return -EINVAL;
 639                 }
 640         } else if ((cmd != 0x100) && (cmd != 0x204)) {
 641                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 642                 return -EINVAL;
 643         }
 644
 645         if (!ctx->parser->adev->uvd.address_64_bit) {
 646                 if ((start >> 28) != ((end - 1) >> 28)) {
 647                         DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
 648                                   start, end);
 649                         return -EINVAL;
 650                 }
 651
 652                 if ((cmd == 0 || cmd == 0x3) &&
 653                     (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
 654                         DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
 655                                   start, end);
 656                         return -EINVAL;
 657                 }
 658         }
 659
 660         if (cmd == 0) {
 661                 ctx->has_msg_cmd = true;
 662                 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
 663                 if (r)
 664                         return r;
 665         } else if (!ctx->has_msg_cmd) {
 666                 DRM_ERROR("Message needed before other commands are send!\n");
 667                 return -EINVAL;
 668         }
 669
 670         return 0;
 671 }
 672
 673 /**
 674  * amdgpu_uvd_cs_reg - parse register writes
 675  *
 676  * @ctx: UVD parser context
 677  * @cb: callback function
 678  *
 679  * Parse the register writes, call cb on each complete command.
 680  */
 681 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
 682                              int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 683 {
 684         struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx];
 685         int i, r;
 686
 687         ctx->idx++;
 688         for (i = 0; i <= ctx->count; ++i) {
 689                 unsigned reg = ctx->reg + i;
 690
 691                 if (ctx->idx >= ib->length_dw) {
 692                         DRM_ERROR("Register command after end of CS!\n");
 693                         return -EINVAL;
 694                 }
 695
 696                 switch (reg) {
 697                 case mmUVD_GPCOM_VCPU_DATA0:
 698                         ctx->data0 = ctx->idx;
 699                         break;
 700                 case mmUVD_GPCOM_VCPU_DATA1:
 701                         ctx->data1 = ctx->idx;
 702                         break;
 703                 case mmUVD_GPCOM_VCPU_CMD:
 704                         r = cb(ctx);
 705                         if (r)
 706                                 return r;
 707                         break;
 708                 case mmUVD_ENGINE_CNTL:
 709                         break;
 710                 default:
 711                         DRM_ERROR("Invalid reg 0x%X!\n", reg);
 712                         return -EINVAL;
 713                 }
 714                 ctx->idx++;
 715         }
 716         return 0;
 717 }
 718
 719 /**
 720  * amdgpu_uvd_cs_packets - parse UVD packets
 721  *
 722  * @ctx: UVD parser context
 723  * @cb: callback function
 724  *
 725  * Parse the command stream packets.
 726  */
 727 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
 728                                  int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 729 {
 730         struct amdgpu_ib *ib = &ctx->parser->ibs[ctx->ib_idx];
 731         int r;
 732
 733         for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
 734                 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
 735                 unsigned type = CP_PACKET_GET_TYPE(cmd);
 736                 switch (type) {
 737                 case PACKET_TYPE0:
 738                         ctx->reg = CP_PACKET0_GET_REG(cmd);
 739                         ctx->count = CP_PACKET_GET_COUNT(cmd);
 740                         r = amdgpu_uvd_cs_reg(ctx, cb);
 741                         if (r)
 742                                 return r;
 743                         break;
 744                 case PACKET_TYPE2:
 745                         ++ctx->idx;
 746                         break;
 747                 default:
 748                         DRM_ERROR("Unknown packet type %d !\n", type);
 749                         return -EINVAL;
 750                 }
 751         }
 752         return 0;
 753 }
 754
 755 /**
 756  * amdgpu_uvd_ring_parse_cs - UVD command submission parser
 757  *
 758  * @parser: Command submission parser context
 759  *
 760  * Parse the command stream, patch in addresses as necessary.
 761  */
 762 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
 763 {
 764         struct amdgpu_uvd_cs_ctx ctx = {};
 765         unsigned buf_sizes[] = {
 766                 [0x00000000]    =       2048,
 767                 [0x00000001]    =       0xFFFFFFFF,
 768                 [0x00000002]    =       0xFFFFFFFF,
 769                 [0x00000003]    =       2048,
 770                 [0x00000004]    =       0xFFFFFFFF,
 771         };
 772         struct amdgpu_ib *ib = &parser->ibs[ib_idx];
 773         int r;
 774
 775         if (ib->length_dw % 16) {
 776                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 777                           ib->length_dw);
 778                 return -EINVAL;
 779         }
 780
 781         ctx.parser = parser;
 782         ctx.buf_sizes = buf_sizes;
 783         ctx.ib_idx = ib_idx;
 784
 785         /* first round, make sure the buffers are actually in the UVD segment */
 786         r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
 787         if (r)
 788                 return r;
 789
 790         /* second round, patch buffer addresses into the command stream */
 791         r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
 792         if (r)
 793                 return r;
 794
 795         if (!ctx.has_msg_cmd) {
 796                 DRM_ERROR("UVD-IBs need a msg command!\n");
 797                 return -EINVAL;
 798         }
 799
 800         amdgpu_uvd_note_usage(ctx.parser->adev);
 801
 802         return 0;
 803 }
 804
 805 static int amdgpu_uvd_free_job(
 806         struct amdgpu_job *sched_job)
 807 {
 808         amdgpu_ib_free(sched_job->adev, sched_job->ibs);
 809         kfree(sched_job->ibs);
 810         return 0;
 811 }
 812
 813 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring,
 814                                struct amdgpu_bo *bo,
 815                                struct fence **fence)
 816 {
 817         struct ttm_validate_buffer tv;
 818         struct ww_acquire_ctx ticket;
 819         struct list_head head;
 820         struct amdgpu_ib *ib = NULL;
 821         struct fence *f = NULL;
 822         struct amdgpu_device *adev = ring->adev;
 823         uint64_t addr;
 824         int i, r;
 825
 826         memset(&tv, 0, sizeof(tv));
 827         tv.bo = &bo->tbo;
 828
 829         INIT_LIST_HEAD(&head);
 830         list_add(&tv.head, &head);
 831
 832         r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
 833         if (r)
 834                 return r;
 835
 836         if (!bo->adev->uvd.address_64_bit) {
 837                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
 838                 amdgpu_uvd_force_into_uvd_segment(bo);
 839         }
 840
 841         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 842         if (r)
 843                 goto err;
 844         ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
 845         if (!ib) {
 846                 r = -ENOMEM;
 847                 goto err;
 848         }
 849         r = amdgpu_ib_get(ring, NULL, 64, ib);
 850         if (r)
 851                 goto err1;
 852
 853         addr = amdgpu_bo_gpu_offset(bo);
 854         ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
 855         ib->ptr[1] = addr;
 856         ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
 857         ib->ptr[3] = addr >> 32;
 858         ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
 859         ib->ptr[5] = 0;
 860         for (i = 6; i < 16; ++i)
 861                 ib->ptr[i] = PACKET2(0);
 862         ib->length_dw = 16;
 863
 864         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
 865                                                  &amdgpu_uvd_free_job,
 866                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 867                                                  &f);
 868         if (r)
 869                 goto err2;
 870
 871         ttm_eu_fence_buffer_objects(&ticket, &head, f);
 872
 873         if (fence)
 874                 *fence = fence_get(f);
 875         amdgpu_bo_unref(&bo);
 876         fence_put(f);
 877         if (amdgpu_enable_scheduler)
 878                 return 0;
 879
 880         amdgpu_ib_free(ring->adev, ib);
 881         kfree(ib);
 882         return 0;
 883 err2:
 884         amdgpu_ib_free(ring->adev, ib);
 885 err1:
 886         kfree(ib);
 887 err:
 888         ttm_eu_backoff_reservation(&ticket, &head);
 889         return r;
 890 }
 891
 892 /* multiple fence commands without any stream commands in between can
 893    crash the vcpu so just try to emmit a dummy create/destroy msg to
 894    avoid this */
 895 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 896                               struct fence **fence)
 897 {
 898         struct amdgpu_device *adev = ring->adev;
 899         struct amdgpu_bo *bo;
 900         uint32_t *msg;
 901         int r, i;
 902
 903         r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
 904                              AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &bo);
 905         if (r)
 906                 return r;
 907
 908         r = amdgpu_bo_reserve(bo, false);
 909         if (r) {
 910                 amdgpu_bo_unref(&bo);
 911                 return r;
 912         }
 913
 914         r = amdgpu_bo_kmap(bo, (void **)&msg);
 915         if (r) {
 916                 amdgpu_bo_unreserve(bo);
 917                 amdgpu_bo_unref(&bo);
 918                 return r;
 919         }
 920
 921         /* stitch together an UVD create msg */
 922         msg[0] = cpu_to_le32(0x00000de4);
 923         msg[1] = cpu_to_le32(0x00000000);
 924         msg[2] = cpu_to_le32(handle);
 925         msg[3] = cpu_to_le32(0x00000000);
 926         msg[4] = cpu_to_le32(0x00000000);
 927         msg[5] = cpu_to_le32(0x00000000);
 928         msg[6] = cpu_to_le32(0x00000000);
 929         msg[7] = cpu_to_le32(0x00000780);
 930         msg[8] = cpu_to_le32(0x00000440);
 931         msg[9] = cpu_to_le32(0x00000000);
 932         msg[10] = cpu_to_le32(0x01b37000);
 933         for (i = 11; i < 1024; ++i)
 934                 msg[i] = cpu_to_le32(0x0);
 935
 936         amdgpu_bo_kunmap(bo);
 937         amdgpu_bo_unreserve(bo);
 938
 939         return amdgpu_uvd_send_msg(ring, bo, fence);
 940 }
 941
 942 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 943                                struct fence **fence)
 944 {
 945         struct amdgpu_device *adev = ring->adev;
 946         struct amdgpu_bo *bo;
 947         uint32_t *msg;
 948         int r, i;
 949
 950         r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
 951                              AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &bo);
 952         if (r)
 953                 return r;
 954
 955         r = amdgpu_bo_reserve(bo, false);
 956         if (r) {
 957                 amdgpu_bo_unref(&bo);
 958                 return r;
 959         }
 960
 961         r = amdgpu_bo_kmap(bo, (void **)&msg);
 962         if (r) {
 963                 amdgpu_bo_unreserve(bo);
 964                 amdgpu_bo_unref(&bo);
 965                 return r;
 966         }
 967
 968         /* stitch together an UVD destroy msg */
 969         msg[0] = cpu_to_le32(0x00000de4);
 970         msg[1] = cpu_to_le32(0x00000002);
 971         msg[2] = cpu_to_le32(handle);
 972         msg[3] = cpu_to_le32(0x00000000);
 973         for (i = 4; i < 1024; ++i)
 974                 msg[i] = cpu_to_le32(0x0);
 975
 976         amdgpu_bo_kunmap(bo);
 977         amdgpu_bo_unreserve(bo);
 978
 979         return amdgpu_uvd_send_msg(ring, bo, fence);
 980 }
 981
 982 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
 983 {
 984         struct amdgpu_device *adev =
 985                 container_of(work, struct amdgpu_device, uvd.idle_work.work);
 986         unsigned i, fences, handles = 0;
 987
 988         fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
 989
 990         for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
 991                 if (atomic_read(&adev->uvd.handles[i]))
 992                         ++handles;
 993
 994         if (fences == 0 && handles == 0) {
 995                 if (adev->pm.dpm_enabled) {
 996                         amdgpu_dpm_enable_uvd(adev, false);
 997                 } else {
 998                         amdgpu_asic_set_uvd_clocks(adev, 0, 0);
 999                 }
1000         } else {
1001                 schedule_delayed_work(&adev->uvd.idle_work,
1002                                       msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
1003         }
1004 }
1005
1006 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev)
1007 {
1008         bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1009         set_clocks &= schedule_delayed_work(&adev->uvd.idle_work,
1010                                             msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
1011
1012         if (set_clocks) {
1013                 if (adev->pm.dpm_enabled) {
1014                         amdgpu_dpm_enable_uvd(adev, true);
1015                 } else {
1016                         amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1017                 }
1018         }
1019 }