drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  * Authors: Christian König <christian.koenig@amd.com>
  26  */
  27
  28 #include <linux/firmware.h>
  29 #include <linux/module.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm.h>
  32
  33 #include "amdgpu.h"
  34 #include "amdgpu_pm.h"
  35 #include "amdgpu_vce.h"
  36 #include "cikd.h"
  37
  38 /* 1 second timeout */
  39 #define VCE_IDLE_TIMEOUT_MS     1000
  40
  41 /* Firmware Names */
  42 #ifdef CONFIG_DRM_AMDGPU_CIK
  43 #define FIRMWARE_BONAIRE        "radeon/bonaire_vce.bin"
  44 #define FIRMWARE_KABINI         "radeon/kabini_vce.bin"
  45 #define FIRMWARE_KAVERI         "radeon/kaveri_vce.bin"
  46 #define FIRMWARE_HAWAII         "radeon/hawaii_vce.bin"
  47 #define FIRMWARE_MULLINS        "radeon/mullins_vce.bin"
  48 #endif
  49 #define FIRMWARE_TONGA          "amdgpu/tonga_vce.bin"
  50 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_vce.bin"
  51 #define FIRMWARE_FIJI           "amdgpu/fiji_vce.bin"
  52
  53 #ifdef CONFIG_DRM_AMDGPU_CIK
  54 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  55 MODULE_FIRMWARE(FIRMWARE_KABINI);
  56 MODULE_FIRMWARE(FIRMWARE_KAVERI);
  57 MODULE_FIRMWARE(FIRMWARE_HAWAII);
  58 MODULE_FIRMWARE(FIRMWARE_MULLINS);
  59 #endif
  60 MODULE_FIRMWARE(FIRMWARE_TONGA);
  61 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
  62 MODULE_FIRMWARE(FIRMWARE_FIJI);
  63
  64 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
  65
  66 /**
  67  * amdgpu_vce_init - allocate memory, load vce firmware
  68  *
  69  * @adev: amdgpu_device pointer
  70  *
  71  * First step to get VCE online, allocate memory and load the firmware
  72  */
  73 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
  74 {
  75         const char *fw_name;
  76         const struct common_firmware_header *hdr;
  77         unsigned ucode_version, version_major, version_minor, binary_id;
  78         int i, r;
  79
  80         INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
  81
  82         switch (adev->asic_type) {
  83 #ifdef CONFIG_DRM_AMDGPU_CIK
  84         case CHIP_BONAIRE:
  85                 fw_name = FIRMWARE_BONAIRE;
  86                 break;
  87         case CHIP_KAVERI:
  88                 fw_name = FIRMWARE_KAVERI;
  89                 break;
  90         case CHIP_KABINI:
  91                 fw_name = FIRMWARE_KABINI;
  92                 break;
  93         case CHIP_HAWAII:
  94                 fw_name = FIRMWARE_HAWAII;
  95                 break;
  96         case CHIP_MULLINS:
  97                 fw_name = FIRMWARE_MULLINS;
  98                 break;
  99 #endif
 100         case CHIP_TONGA:
 101                 fw_name = FIRMWARE_TONGA;
 102                 break;
 103         case CHIP_CARRIZO:
 104                 fw_name = FIRMWARE_CARRIZO;
 105                 break;
 106         case CHIP_FIJI:
 107                 fw_name = FIRMWARE_FIJI;
 108                 break;
 109
 110         default:
 111                 return -EINVAL;
 112         }
 113
 114         r = request_firmware(&adev->vce.fw, fw_name, adev->dev);
 115         if (r) {
 116                 dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
 117                         fw_name);
 118                 return r;
 119         }
 120
 121         r = amdgpu_ucode_validate(adev->vce.fw);
 122         if (r) {
 123                 dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
 124                         fw_name);
 125                 release_firmware(adev->vce.fw);
 126                 adev->vce.fw = NULL;
 127                 return r;
 128         }
 129
 130         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 131
 132         ucode_version = le32_to_cpu(hdr->ucode_version);
 133         version_major = (ucode_version >> 20) & 0xfff;
 134         version_minor = (ucode_version >> 8) & 0xfff;
 135         binary_id = ucode_version & 0xff;
 136         DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
 137                 version_major, version_minor, binary_id);
 138         adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
 139                                 (binary_id << 8));
 140
 141         /* allocate firmware, stack and heap BO */
 142
 143         r = amdgpu_bo_create(adev, size, PAGE_SIZE, true,
 144                              AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->vce.vcpu_bo);
 145         if (r) {
 146                 dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
 147                 return r;
 148         }
 149
 150         r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 151         if (r) {
 152                 amdgpu_bo_unref(&adev->vce.vcpu_bo);
 153                 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 154                 return r;
 155         }
 156
 157         r = amdgpu_bo_pin(adev->vce.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
 158                           &adev->vce.gpu_addr);
 159         amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 160         if (r) {
 161                 amdgpu_bo_unref(&adev->vce.vcpu_bo);
 162                 dev_err(adev->dev, "(%d) VCE bo pin failed\n", r);
 163                 return r;
 164         }
 165
 166         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 167                 atomic_set(&adev->vce.handles[i], 0);
 168                 adev->vce.filp[i] = NULL;
 169         }
 170
 171         return 0;
 172 }
 173
 174 /**
 175  * amdgpu_vce_fini - free memory
 176  *
 177  * @adev: amdgpu_device pointer
 178  *
 179  * Last step on VCE teardown, free firmware memory
 180  */
 181 int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 182 {
 183         if (adev->vce.vcpu_bo == NULL)
 184                 return 0;
 185
 186         amdgpu_bo_unref(&adev->vce.vcpu_bo);
 187
 188         amdgpu_ring_fini(&adev->vce.ring[0]);
 189         amdgpu_ring_fini(&adev->vce.ring[1]);
 190
 191         release_firmware(adev->vce.fw);
 192
 193         return 0;
 194 }
 195
 196 /**
 197  * amdgpu_vce_suspend - unpin VCE fw memory
 198  *
 199  * @adev: amdgpu_device pointer
 200  *
 201  */
 202 int amdgpu_vce_suspend(struct amdgpu_device *adev)
 203 {
 204         int i;
 205
 206         if (adev->vce.vcpu_bo == NULL)
 207                 return 0;
 208
 209         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 210                 if (atomic_read(&adev->vce.handles[i]))
 211                         break;
 212
 213         if (i == AMDGPU_MAX_VCE_HANDLES)
 214                 return 0;
 215
 216         /* TODO: suspending running encoding sessions isn't supported */
 217         return -EINVAL;
 218 }
 219
 220 /**
 221  * amdgpu_vce_resume - pin VCE fw memory
 222  *
 223  * @adev: amdgpu_device pointer
 224  *
 225  */
 226 int amdgpu_vce_resume(struct amdgpu_device *adev)
 227 {
 228         void *cpu_addr;
 229         const struct common_firmware_header *hdr;
 230         unsigned offset;
 231         int r;
 232
 233         if (adev->vce.vcpu_bo == NULL)
 234                 return -EINVAL;
 235
 236         r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 237         if (r) {
 238                 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 239                 return r;
 240         }
 241
 242         r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
 243         if (r) {
 244                 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 245                 dev_err(adev->dev, "(%d) VCE map failed\n", r);
 246                 return r;
 247         }
 248
 249         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 250         offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 251         memcpy(cpu_addr, (adev->vce.fw->data) + offset,
 252                 (adev->vce.fw->size) - offset);
 253
 254         amdgpu_bo_kunmap(adev->vce.vcpu_bo);
 255
 256         amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 257
 258         return 0;
 259 }
 260
 261 /**
 262  * amdgpu_vce_idle_work_handler - power off VCE
 263  *
 264  * @work: pointer to work structure
 265  *
 266  * power of VCE when it's not used any more
 267  */
 268 static void amdgpu_vce_idle_work_handler(struct work_struct *work)
 269 {
 270         struct amdgpu_device *adev =
 271                 container_of(work, struct amdgpu_device, vce.idle_work.work);
 272
 273         if ((amdgpu_fence_count_emitted(&adev->vce.ring[0]) == 0) &&
 274             (amdgpu_fence_count_emitted(&adev->vce.ring[1]) == 0)) {
 275                 if (adev->pm.dpm_enabled) {
 276                         amdgpu_dpm_enable_vce(adev, false);
 277                 } else {
 278                         amdgpu_asic_set_vce_clocks(adev, 0, 0);
 279                 }
 280         } else {
 281                 schedule_delayed_work(&adev->vce.idle_work,
 282                                       msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
 283         }
 284 }
 285
 286 /**
 287  * amdgpu_vce_note_usage - power up VCE
 288  *
 289  * @adev: amdgpu_device pointer
 290  *
 291  * Make sure VCE is powerd up when we want to use it
 292  */
 293 static void amdgpu_vce_note_usage(struct amdgpu_device *adev)
 294 {
 295         bool streams_changed = false;
 296         bool set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
 297         set_clocks &= schedule_delayed_work(&adev->vce.idle_work,
 298                                             msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
 299
 300         if (adev->pm.dpm_enabled) {
 301                 /* XXX figure out if the streams changed */
 302                 streams_changed = false;
 303         }
 304
 305         if (set_clocks || streams_changed) {
 306                 if (adev->pm.dpm_enabled) {
 307                         amdgpu_dpm_enable_vce(adev, true);
 308                 } else {
 309                         amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
 310                 }
 311         }
 312 }
 313
 314 /**
 315  * amdgpu_vce_free_handles - free still open VCE handles
 316  *
 317  * @adev: amdgpu_device pointer
 318  * @filp: drm file pointer
 319  *
 320  * Close all VCE handles still open by this file pointer
 321  */
 322 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 323 {
 324         struct amdgpu_ring *ring = &adev->vce.ring[0];
 325         int i, r;
 326         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 327                 uint32_t handle = atomic_read(&adev->vce.handles[i]);
 328                 if (!handle || adev->vce.filp[i] != filp)
 329                         continue;
 330
 331                 amdgpu_vce_note_usage(adev);
 332
 333                 r = amdgpu_vce_get_destroy_msg(ring, handle, NULL);
 334                 if (r)
 335                         DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
 336
 337                 adev->vce.filp[i] = NULL;
 338                 atomic_set(&adev->vce.handles[i], 0);
 339         }
 340 }
 341
 342 static int amdgpu_vce_free_job(
 343         struct amdgpu_cs_parser *sched_job)
 344 {
 345         amdgpu_ib_free(sched_job->adev, sched_job->ibs);
 346         kfree(sched_job->ibs);
 347         return 0;
 348 }
 349
 350 /**
 351  * amdgpu_vce_get_create_msg - generate a VCE create msg
 352  *
 353  * @adev: amdgpu_device pointer
 354  * @ring: ring we should submit the msg to
 355  * @handle: VCE session handle to use
 356  * @fence: optional fence to return
 357  *
 358  * Open up a stream for HW test
 359  */
 360 int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 361                               struct amdgpu_fence **fence)
 362 {
 363         const unsigned ib_size_dw = 1024;
 364         struct amdgpu_ib *ib = NULL;
 365         struct amdgpu_device *adev = ring->adev;
 366         uint64_t dummy;
 367         int i, r;
 368
 369         ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
 370         if (!ib)
 371                 return -ENOMEM;
 372         r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, ib);
 373         if (r) {
 374                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 375                 kfree(ib);
 376                 return r;
 377         }
 378
 379         dummy = ib->gpu_addr + 1024;
 380
 381         /* stitch together an VCE create msg */
 382         ib->length_dw = 0;
 383         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 384         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 385         ib->ptr[ib->length_dw++] = handle;
 386
 387         ib->ptr[ib->length_dw++] = 0x00000030; /* len */
 388         ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
 389         ib->ptr[ib->length_dw++] = 0x00000000;
 390         ib->ptr[ib->length_dw++] = 0x00000042;
 391         ib->ptr[ib->length_dw++] = 0x0000000a;
 392         ib->ptr[ib->length_dw++] = 0x00000001;
 393         ib->ptr[ib->length_dw++] = 0x00000080;
 394         ib->ptr[ib->length_dw++] = 0x00000060;
 395         ib->ptr[ib->length_dw++] = 0x00000100;
 396         ib->ptr[ib->length_dw++] = 0x00000100;
 397         ib->ptr[ib->length_dw++] = 0x0000000c;
 398         ib->ptr[ib->length_dw++] = 0x00000000;
 399
 400         ib->ptr[ib->length_dw++] = 0x00000014; /* len */
 401         ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
 402         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 403         ib->ptr[ib->length_dw++] = dummy;
 404         ib->ptr[ib->length_dw++] = 0x00000001;
 405
 406         for (i = ib->length_dw; i < ib_size_dw; ++i)
 407                 ib->ptr[i] = 0x0;
 408
 409         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
 410                                                  &amdgpu_vce_free_job,
 411                                                  AMDGPU_FENCE_OWNER_UNDEFINED);
 412         if (r)
 413                 goto err;
 414         if (fence)
 415                 *fence = amdgpu_fence_ref(ib->fence);
 416         if (amdgpu_enable_scheduler)
 417                 return 0;
 418 err:
 419         amdgpu_ib_free(adev, ib);
 420         kfree(ib);
 421         return r;
 422 }
 423
 424 /**
 425  * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
 426  *
 427  * @adev: amdgpu_device pointer
 428  * @ring: ring we should submit the msg to
 429  * @handle: VCE session handle to use
 430  * @fence: optional fence to return
 431  *
 432  * Close up a stream for HW test or if userspace failed to do so
 433  */
 434 int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 435                                struct amdgpu_fence **fence)
 436 {
 437         const unsigned ib_size_dw = 1024;
 438         struct amdgpu_ib *ib = NULL;
 439         struct amdgpu_device *adev = ring->adev;
 440         uint64_t dummy;
 441         int i, r;
 442
 443         ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
 444         if (!ib)
 445                 return -ENOMEM;
 446
 447         r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, ib);
 448         if (r) {
 449                 kfree(ib);
 450                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 451                 return r;
 452         }
 453
 454         dummy = ib->gpu_addr + 1024;
 455
 456         /* stitch together an VCE destroy msg */
 457         ib->length_dw = 0;
 458         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 459         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 460         ib->ptr[ib->length_dw++] = handle;
 461
 462         ib->ptr[ib->length_dw++] = 0x00000014; /* len */
 463         ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
 464         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 465         ib->ptr[ib->length_dw++] = dummy;
 466         ib->ptr[ib->length_dw++] = 0x00000001;
 467
 468         ib->ptr[ib->length_dw++] = 0x00000008; /* len */
 469         ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
 470
 471         for (i = ib->length_dw; i < ib_size_dw; ++i)
 472                 ib->ptr[i] = 0x0;
 473         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
 474                                                  &amdgpu_vce_free_job,
 475                                                  AMDGPU_FENCE_OWNER_UNDEFINED);
 476         if (r)
 477                 goto err;
 478         if (fence)
 479                 *fence = amdgpu_fence_ref(ib->fence);
 480         if (amdgpu_enable_scheduler)
 481                 return 0;
 482 err:
 483         amdgpu_ib_free(adev, ib);
 484         kfree(ib);
 485         return r;
 486 }
 487
 488 /**
 489  * amdgpu_vce_cs_reloc - command submission relocation
 490  *
 491  * @p: parser context
 492  * @lo: address of lower dword
 493  * @hi: address of higher dword
 494  * @size: minimum size
 495  *
 496  * Patch relocation inside command stream with real buffer address
 497  */
 498 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
 499                                int lo, int hi, unsigned size, uint32_t index)
 500 {
 501         struct amdgpu_bo_va_mapping *mapping;
 502         struct amdgpu_ib *ib = &p->ibs[ib_idx];
 503         struct amdgpu_bo *bo;
 504         uint64_t addr;
 505
 506         if (index == 0xffffffff)
 507                 index = 0;
 508
 509         addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
 510                ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
 511         addr += ((uint64_t)size) * ((uint64_t)index);
 512
 513         mapping = amdgpu_cs_find_mapping(p, addr, &bo);
 514         if (mapping == NULL) {
 515                 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
 516                           addr, lo, hi, size, index);
 517                 return -EINVAL;
 518         }
 519
 520         if ((addr + (uint64_t)size) >
 521             ((uint64_t)mapping->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 522                 DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",
 523                           addr, lo, hi);
 524                 return -EINVAL;
 525         }
 526
 527         addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
 528         addr += amdgpu_bo_gpu_offset(bo);
 529         addr -= ((uint64_t)size) * ((uint64_t)index);
 530
 531         ib->ptr[lo] = addr & 0xFFFFFFFF;
 532         ib->ptr[hi] = addr >> 32;
 533
 534         return 0;
 535 }
 536
 537 /**
 538  * amdgpu_vce_validate_handle - validate stream handle
 539  *
 540  * @p: parser context
 541  * @handle: handle to validate
 542  * @allocated: allocated a new handle?
 543  *
 544  * Validates the handle and return the found session index or -EINVAL
 545  * we we don't have another free session index.
 546  */
 547 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
 548                                       uint32_t handle, bool *allocated)
 549 {
 550         unsigned i;
 551
 552         *allocated = false;
 553
 554         /* validate the handle */
 555         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 556                 if (atomic_read(&p->adev->vce.handles[i]) == handle) {
 557                         if (p->adev->vce.filp[i] != p->filp) {
 558                                 DRM_ERROR("VCE handle collision detected!\n");
 559                                 return -EINVAL;
 560                         }
 561                         return i;
 562                 }
 563         }
 564
 565         /* handle not found try to alloc a new one */
 566         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 567                 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
 568                         p->adev->vce.filp[i] = p->filp;
 569                         p->adev->vce.img_size[i] = 0;
 570                         *allocated = true;
 571                         return i;
 572                 }
 573         }
 574
 575         DRM_ERROR("No more free VCE handles!\n");
 576         return -EINVAL;
 577 }
 578
 579 /**
 580  * amdgpu_vce_cs_parse - parse and validate the command stream
 581  *
 582  * @p: parser context
 583  *
 584  */
 585 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
 586 {
 587         struct amdgpu_ib *ib = &p->ibs[ib_idx];
 588         unsigned fb_idx = 0, bs_idx = 0;
 589         int session_idx = -1;
 590         bool destroyed = false;
 591         bool created = false;
 592         bool allocated = false;
 593         uint32_t tmp, handle = 0;
 594         uint32_t *size = &tmp;
 595         int i, r = 0, idx = 0;
 596
 597         amdgpu_vce_note_usage(p->adev);
 598
 599         while (idx < ib->length_dw) {
 600                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 601                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 602
 603                 if ((len < 8) || (len & 3)) {
 604                         DRM_ERROR("invalid VCE command length (%d)!\n", len);
 605                         r = -EINVAL;
 606                         goto out;
 607                 }
 608
 609                 if (destroyed) {
 610                         DRM_ERROR("No other command allowed after destroy!\n");
 611                         r = -EINVAL;
 612                         goto out;
 613                 }
 614
 615                 switch (cmd) {
 616                 case 0x00000001: // session
 617                         handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
 618                         session_idx = amdgpu_vce_validate_handle(p, handle,
 619                                                                  &allocated);
 620                         if (session_idx < 0)
 621                                 return session_idx;
 622                         size = &p->adev->vce.img_size[session_idx];
 623                         break;
 624
 625                 case 0x00000002: // task info
 626                         fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
 627                         bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
 628                         break;
 629
 630                 case 0x01000001: // create
 631                         created = true;
 632                         if (!allocated) {
 633                                 DRM_ERROR("Handle already in use!\n");
 634                                 r = -EINVAL;
 635                                 goto out;
 636                         }
 637
 638                         *size = amdgpu_get_ib_value(p, ib_idx, idx + 8) *
 639                                 amdgpu_get_ib_value(p, ib_idx, idx + 10) *
 640                                 8 * 3 / 2;
 641                         break;
 642
 643                 case 0x04000001: // config extension
 644                 case 0x04000002: // pic control
 645                 case 0x04000005: // rate control
 646                 case 0x04000007: // motion estimation
 647                 case 0x04000008: // rdo
 648                 case 0x04000009: // vui
 649                 case 0x05000002: // auxiliary buffer
 650                         break;
 651
 652                 case 0x03000001: // encode
 653                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9,
 654                                                 *size, 0);
 655                         if (r)
 656                                 goto out;
 657
 658                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11,
 659                                                 *size / 3, 0);
 660                         if (r)
 661                                 goto out;
 662                         break;
 663
 664                 case 0x02000001: // destroy
 665                         destroyed = true;
 666                         break;
 667
 668                 case 0x05000001: // context buffer
 669                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 670                                                 *size * 2, 0);
 671                         if (r)
 672                                 goto out;
 673                         break;
 674
 675                 case 0x05000004: // video bitstream buffer
 676                         tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
 677                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 678                                                 tmp, bs_idx);
 679                         if (r)
 680                                 goto out;
 681                         break;
 682
 683                 case 0x05000005: // feedback buffer
 684                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 685                                                 4096, fb_idx);
 686                         if (r)
 687                                 goto out;
 688                         break;
 689
 690                 default:
 691                         DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
 692                         r = -EINVAL;
 693                         goto out;
 694                 }
 695
 696                 if (session_idx == -1) {
 697                         DRM_ERROR("no session command at start of IB\n");
 698                         r = -EINVAL;
 699                         goto out;
 700                 }
 701
 702                 idx += len / 4;
 703         }
 704
 705         if (allocated && !created) {
 706                 DRM_ERROR("New session without create command!\n");
 707                 r = -ENOENT;
 708         }
 709
 710 out:
 711         if ((!r && destroyed) || (r && allocated)) {
 712                 /*
 713                  * IB contains a destroy msg or we have allocated an
 714                  * handle and got an error, anyway free the handle
 715                  */
 716                 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 717                         atomic_cmpxchg(&p->adev->vce.handles[i], handle, 0);
 718         }
 719
 720         return r;
 721 }
 722
 723 /**
 724  * amdgpu_vce_ring_emit_semaphore - emit a semaphore command
 725  *
 726  * @ring: engine to use
 727  * @semaphore: address of semaphore
 728  * @emit_wait: true=emit wait, false=emit signal
 729  *
 730  */
 731 bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring,
 732                                     struct amdgpu_semaphore *semaphore,
 733                                     bool emit_wait)
 734 {
 735         uint64_t addr = semaphore->gpu_addr;
 736
 737         amdgpu_ring_write(ring, VCE_CMD_SEMAPHORE);
 738         amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
 739         amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
 740         amdgpu_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0));
 741         if (!emit_wait)
 742                 amdgpu_ring_write(ring, VCE_CMD_END);
 743
 744         return true;
 745 }
 746
 747 /**
 748  * amdgpu_vce_ring_emit_ib - execute indirect buffer
 749  *
 750  * @ring: engine to use
 751  * @ib: the IB to execute
 752  *
 753  */
 754 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 755 {
 756         amdgpu_ring_write(ring, VCE_CMD_IB);
 757         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 758         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 759         amdgpu_ring_write(ring, ib->length_dw);
 760 }
 761
 762 /**
 763  * amdgpu_vce_ring_emit_fence - add a fence command to the ring
 764  *
 765  * @ring: engine to use
 766  * @fence: the fence
 767  *
 768  */
 769 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 770                                 unsigned flags)
 771 {
 772         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 773
 774         amdgpu_ring_write(ring, VCE_CMD_FENCE);
 775         amdgpu_ring_write(ring, addr);
 776         amdgpu_ring_write(ring, upper_32_bits(addr));
 777         amdgpu_ring_write(ring, seq);
 778         amdgpu_ring_write(ring, VCE_CMD_TRAP);
 779         amdgpu_ring_write(ring, VCE_CMD_END);
 780 }
 781
 782 /**
 783  * amdgpu_vce_ring_test_ring - test if VCE ring is working
 784  *
 785  * @ring: the engine to test on
 786  *
 787  */
 788 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
 789 {
 790         struct amdgpu_device *adev = ring->adev;
 791         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 792         unsigned i;
 793         int r;
 794
 795         r = amdgpu_ring_lock(ring, 16);
 796         if (r) {
 797                 DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
 798                           ring->idx, r);
 799                 return r;
 800         }
 801         amdgpu_ring_write(ring, VCE_CMD_END);
 802         amdgpu_ring_unlock_commit(ring);
 803
 804         for (i = 0; i < adev->usec_timeout; i++) {
 805                 if (amdgpu_ring_get_rptr(ring) != rptr)
 806                         break;
 807                 DRM_UDELAY(1);
 808         }
 809
 810         if (i < adev->usec_timeout) {
 811                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 812                          ring->idx, i);
 813         } else {
 814                 DRM_ERROR("amdgpu: ring %d test failed\n",
 815                           ring->idx);
 816                 r = -ETIMEDOUT;
 817         }
 818
 819         return r;
 820 }
 821
 822 /**
 823  * amdgpu_vce_ring_test_ib - test if VCE IBs are working
 824  *
 825  * @ring: the engine to test on
 826  *
 827  */
 828 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring)
 829 {
 830         struct amdgpu_fence *fence = NULL;
 831         int r;
 832
 833         r = amdgpu_vce_get_create_msg(ring, 1, NULL);
 834         if (r) {
 835                 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
 836                 goto error;
 837         }
 838
 839         r = amdgpu_vce_get_destroy_msg(ring, 1, &fence);
 840         if (r) {
 841                 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
 842                 goto error;
 843         }
 844
 845         r = amdgpu_fence_wait(fence, false);
 846         if (r) {
 847                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 848         } else {
 849                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 850         }
 851 error:
 852         amdgpu_fence_unref(&fence);
 853         return r;
 854 }