drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "vid.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34
  35 #include "dce/dce_10_0_d.h"
  36 #include "dce/dce_10_0_sh_mask.h"
  37 #include "dce/dce_10_0_enum.h"
  38 #include "oss/oss_3_0_d.h"
  39 #include "oss/oss_3_0_sh_mask.h"
  40 #include "gmc/gmc_8_1_d.h"
  41 #include "gmc/gmc_8_1_sh_mask.h"
  42
  43 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
  44 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
  45
  46 static const u32 crtc_offsets[] =
  47 {
  48         CRTC0_REGISTER_OFFSET,
  49         CRTC1_REGISTER_OFFSET,
  50         CRTC2_REGISTER_OFFSET,
  51         CRTC3_REGISTER_OFFSET,
  52         CRTC4_REGISTER_OFFSET,
  53         CRTC5_REGISTER_OFFSET,
  54         CRTC6_REGISTER_OFFSET
  55 };
  56
  57 static const u32 hpd_offsets[] =
  58 {
  59         HPD0_REGISTER_OFFSET,
  60         HPD1_REGISTER_OFFSET,
  61         HPD2_REGISTER_OFFSET,
  62         HPD3_REGISTER_OFFSET,
  63         HPD4_REGISTER_OFFSET,
  64         HPD5_REGISTER_OFFSET
  65 };
  66
  67 static const uint32_t dig_offsets[] = {
  68         DIG0_REGISTER_OFFSET,
  69         DIG1_REGISTER_OFFSET,
  70         DIG2_REGISTER_OFFSET,
  71         DIG3_REGISTER_OFFSET,
  72         DIG4_REGISTER_OFFSET,
  73         DIG5_REGISTER_OFFSET,
  74         DIG6_REGISTER_OFFSET
  75 };
  76
  77 static const struct {
  78         uint32_t        reg;
  79         uint32_t        vblank;
  80         uint32_t        vline;
  81         uint32_t        hpd;
  82
  83 } interrupt_status_offsets[] = { {
  84         .reg = mmDISP_INTERRUPT_STATUS,
  85         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  86         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  87         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  88 }, {
  89         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  90         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  91         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  92         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  93 }, {
  94         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  95         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  96         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  97         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
  98 }, {
  99         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 100         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 101         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 102         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 103 }, {
 104         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 105         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 106         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 107         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 108 }, {
 109         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 110         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 111         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 112         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 113 } };
 114
 115 static const u32 golden_settings_tonga_a11[] =
 116 {
 117         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 118         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 119         mmFBC_MISC, 0x1f311fff, 0x12300000,
 120         mmHDMI_CONTROL, 0x31000111, 0x00000011,
 121 };
 122
 123 static const u32 tonga_mgcg_cgcg_init[] =
 124 {
 125         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 126         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 127 };
 128
 129 static const u32 golden_settings_fiji_a10[] =
 130 {
 131         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 132         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 133         mmFBC_MISC, 0x1f311fff, 0x12300000,
 134         mmHDMI_CONTROL, 0x31000111, 0x00000011,
 135 };
 136
 137 static const u32 fiji_mgcg_cgcg_init[] =
 138 {
 139         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 140         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 141 };
 142
 143 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
 144 {
 145         switch (adev->asic_type) {
 146         case CHIP_FIJI:
 147                 amdgpu_program_register_sequence(adev,
 148                                                  fiji_mgcg_cgcg_init,
 149                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 150                 amdgpu_program_register_sequence(adev,
 151                                                  golden_settings_fiji_a10,
 152                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 153                 break;
 154         case CHIP_TONGA:
 155                 amdgpu_program_register_sequence(adev,
 156                                                  tonga_mgcg_cgcg_init,
 157                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 158                 amdgpu_program_register_sequence(adev,
 159                                                  golden_settings_tonga_a11,
 160                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 161                 break;
 162         default:
 163                 break;
 164         }
 165 }
 166
 167 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
 168                                      u32 block_offset, u32 reg)
 169 {
 170         unsigned long flags;
 171         u32 r;
 172
 173         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 174         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 175         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 176         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 177
 178         return r;
 179 }
 180
 181 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
 182                                       u32 block_offset, u32 reg, u32 v)
 183 {
 184         unsigned long flags;
 185
 186         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 187         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 188         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 189         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 190 }
 191
 192 static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 193 {
 194         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 195                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 196                 return true;
 197         else
 198                 return false;
 199 }
 200
 201 static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 202 {
 203         u32 pos1, pos2;
 204
 205         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 206         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 207
 208         if (pos1 != pos2)
 209                 return true;
 210         else
 211                 return false;
 212 }
 213
 214 /**
 215  * dce_v10_0_vblank_wait - vblank wait asic callback.
 216  *
 217  * @adev: amdgpu_device pointer
 218  * @crtc: crtc to wait for vblank on
 219  *
 220  * Wait for vblank on the requested crtc (evergreen+).
 221  */
 222 static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 223 {
 224         unsigned i = 0;
 225
 226         if (crtc >= adev->mode_info.num_crtc)
 227                 return;
 228
 229         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 230                 return;
 231
 232         /* depending on when we hit vblank, we may be close to active; if so,
 233          * wait for another frame.
 234          */
 235         while (dce_v10_0_is_in_vblank(adev, crtc)) {
 236                 if (i++ % 100 == 0) {
 237                         if (!dce_v10_0_is_counter_moving(adev, crtc))
 238                                 break;
 239                 }
 240         }
 241
 242         while (!dce_v10_0_is_in_vblank(adev, crtc)) {
 243                 if (i++ % 100 == 0) {
 244                         if (!dce_v10_0_is_counter_moving(adev, crtc))
 245                                 break;
 246                 }
 247         }
 248 }
 249
 250 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 251 {
 252         if (crtc >= adev->mode_info.num_crtc)
 253                 return 0;
 254         else
 255                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 256 }
 257
 258 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 259 {
 260         unsigned i;
 261
 262         /* Enable pflip interrupts */
 263         for (i = 0; i < adev->mode_info.num_crtc; i++)
 264                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 265 }
 266
 267 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 268 {
 269         unsigned i;
 270
 271         /* Disable pflip interrupts */
 272         for (i = 0; i < adev->mode_info.num_crtc; i++)
 273                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 274 }
 275
 276 /**
 277  * dce_v10_0_page_flip - pageflip callback.
 278  *
 279  * @adev: amdgpu_device pointer
 280  * @crtc_id: crtc to cleanup pageflip on
 281  * @crtc_base: new address of the crtc (GPU MC address)
 282  *
 283  * Triggers the actual pageflip by updating the primary
 284  * surface base address.
 285  */
 286 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
 287                                 int crtc_id, u64 crtc_base, bool async)
 288 {
 289         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 290         u32 tmp;
 291
 292         /* flip at hsync for async, default is vsync */
 293         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
 294         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
 295                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
 296         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 297         /* update the primary scanout address */
 298         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 299                upper_32_bits(crtc_base));
 300         /* writing to the low address triggers the update */
 301         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 302                lower_32_bits(crtc_base));
 303         /* post the write */
 304         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 305 }
 306
 307 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 308                                         u32 *vbl, u32 *position)
 309 {
 310         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 311                 return -EINVAL;
 312
 313         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 314         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 315
 316         return 0;
 317 }
 318
 319 /**
 320  * dce_v10_0_hpd_sense - hpd sense callback.
 321  *
 322  * @adev: amdgpu_device pointer
 323  * @hpd: hpd (hotplug detect) pin
 324  *
 325  * Checks if a digital monitor is connected (evergreen+).
 326  * Returns true if connected, false if not connected.
 327  */
 328 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
 329                                enum amdgpu_hpd_id hpd)
 330 {
 331         int idx;
 332         bool connected = false;
 333
 334         switch (hpd) {
 335         case AMDGPU_HPD_1:
 336                 idx = 0;
 337                 break;
 338         case AMDGPU_HPD_2:
 339                 idx = 1;
 340                 break;
 341         case AMDGPU_HPD_3:
 342                 idx = 2;
 343                 break;
 344         case AMDGPU_HPD_4:
 345                 idx = 3;
 346                 break;
 347         case AMDGPU_HPD_5:
 348                 idx = 4;
 349                 break;
 350         case AMDGPU_HPD_6:
 351                 idx = 5;
 352                 break;
 353         default:
 354                 return connected;
 355         }
 356
 357         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
 358             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 359                 connected = true;
 360
 361         return connected;
 362 }
 363
 364 /**
 365  * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
 366  *
 367  * @adev: amdgpu_device pointer
 368  * @hpd: hpd (hotplug detect) pin
 369  *
 370  * Set the polarity of the hpd pin (evergreen+).
 371  */
 372 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
 373                                       enum amdgpu_hpd_id hpd)
 374 {
 375         u32 tmp;
 376         bool connected = dce_v10_0_hpd_sense(adev, hpd);
 377         int idx;
 378
 379         switch (hpd) {
 380         case AMDGPU_HPD_1:
 381                 idx = 0;
 382                 break;
 383         case AMDGPU_HPD_2:
 384                 idx = 1;
 385                 break;
 386         case AMDGPU_HPD_3:
 387                 idx = 2;
 388                 break;
 389         case AMDGPU_HPD_4:
 390                 idx = 3;
 391                 break;
 392         case AMDGPU_HPD_5:
 393                 idx = 4;
 394                 break;
 395         case AMDGPU_HPD_6:
 396                 idx = 5;
 397                 break;
 398         default:
 399                 return;
 400         }
 401
 402         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
 403         if (connected)
 404                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 405         else
 406                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 407         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
 408 }
 409
 410 /**
 411  * dce_v10_0_hpd_init - hpd setup callback.
 412  *
 413  * @adev: amdgpu_device pointer
 414  *
 415  * Setup the hpd pins used by the card (evergreen+).
 416  * Enable the pin, set the polarity, and enable the hpd interrupts.
 417  */
 418 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
 419 {
 420         struct drm_device *dev = adev->ddev;
 421         struct drm_connector *connector;
 422         u32 tmp;
 423         int idx;
 424
 425         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 426                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 427
 428                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 429                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 430                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 431                          * aux dp channel on imac and help (but not completely fix)
 432                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 433                          * also avoid interrupt storms during dpms.
 434                          */
 435                         continue;
 436                 }
 437
 438                 switch (amdgpu_connector->hpd.hpd) {
 439                 case AMDGPU_HPD_1:
 440                         idx = 0;
 441                         break;
 442                 case AMDGPU_HPD_2:
 443                         idx = 1;
 444                         break;
 445                 case AMDGPU_HPD_3:
 446                         idx = 2;
 447                         break;
 448                 case AMDGPU_HPD_4:
 449                         idx = 3;
 450                         break;
 451                 case AMDGPU_HPD_5:
 452                         idx = 4;
 453                         break;
 454                 case AMDGPU_HPD_6:
 455                         idx = 5;
 456                         break;
 457                 default:
 458                         continue;
 459                 }
 460
 461                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 462                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 463                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 464
 465                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
 466                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 467                                     DC_HPD_CONNECT_INT_DELAY,
 468                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 469                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 470                                     DC_HPD_DISCONNECT_INT_DELAY,
 471                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 472                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
 473
 474                 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 475                 amdgpu_irq_get(adev, &adev->hpd_irq,
 476                                amdgpu_connector->hpd.hpd);
 477         }
 478 }
 479
 480 /**
 481  * dce_v10_0_hpd_fini - hpd tear down callback.
 482  *
 483  * @adev: amdgpu_device pointer
 484  *
 485  * Tear down the hpd pins used by the card (evergreen+).
 486  * Disable the hpd interrupts.
 487  */
 488 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
 489 {
 490         struct drm_device *dev = adev->ddev;
 491         struct drm_connector *connector;
 492         u32 tmp;
 493         int idx;
 494
 495         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 496                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 497
 498                 switch (amdgpu_connector->hpd.hpd) {
 499                 case AMDGPU_HPD_1:
 500                         idx = 0;
 501                         break;
 502                 case AMDGPU_HPD_2:
 503                         idx = 1;
 504                         break;
 505                 case AMDGPU_HPD_3:
 506                         idx = 2;
 507                         break;
 508                 case AMDGPU_HPD_4:
 509                         idx = 3;
 510                         break;
 511                 case AMDGPU_HPD_5:
 512                         idx = 4;
 513                         break;
 514                 case AMDGPU_HPD_6:
 515                         idx = 5;
 516                         break;
 517                 default:
 518                         continue;
 519                 }
 520
 521                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 522                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 523                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 524
 525                 amdgpu_irq_put(adev, &adev->hpd_irq,
 526                                amdgpu_connector->hpd.hpd);
 527         }
 528 }
 529
 530 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 531 {
 532         return mmDC_GPIO_HPD_A;
 533 }
 534
 535 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
 536 {
 537         u32 crtc_hung = 0;
 538         u32 crtc_status[6];
 539         u32 i, j, tmp;
 540
 541         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 542                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 543                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 544                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 545                         crtc_hung |= (1 << i);
 546                 }
 547         }
 548
 549         for (j = 0; j < 10; j++) {
 550                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 551                         if (crtc_hung & (1 << i)) {
 552                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 553                                 if (tmp != crtc_status[i])
 554                                         crtc_hung &= ~(1 << i);
 555                         }
 556                 }
 557                 if (crtc_hung == 0)
 558                         return false;
 559                 udelay(100);
 560         }
 561
 562         return true;
 563 }
 564
 565 static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
 566                                      struct amdgpu_mode_mc_save *save)
 567 {
 568         u32 crtc_enabled, tmp;
 569         int i;
 570
 571         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 572         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 573
 574         /* disable VGA render */
 575         tmp = RREG32(mmVGA_RENDER_CONTROL);
 576         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 577         WREG32(mmVGA_RENDER_CONTROL, tmp);
 578
 579         /* blank the display controllers */
 580         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 581                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 582                                              CRTC_CONTROL, CRTC_MASTER_EN);
 583                 if (crtc_enabled) {
 584 #if 0
 585                         u32 frame_count;
 586                         int j;
 587
 588                         save->crtc_enabled[i] = true;
 589                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 590                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
 591                                 amdgpu_display_vblank_wait(adev, i);
 592                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 593                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
 594                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 595                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 596                         }
 597                         /* wait for the next frame */
 598                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 599                         for (j = 0; j < adev->usec_timeout; j++) {
 600                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 601                                         break;
 602                                 udelay(1);
 603                         }
 604                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 605                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
 606                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
 607                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 608                         }
 609                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
 610                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
 611                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
 612                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 613                         }
 614 #else
 615                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 616                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 617                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 618                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 619                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 620                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 621                         save->crtc_enabled[i] = false;
 622                         /* ***** */
 623 #endif
 624                 } else {
 625                         save->crtc_enabled[i] = false;
 626                 }
 627         }
 628 }
 629
 630 static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
 631                                        struct amdgpu_mode_mc_save *save)
 632 {
 633         u32 tmp, frame_count;
 634         int i, j;
 635
 636         /* update crtc base addresses */
 637         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 638                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 639                        upper_32_bits(adev->mc.vram_start));
 640                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 641                        upper_32_bits(adev->mc.vram_start));
 642                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 643                        (u32)adev->mc.vram_start);
 644                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 645                        (u32)adev->mc.vram_start);
 646
 647                 if (save->crtc_enabled[i]) {
 648                         tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
 649                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
 650                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
 651                                 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
 652                         }
 653                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 654                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
 655                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
 656                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 657                         }
 658                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
 659                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
 660                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
 661                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 662                         }
 663                         for (j = 0; j < adev->usec_timeout; j++) {
 664                                 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 665                                 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
 666                                         break;
 667                                 udelay(1);
 668                         }
 669                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 670                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
 671                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 672                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 673                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 674                         /* wait for the next frame */
 675                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 676                         for (j = 0; j < adev->usec_timeout; j++) {
 677                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 678                                         break;
 679                                 udelay(1);
 680                         }
 681                 }
 682         }
 683
 684         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 685         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
 686
 687         /* Unlock vga access */
 688         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 689         mdelay(1);
 690         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 691 }
 692
 693 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
 694                                            bool render)
 695 {
 696         u32 tmp;
 697
 698         /* Lockout access through VGA aperture*/
 699         tmp = RREG32(mmVGA_HDP_CONTROL);
 700         if (render)
 701                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 702         else
 703                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 704         WREG32(mmVGA_HDP_CONTROL, tmp);
 705
 706         /* disable VGA render */
 707         tmp = RREG32(mmVGA_RENDER_CONTROL);
 708         if (render)
 709                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 710         else
 711                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 712         WREG32(mmVGA_RENDER_CONTROL, tmp);
 713 }
 714
 715 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
 716 {
 717         struct drm_device *dev = encoder->dev;
 718         struct amdgpu_device *adev = dev->dev_private;
 719         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 720         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 721         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 722         int bpc = 0;
 723         u32 tmp = 0;
 724         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 725
 726         if (connector) {
 727                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 728                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 729                 dither = amdgpu_connector->dither;
 730         }
 731
 732         /* LVDS/eDP FMT is set up by atom */
 733         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 734                 return;
 735
 736         /* not needed for analog */
 737         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 738             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 739                 return;
 740
 741         if (bpc == 0)
 742                 return;
 743
 744         switch (bpc) {
 745         case 6:
 746                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 747                         /* XXX sort out optimal dither settings */
 748                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 749                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 750                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 751                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 752                 } else {
 753                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 754                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 755                 }
 756                 break;
 757         case 8:
 758                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 759                         /* XXX sort out optimal dither settings */
 760                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 761                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 762                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 763                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 764                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 765                 } else {
 766                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 767                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 768                 }
 769                 break;
 770         case 10:
 771                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 772                         /* XXX sort out optimal dither settings */
 773                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 774                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 775                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 776                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 777                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 778                 } else {
 779                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 780                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 781                 }
 782                 break;
 783         default:
 784                 /* not needed */
 785                 break;
 786         }
 787
 788         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 789 }
 790
 791
 792 /* display watermark setup */
 793 /**
 794  * dce_v10_0_line_buffer_adjust - Set up the line buffer
 795  *
 796  * @adev: amdgpu_device pointer
 797  * @amdgpu_crtc: the selected display controller
 798  * @mode: the current display mode on the selected display
 799  * controller
 800  *
 801  * Setup up the line buffer allocation for
 802  * the selected display controller (CIK).
 803  * Returns the line buffer size in pixels.
 804  */
 805 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
 806                                        struct amdgpu_crtc *amdgpu_crtc,
 807                                        struct drm_display_mode *mode)
 808 {
 809         u32 tmp, buffer_alloc, i, mem_cfg;
 810         u32 pipe_offset = amdgpu_crtc->crtc_id;
 811         /*
 812          * Line Buffer Setup
 813          * There are 6 line buffers, one for each display controllers.
 814          * There are 3 partitions per LB. Select the number of partitions
 815          * to enable based on the display width.  For display widths larger
 816          * than 4096, you need use to use 2 display controllers and combine
 817          * them using the stereo blender.
 818          */
 819         if (amdgpu_crtc->base.enabled && mode) {
 820                 if (mode->crtc_hdisplay < 1920) {
 821                         mem_cfg = 1;
 822                         buffer_alloc = 2;
 823                 } else if (mode->crtc_hdisplay < 2560) {
 824                         mem_cfg = 2;
 825                         buffer_alloc = 2;
 826                 } else if (mode->crtc_hdisplay < 4096) {
 827                         mem_cfg = 0;
 828                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 829                 } else {
 830                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 831                         mem_cfg = 0;
 832                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 833                 }
 834         } else {
 835                 mem_cfg = 1;
 836                 buffer_alloc = 0;
 837         }
 838
 839         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 840         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 841         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 842
 843         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 844         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 845         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 846
 847         for (i = 0; i < adev->usec_timeout; i++) {
 848                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 849                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 850                         break;
 851                 udelay(1);
 852         }
 853
 854         if (amdgpu_crtc->base.enabled && mode) {
 855                 switch (mem_cfg) {
 856                 case 0:
 857                 default:
 858                         return 4096 * 2;
 859                 case 1:
 860                         return 1920 * 2;
 861                 case 2:
 862                         return 2560 * 2;
 863                 }
 864         }
 865
 866         /* controller not enabled, so no lb used */
 867         return 0;
 868 }
 869
 870 /**
 871  * cik_get_number_of_dram_channels - get the number of dram channels
 872  *
 873  * @adev: amdgpu_device pointer
 874  *
 875  * Look up the number of video ram channels (CIK).
 876  * Used for display watermark bandwidth calculations
 877  * Returns the number of dram channels
 878  */
 879 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 880 {
 881         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 882
 883         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 884         case 0:
 885         default:
 886                 return 1;
 887         case 1:
 888                 return 2;
 889         case 2:
 890                 return 4;
 891         case 3:
 892                 return 8;
 893         case 4:
 894                 return 3;
 895         case 5:
 896                 return 6;
 897         case 6:
 898                 return 10;
 899         case 7:
 900                 return 12;
 901         case 8:
 902                 return 16;
 903         }
 904 }
 905
 906 struct dce10_wm_params {
 907         u32 dram_channels; /* number of dram channels */
 908         u32 yclk;          /* bandwidth per dram data pin in kHz */
 909         u32 sclk;          /* engine clock in kHz */
 910         u32 disp_clk;      /* display clock in kHz */
 911         u32 src_width;     /* viewport width */
 912         u32 active_time;   /* active display time in ns */
 913         u32 blank_time;    /* blank time in ns */
 914         bool interlaced;    /* mode is interlaced */
 915         fixed20_12 vsc;    /* vertical scale ratio */
 916         u32 num_heads;     /* number of active crtcs */
 917         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 918         u32 lb_size;       /* line buffer allocated to pipe */
 919         u32 vtaps;         /* vertical scaler taps */
 920 };
 921
 922 /**
 923  * dce_v10_0_dram_bandwidth - get the dram bandwidth
 924  *
 925  * @wm: watermark calculation data
 926  *
 927  * Calculate the raw dram bandwidth (CIK).
 928  * Used for display watermark bandwidth calculations
 929  * Returns the dram bandwidth in MBytes/s
 930  */
 931 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
 932 {
 933         /* Calculate raw DRAM Bandwidth */
 934         fixed20_12 dram_efficiency; /* 0.7 */
 935         fixed20_12 yclk, dram_channels, bandwidth;
 936         fixed20_12 a;
 937
 938         a.full = dfixed_const(1000);
 939         yclk.full = dfixed_const(wm->yclk);
 940         yclk.full = dfixed_div(yclk, a);
 941         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 942         a.full = dfixed_const(10);
 943         dram_efficiency.full = dfixed_const(7);
 944         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 945         bandwidth.full = dfixed_mul(dram_channels, yclk);
 946         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 947
 948         return dfixed_trunc(bandwidth);
 949 }
 950
 951 /**
 952  * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
 953  *
 954  * @wm: watermark calculation data
 955  *
 956  * Calculate the dram bandwidth used for display (CIK).
 957  * Used for display watermark bandwidth calculations
 958  * Returns the dram bandwidth for display in MBytes/s
 959  */
 960 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 961 {
 962         /* Calculate DRAM Bandwidth and the part allocated to display. */
 963         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 964         fixed20_12 yclk, dram_channels, bandwidth;
 965         fixed20_12 a;
 966
 967         a.full = dfixed_const(1000);
 968         yclk.full = dfixed_const(wm->yclk);
 969         yclk.full = dfixed_div(yclk, a);
 970         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 971         a.full = dfixed_const(10);
 972         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 973         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 974         bandwidth.full = dfixed_mul(dram_channels, yclk);
 975         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 976
 977         return dfixed_trunc(bandwidth);
 978 }
 979
 980 /**
 981  * dce_v10_0_data_return_bandwidth - get the data return bandwidth
 982  *
 983  * @wm: watermark calculation data
 984  *
 985  * Calculate the data return bandwidth used for display (CIK).
 986  * Used for display watermark bandwidth calculations
 987  * Returns the data return bandwidth in MBytes/s
 988  */
 989 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
 990 {
 991         /* Calculate the display Data return Bandwidth */
 992         fixed20_12 return_efficiency; /* 0.8 */
 993         fixed20_12 sclk, bandwidth;
 994         fixed20_12 a;
 995
 996         a.full = dfixed_const(1000);
 997         sclk.full = dfixed_const(wm->sclk);
 998         sclk.full = dfixed_div(sclk, a);
 999         a.full = dfixed_const(10);
1000         return_efficiency.full = dfixed_const(8);
1001         return_efficiency.full = dfixed_div(return_efficiency, a);
1002         a.full = dfixed_const(32);
1003         bandwidth.full = dfixed_mul(a, sclk);
1004         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
1005
1006         return dfixed_trunc(bandwidth);
1007 }
1008
1009 /**
1010  * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
1011  *
1012  * @wm: watermark calculation data
1013  *
1014  * Calculate the dmif bandwidth used for display (CIK).
1015  * Used for display watermark bandwidth calculations
1016  * Returns the dmif bandwidth in MBytes/s
1017  */
1018 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
1019 {
1020         /* Calculate the DMIF Request Bandwidth */
1021         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1022         fixed20_12 disp_clk, bandwidth;
1023         fixed20_12 a, b;
1024
1025         a.full = dfixed_const(1000);
1026         disp_clk.full = dfixed_const(wm->disp_clk);
1027         disp_clk.full = dfixed_div(disp_clk, a);
1028         a.full = dfixed_const(32);
1029         b.full = dfixed_mul(a, disp_clk);
1030
1031         a.full = dfixed_const(10);
1032         disp_clk_request_efficiency.full = dfixed_const(8);
1033         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1034
1035         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1036
1037         return dfixed_trunc(bandwidth);
1038 }
1039
1040 /**
1041  * dce_v10_0_available_bandwidth - get the min available bandwidth
1042  *
1043  * @wm: watermark calculation data
1044  *
1045  * Calculate the min available bandwidth used for display (CIK).
1046  * Used for display watermark bandwidth calculations
1047  * Returns the min available bandwidth in MBytes/s
1048  */
1049 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
1050 {
1051         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1052         u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
1053         u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
1054         u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
1055
1056         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1057 }
1058
1059 /**
1060  * dce_v10_0_average_bandwidth - get the average available bandwidth
1061  *
1062  * @wm: watermark calculation data
1063  *
1064  * Calculate the average available bandwidth used for display (CIK).
1065  * Used for display watermark bandwidth calculations
1066  * Returns the average available bandwidth in MBytes/s
1067  */
1068 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
1069 {
1070         /* Calculate the display mode Average Bandwidth
1071          * DisplayMode should contain the source and destination dimensions,
1072          * timing, etc.
1073          */
1074         fixed20_12 bpp;
1075         fixed20_12 line_time;
1076         fixed20_12 src_width;
1077         fixed20_12 bandwidth;
1078         fixed20_12 a;
1079
1080         a.full = dfixed_const(1000);
1081         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1082         line_time.full = dfixed_div(line_time, a);
1083         bpp.full = dfixed_const(wm->bytes_per_pixel);
1084         src_width.full = dfixed_const(wm->src_width);
1085         bandwidth.full = dfixed_mul(src_width, bpp);
1086         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1087         bandwidth.full = dfixed_div(bandwidth, line_time);
1088
1089         return dfixed_trunc(bandwidth);
1090 }
1091
1092 /**
1093  * dce_v10_0_latency_watermark - get the latency watermark
1094  *
1095  * @wm: watermark calculation data
1096  *
1097  * Calculate the latency watermark (CIK).
1098  * Used for display watermark bandwidth calculations
1099  * Returns the latency watermark in ns
1100  */
1101 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
1102 {
1103         /* First calculate the latency in ns */
1104         u32 mc_latency = 2000; /* 2000 ns. */
1105         u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
1106         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1107         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1108         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1109         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1110                 (wm->num_heads * cursor_line_pair_return_time);
1111         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1112         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1113         u32 tmp, dmif_size = 12288;
1114         fixed20_12 a, b, c;
1115
1116         if (wm->num_heads == 0)
1117                 return 0;
1118
1119         a.full = dfixed_const(2);
1120         b.full = dfixed_const(1);
1121         if ((wm->vsc.full > a.full) ||
1122             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1123             (wm->vtaps >= 5) ||
1124             ((wm->vsc.full >= a.full) && wm->interlaced))
1125                 max_src_lines_per_dst_line = 4;
1126         else
1127                 max_src_lines_per_dst_line = 2;
1128
1129         a.full = dfixed_const(available_bandwidth);
1130         b.full = dfixed_const(wm->num_heads);
1131         a.full = dfixed_div(a, b);
1132
1133         b.full = dfixed_const(mc_latency + 512);
1134         c.full = dfixed_const(wm->disp_clk);
1135         b.full = dfixed_div(b, c);
1136
1137         c.full = dfixed_const(dmif_size);
1138         b.full = dfixed_div(c, b);
1139
1140         tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1141
1142         b.full = dfixed_const(1000);
1143         c.full = dfixed_const(wm->disp_clk);
1144         b.full = dfixed_div(c, b);
1145         c.full = dfixed_const(wm->bytes_per_pixel);
1146         b.full = dfixed_mul(b, c);
1147
1148         lb_fill_bw = min(tmp, dfixed_trunc(b));
1149
1150         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1151         b.full = dfixed_const(1000);
1152         c.full = dfixed_const(lb_fill_bw);
1153         b.full = dfixed_div(c, b);
1154         a.full = dfixed_div(a, b);
1155         line_fill_time = dfixed_trunc(a);
1156
1157         if (line_fill_time < wm->active_time)
1158                 return latency;
1159         else
1160                 return latency + (line_fill_time - wm->active_time);
1161
1162 }
1163
1164 /**
1165  * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1166  * average and available dram bandwidth
1167  *
1168  * @wm: watermark calculation data
1169  *
1170  * Check if the display average bandwidth fits in the display
1171  * dram bandwidth (CIK).
1172  * Used for display watermark bandwidth calculations
1173  * Returns true if the display fits, false if not.
1174  */
1175 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1176 {
1177         if (dce_v10_0_average_bandwidth(wm) <=
1178             (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1179                 return true;
1180         else
1181                 return false;
1182 }
1183
1184 /**
1185  * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
1186  * average and available bandwidth
1187  *
1188  * @wm: watermark calculation data
1189  *
1190  * Check if the display average bandwidth fits in the display
1191  * available bandwidth (CIK).
1192  * Used for display watermark bandwidth calculations
1193  * Returns true if the display fits, false if not.
1194  */
1195 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1196 {
1197         if (dce_v10_0_average_bandwidth(wm) <=
1198             (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
1199                 return true;
1200         else
1201                 return false;
1202 }
1203
1204 /**
1205  * dce_v10_0_check_latency_hiding - check latency hiding
1206  *
1207  * @wm: watermark calculation data
1208  *
1209  * Check latency hiding (CIK).
1210  * Used for display watermark bandwidth calculations
1211  * Returns true if the display fits, false if not.
1212  */
1213 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
1214 {
1215         u32 lb_partitions = wm->lb_size / wm->src_width;
1216         u32 line_time = wm->active_time + wm->blank_time;
1217         u32 latency_tolerant_lines;
1218         u32 latency_hiding;
1219         fixed20_12 a;
1220
1221         a.full = dfixed_const(1);
1222         if (wm->vsc.full > a.full)
1223                 latency_tolerant_lines = 1;
1224         else {
1225                 if (lb_partitions <= (wm->vtaps + 1))
1226                         latency_tolerant_lines = 1;
1227                 else
1228                         latency_tolerant_lines = 2;
1229         }
1230
1231         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1232
1233         if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1234                 return true;
1235         else
1236                 return false;
1237 }
1238
1239 /**
1240  * dce_v10_0_program_watermarks - program display watermarks
1241  *
1242  * @adev: amdgpu_device pointer
1243  * @amdgpu_crtc: the selected display controller
1244  * @lb_size: line buffer size
1245  * @num_heads: number of display controllers in use
1246  *
1247  * Calculate and program the display watermarks for the
1248  * selected display controller (CIK).
1249  */
1250 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1251                                         struct amdgpu_crtc *amdgpu_crtc,
1252                                         u32 lb_size, u32 num_heads)
1253 {
1254         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1255         struct dce10_wm_params wm_low, wm_high;
1256         u32 pixel_period;
1257         u32 line_time = 0;
1258         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1259         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1260
1261         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1262                 pixel_period = 1000000 / (u32)mode->clock;
1263                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1264
1265                 /* watermark for high clocks */
1266                 if (adev->pm.dpm_enabled) {
1267                         wm_high.yclk =
1268                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1269                         wm_high.sclk =
1270                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1271                 } else {
1272                         wm_high.yclk = adev->pm.current_mclk * 10;
1273                         wm_high.sclk = adev->pm.current_sclk * 10;
1274                 }
1275
1276                 wm_high.disp_clk = mode->clock;
1277                 wm_high.src_width = mode->crtc_hdisplay;
1278                 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1279                 wm_high.blank_time = line_time - wm_high.active_time;
1280                 wm_high.interlaced = false;
1281                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1282                         wm_high.interlaced = true;
1283                 wm_high.vsc = amdgpu_crtc->vsc;
1284                 wm_high.vtaps = 1;
1285                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1286                         wm_high.vtaps = 2;
1287                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1288                 wm_high.lb_size = lb_size;
1289                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1290                 wm_high.num_heads = num_heads;
1291
1292                 /* set for high clocks */
1293                 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1294
1295                 /* possibly force display priority to high */
1296                 /* should really do this at mode validation time... */
1297                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1298                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1299                     !dce_v10_0_check_latency_hiding(&wm_high) ||
1300                     (adev->mode_info.disp_priority == 2)) {
1301                         DRM_DEBUG_KMS("force priority to high\n");
1302                 }
1303
1304                 /* watermark for low clocks */
1305                 if (adev->pm.dpm_enabled) {
1306                         wm_low.yclk =
1307                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1308                         wm_low.sclk =
1309                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1310                 } else {
1311                         wm_low.yclk = adev->pm.current_mclk * 10;
1312                         wm_low.sclk = adev->pm.current_sclk * 10;
1313                 }
1314
1315                 wm_low.disp_clk = mode->clock;
1316                 wm_low.src_width = mode->crtc_hdisplay;
1317                 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1318                 wm_low.blank_time = line_time - wm_low.active_time;
1319                 wm_low.interlaced = false;
1320                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1321                         wm_low.interlaced = true;
1322                 wm_low.vsc = amdgpu_crtc->vsc;
1323                 wm_low.vtaps = 1;
1324                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1325                         wm_low.vtaps = 2;
1326                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1327                 wm_low.lb_size = lb_size;
1328                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1329                 wm_low.num_heads = num_heads;
1330
1331                 /* set for low clocks */
1332                 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1333
1334                 /* possibly force display priority to high */
1335                 /* should really do this at mode validation time... */
1336                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1337                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1338                     !dce_v10_0_check_latency_hiding(&wm_low) ||
1339                     (adev->mode_info.disp_priority == 2)) {
1340                         DRM_DEBUG_KMS("force priority to high\n");
1341                 }
1342                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1343         }
1344
1345         /* select wm A */
1346         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1347         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1348         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1349         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1350         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1351         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1352         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1353         /* select wm B */
1354         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1355         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1356         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1357         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1358         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1359         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1360         /* restore original selection */
1361         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1362
1363         /* save values for DPM */
1364         amdgpu_crtc->line_time = line_time;
1365         amdgpu_crtc->wm_high = latency_watermark_a;
1366         amdgpu_crtc->wm_low = latency_watermark_b;
1367         /* Save number of lines the linebuffer leads before the scanout */
1368         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1369 }
1370
1371 /**
1372  * dce_v10_0_bandwidth_update - program display watermarks
1373  *
1374  * @adev: amdgpu_device pointer
1375  *
1376  * Calculate and program the display watermarks and line
1377  * buffer allocation (CIK).
1378  */
1379 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1380 {
1381         struct drm_display_mode *mode = NULL;
1382         u32 num_heads = 0, lb_size;
1383         int i;
1384
1385         amdgpu_update_display_priority(adev);
1386
1387         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1388                 if (adev->mode_info.crtcs[i]->base.enabled)
1389                         num_heads++;
1390         }
1391         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1392                 mode = &adev->mode_info.crtcs[i]->base.mode;
1393                 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1394                 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1395                                             lb_size, num_heads);
1396         }
1397 }
1398
1399 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1400 {
1401         int i;
1402         u32 offset, tmp;
1403
1404         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1405                 offset = adev->mode_info.audio.pin[i].offset;
1406                 tmp = RREG32_AUDIO_ENDPT(offset,
1407                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1408                 if (((tmp &
1409                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1410                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1411                         adev->mode_info.audio.pin[i].connected = false;
1412                 else
1413                         adev->mode_info.audio.pin[i].connected = true;
1414         }
1415 }
1416
1417 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1418 {
1419         int i;
1420
1421         dce_v10_0_audio_get_connected_pins(adev);
1422
1423         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1424                 if (adev->mode_info.audio.pin[i].connected)
1425                         return &adev->mode_info.audio.pin[i];
1426         }
1427         DRM_ERROR("No connected audio pins found!\n");
1428         return NULL;
1429 }
1430
1431 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1432 {
1433         struct amdgpu_device *adev = encoder->dev->dev_private;
1434         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1435         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1436         u32 tmp;
1437
1438         if (!dig || !dig->afmt || !dig->afmt->pin)
1439                 return;
1440
1441         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1442         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1443         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1444 }
1445
1446 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1447                                                 struct drm_display_mode *mode)
1448 {
1449         struct amdgpu_device *adev = encoder->dev->dev_private;
1450         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1451         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1452         struct drm_connector *connector;
1453         struct amdgpu_connector *amdgpu_connector = NULL;
1454         u32 tmp;
1455         int interlace = 0;
1456
1457         if (!dig || !dig->afmt || !dig->afmt->pin)
1458                 return;
1459
1460         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1461                 if (connector->encoder == encoder) {
1462                         amdgpu_connector = to_amdgpu_connector(connector);
1463                         break;
1464                 }
1465         }
1466
1467         if (!amdgpu_connector) {
1468                 DRM_ERROR("Couldn't find encoder's connector\n");
1469                 return;
1470         }
1471
1472         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1473                 interlace = 1;
1474         if (connector->latency_present[interlace]) {
1475                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1476                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1477                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1478                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1479         } else {
1480                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1481                                     VIDEO_LIPSYNC, 0);
1482                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1483                                     AUDIO_LIPSYNC, 0);
1484         }
1485         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1486                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1487 }
1488
1489 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1490 {
1491         struct amdgpu_device *adev = encoder->dev->dev_private;
1492         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1493         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1494         struct drm_connector *connector;
1495         struct amdgpu_connector *amdgpu_connector = NULL;
1496         u32 tmp;
1497         u8 *sadb = NULL;
1498         int sad_count;
1499
1500         if (!dig || !dig->afmt || !dig->afmt->pin)
1501                 return;
1502
1503         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1504                 if (connector->encoder == encoder) {
1505                         amdgpu_connector = to_amdgpu_connector(connector);
1506                         break;
1507                 }
1508         }
1509
1510         if (!amdgpu_connector) {
1511                 DRM_ERROR("Couldn't find encoder's connector\n");
1512                 return;
1513         }
1514
1515         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1516         if (sad_count < 0) {
1517                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1518                 sad_count = 0;
1519         }
1520
1521         /* program the speaker allocation */
1522         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1523                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1524         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1525                             DP_CONNECTION, 0);
1526         /* set HDMI mode */
1527         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1528                             HDMI_CONNECTION, 1);
1529         if (sad_count)
1530                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1531                                     SPEAKER_ALLOCATION, sadb[0]);
1532         else
1533                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1534                                     SPEAKER_ALLOCATION, 5); /* stereo */
1535         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1536                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1537
1538         kfree(sadb);
1539 }
1540
1541 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1542 {
1543         struct amdgpu_device *adev = encoder->dev->dev_private;
1544         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1545         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1546         struct drm_connector *connector;
1547         struct amdgpu_connector *amdgpu_connector = NULL;
1548         struct cea_sad *sads;
1549         int i, sad_count;
1550
1551         static const u16 eld_reg_to_type[][2] = {
1552                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1553                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1554                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1555                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1556                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1557                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1558                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1559                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1560                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1561                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1562                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1563                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1564         };
1565
1566         if (!dig || !dig->afmt || !dig->afmt->pin)
1567                 return;
1568
1569         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1570                 if (connector->encoder == encoder) {
1571                         amdgpu_connector = to_amdgpu_connector(connector);
1572                         break;
1573                 }
1574         }
1575
1576         if (!amdgpu_connector) {
1577                 DRM_ERROR("Couldn't find encoder's connector\n");
1578                 return;
1579         }
1580
1581         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1582         if (sad_count <= 0) {
1583                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1584                 return;
1585         }
1586         BUG_ON(!sads);
1587
1588         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1589                 u32 tmp = 0;
1590                 u8 stereo_freqs = 0;
1591                 int max_channels = -1;
1592                 int j;
1593
1594                 for (j = 0; j < sad_count; j++) {
1595                         struct cea_sad *sad = &sads[j];
1596
1597                         if (sad->format == eld_reg_to_type[i][1]) {
1598                                 if (sad->channels > max_channels) {
1599                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1600                                                             MAX_CHANNELS, sad->channels);
1601                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1602                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1603                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1604                                                             SUPPORTED_FREQUENCIES, sad->freq);
1605                                         max_channels = sad->channels;
1606                                 }
1607
1608                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1609                                         stereo_freqs |= sad->freq;
1610                                 else
1611                                         break;
1612                         }
1613                 }
1614
1615                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1616                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1617                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1618         }
1619
1620         kfree(sads);
1621 }
1622
1623 static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1624                                   struct amdgpu_audio_pin *pin,
1625                                   bool enable)
1626 {
1627         if (!pin)
1628                 return;
1629
1630         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1631                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1632 }
1633
1634 static const u32 pin_offsets[] =
1635 {
1636         AUD0_REGISTER_OFFSET,
1637         AUD1_REGISTER_OFFSET,
1638         AUD2_REGISTER_OFFSET,
1639         AUD3_REGISTER_OFFSET,
1640         AUD4_REGISTER_OFFSET,
1641         AUD5_REGISTER_OFFSET,
1642         AUD6_REGISTER_OFFSET,
1643 };
1644
1645 static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1646 {
1647         int i;
1648
1649         if (!amdgpu_audio)
1650                 return 0;
1651
1652         adev->mode_info.audio.enabled = true;
1653
1654         adev->mode_info.audio.num_pins = 7;
1655
1656         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1657                 adev->mode_info.audio.pin[i].channels = -1;
1658                 adev->mode_info.audio.pin[i].rate = -1;
1659                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1660                 adev->mode_info.audio.pin[i].status_bits = 0;
1661                 adev->mode_info.audio.pin[i].category_code = 0;
1662                 adev->mode_info.audio.pin[i].connected = false;
1663                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1664                 adev->mode_info.audio.pin[i].id = i;
1665                 /* disable audio.  it will be set up later */
1666                 /* XXX remove once we switch to ip funcs */
1667                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1668         }
1669
1670         return 0;
1671 }
1672
1673 static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1674 {
1675         int i;
1676
1677         if (!amdgpu_audio)
1678                 return;
1679
1680         if (!adev->mode_info.audio.enabled)
1681                 return;
1682
1683         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1684                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1685
1686         adev->mode_info.audio.enabled = false;
1687 }
1688
1689 /*
1690  * update the N and CTS parameters for a given pixel clock rate
1691  */
1692 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1693 {
1694         struct drm_device *dev = encoder->dev;
1695         struct amdgpu_device *adev = dev->dev_private;
1696         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1697         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1698         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1699         u32 tmp;
1700
1701         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1702         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1703         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1704         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1705         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1706         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1707
1708         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1709         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1710         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1711         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1712         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1713         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1714
1715         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1716         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1717         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1718         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1719         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1720         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1721
1722 }
1723
1724 /*
1725  * build a HDMI Video Info Frame
1726  */
1727 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1728                                                void *buffer, size_t size)
1729 {
1730         struct drm_device *dev = encoder->dev;
1731         struct amdgpu_device *adev = dev->dev_private;
1732         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1733         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1734         uint8_t *frame = buffer + 3;
1735         uint8_t *header = buffer;
1736
1737         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1738                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1739         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1740                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1741         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1742                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1743         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1744                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1745 }
1746
1747 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1748 {
1749         struct drm_device *dev = encoder->dev;
1750         struct amdgpu_device *adev = dev->dev_private;
1751         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1752         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1753         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1754         u32 dto_phase = 24 * 1000;
1755         u32 dto_modulo = clock;
1756         u32 tmp;
1757
1758         if (!dig || !dig->afmt)
1759                 return;
1760
1761         /* XXX two dtos; generally use dto0 for hdmi */
1762         /* Express [24MHz / target pixel clock] as an exact rational
1763          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1764          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1765          */
1766         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1767         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1768                             amdgpu_crtc->crtc_id);
1769         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1770         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1771         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1772 }
1773
1774 /*
1775  * update the info frames with the data from the current display mode
1776  */
1777 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1778                                   struct drm_display_mode *mode)
1779 {
1780         struct drm_device *dev = encoder->dev;
1781         struct amdgpu_device *adev = dev->dev_private;
1782         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1783         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1784         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1785         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1786         struct hdmi_avi_infoframe frame;
1787         ssize_t err;
1788         u32 tmp;
1789         int bpc = 8;
1790
1791         if (!dig || !dig->afmt)
1792                 return;
1793
1794         /* Silent, r600_hdmi_enable will raise WARN for us */
1795         if (!dig->afmt->enabled)
1796                 return;
1797
1798         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1799         if (encoder->crtc) {
1800                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1801                 bpc = amdgpu_crtc->bpc;
1802         }
1803
1804         /* disable audio prior to setting up hw */
1805         dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1806         dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1807
1808         dce_v10_0_audio_set_dto(encoder, mode->clock);
1809
1810         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1811         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1812         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1813
1814         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1815
1816         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1817         switch (bpc) {
1818         case 0:
1819         case 6:
1820         case 8:
1821         case 16:
1822         default:
1823                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1824                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1825                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1826                           connector->name, bpc);
1827                 break;
1828         case 10:
1829                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1830                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1831                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1832                           connector->name);
1833                 break;
1834         case 12:
1835                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1836                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1837                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1838                           connector->name);
1839                 break;
1840         }
1841         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1842
1843         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1844         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1845         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1846         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1847         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1848
1849         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1850         /* enable audio info frames (frames won't be set until audio is enabled) */
1851         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1852         /* required for audio info values to be updated */
1853         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1854         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1855
1856         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1857         /* required for audio info values to be updated */
1858         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1859         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1860
1861         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1862         /* anything other than 0 */
1863         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1864         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1865
1866         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1867
1868         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1869         /* set the default audio delay */
1870         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1871         /* should be suffient for all audio modes and small enough for all hblanks */
1872         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1873         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1874
1875         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1876         /* allow 60958 channel status fields to be updated */
1877         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1878         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1879
1880         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1881         if (bpc > 8)
1882                 /* clear SW CTS value */
1883                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1884         else
1885                 /* select SW CTS value */
1886                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1887         /* allow hw to sent ACR packets when required */
1888         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1889         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1890
1891         dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1892
1893         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1894         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1895         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1896
1897         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1898         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1899         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1900
1901         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1902         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1903         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1904         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1905         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1906         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1907         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1908         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1909
1910         dce_v10_0_audio_write_speaker_allocation(encoder);
1911
1912         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1913                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1914
1915         dce_v10_0_afmt_audio_select_pin(encoder);
1916         dce_v10_0_audio_write_sad_regs(encoder);
1917         dce_v10_0_audio_write_latency_fields(encoder, mode);
1918
1919         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1920         if (err < 0) {
1921                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1922                 return;
1923         }
1924
1925         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1926         if (err < 0) {
1927                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1928                 return;
1929         }
1930
1931         dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1932
1933         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1934         /* enable AVI info frames */
1935         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1936         /* required for audio info values to be updated */
1937         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1938         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1939
1940         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1941         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1942         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1943
1944         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1945         /* send audio packets */
1946         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1947         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1948
1949         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1950         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1951         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1952         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1953
1954         /* enable audio after to setting up hw */
1955         dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1956 }
1957
1958 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1959 {
1960         struct drm_device *dev = encoder->dev;
1961         struct amdgpu_device *adev = dev->dev_private;
1962         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1963         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1964
1965         if (!dig || !dig->afmt)
1966                 return;
1967
1968         /* Silent, r600_hdmi_enable will raise WARN for us */
1969         if (enable && dig->afmt->enabled)
1970                 return;
1971         if (!enable && !dig->afmt->enabled)
1972                 return;
1973
1974         if (!enable && dig->afmt->pin) {
1975                 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1976                 dig->afmt->pin = NULL;
1977         }
1978
1979         dig->afmt->enabled = enable;
1980
1981         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1982                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1983 }
1984
1985 static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
1986 {
1987         int i;
1988
1989         for (i = 0; i < adev->mode_info.num_dig; i++)
1990                 adev->mode_info.afmt[i] = NULL;
1991
1992         /* DCE10 has audio blocks tied to DIG encoders */
1993         for (i = 0; i < adev->mode_info.num_dig; i++) {
1994                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1995                 if (adev->mode_info.afmt[i]) {
1996                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1997                         adev->mode_info.afmt[i]->id = i;
1998                 } else {
1999                         int j;
2000                         for (j = 0; j < i; j++) {
2001                                 kfree(adev->mode_info.afmt[j]);
2002                                 adev->mode_info.afmt[j] = NULL;
2003                         }
2004                         return -ENOMEM;
2005                 }
2006         }
2007         return 0;
2008 }
2009
2010 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
2011 {
2012         int i;
2013
2014         for (i = 0; i < adev->mode_info.num_dig; i++) {
2015                 kfree(adev->mode_info.afmt[i]);
2016                 adev->mode_info.afmt[i] = NULL;
2017         }
2018 }
2019
2020 static const u32 vga_control_regs[6] =
2021 {
2022         mmD1VGA_CONTROL,
2023         mmD2VGA_CONTROL,
2024         mmD3VGA_CONTROL,
2025         mmD4VGA_CONTROL,
2026         mmD5VGA_CONTROL,
2027         mmD6VGA_CONTROL,
2028 };
2029
2030 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
2031 {
2032         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2033         struct drm_device *dev = crtc->dev;
2034         struct amdgpu_device *adev = dev->dev_private;
2035         u32 vga_control;
2036
2037         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2038         if (enable)
2039                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2040         else
2041                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2042 }
2043
2044 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
2045 {
2046         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2047         struct drm_device *dev = crtc->dev;
2048         struct amdgpu_device *adev = dev->dev_private;
2049
2050         if (enable)
2051                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2052         else
2053                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2054 }
2055
2056 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
2057                                      struct drm_framebuffer *fb,
2058                                      int x, int y, int atomic)
2059 {
2060         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2061         struct drm_device *dev = crtc->dev;
2062         struct amdgpu_device *adev = dev->dev_private;
2063         struct amdgpu_framebuffer *amdgpu_fb;
2064         struct drm_framebuffer *target_fb;
2065         struct drm_gem_object *obj;
2066         struct amdgpu_bo *rbo;
2067         uint64_t fb_location, tiling_flags;
2068         uint32_t fb_format, fb_pitch_pixels;
2069         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2070         u32 pipe_config;
2071         u32 tmp, viewport_w, viewport_h;
2072         int r;
2073         bool bypass_lut = false;
2074
2075         /* no fb bound */
2076         if (!atomic && !crtc->primary->fb) {
2077                 DRM_DEBUG_KMS("No FB bound\n");
2078                 return 0;
2079         }
2080
2081         if (atomic) {
2082                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2083                 target_fb = fb;
2084         } else {
2085                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2086                 target_fb = crtc->primary->fb;
2087         }
2088
2089         /* If atomic, assume fb object is pinned & idle & fenced and
2090          * just update base pointers
2091          */
2092         obj = amdgpu_fb->obj;
2093         rbo = gem_to_amdgpu_bo(obj);
2094         r = amdgpu_bo_reserve(rbo, false);
2095         if (unlikely(r != 0))
2096                 return r;
2097
2098         if (atomic) {
2099                 fb_location = amdgpu_bo_gpu_offset(rbo);
2100         } else {
2101                 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2102                 if (unlikely(r != 0)) {
2103                         amdgpu_bo_unreserve(rbo);
2104                         return -EINVAL;
2105                 }
2106         }
2107
2108         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2109         amdgpu_bo_unreserve(rbo);
2110
2111         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2112
2113         switch (target_fb->pixel_format) {
2114         case DRM_FORMAT_C8:
2115                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2116                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2117                 break;
2118         case DRM_FORMAT_XRGB4444:
2119         case DRM_FORMAT_ARGB4444:
2120                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2121                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2122 #ifdef __BIG_ENDIAN
2123                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2124                                         ENDIAN_8IN16);
2125 #endif
2126                 break;
2127         case DRM_FORMAT_XRGB1555:
2128         case DRM_FORMAT_ARGB1555:
2129                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2130                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2131 #ifdef __BIG_ENDIAN
2132                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2133                                         ENDIAN_8IN16);
2134 #endif
2135                 break;
2136         case DRM_FORMAT_BGRX5551:
2137         case DRM_FORMAT_BGRA5551:
2138                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2139                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2140 #ifdef __BIG_ENDIAN
2141                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2142                                         ENDIAN_8IN16);
2143 #endif
2144                 break;
2145         case DRM_FORMAT_RGB565:
2146                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2147                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2148 #ifdef __BIG_ENDIAN
2149                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2150                                         ENDIAN_8IN16);
2151 #endif
2152                 break;
2153         case DRM_FORMAT_XRGB8888:
2154         case DRM_FORMAT_ARGB8888:
2155                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2156                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2157 #ifdef __BIG_ENDIAN
2158                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2159                                         ENDIAN_8IN32);
2160 #endif
2161                 break;
2162         case DRM_FORMAT_XRGB2101010:
2163         case DRM_FORMAT_ARGB2101010:
2164                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2165                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2166 #ifdef __BIG_ENDIAN
2167                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2168                                         ENDIAN_8IN32);
2169 #endif
2170                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2171                 bypass_lut = true;
2172                 break;
2173         case DRM_FORMAT_BGRX1010102:
2174         case DRM_FORMAT_BGRA1010102:
2175                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2176                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2177 #ifdef __BIG_ENDIAN
2178                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2179                                         ENDIAN_8IN32);
2180 #endif
2181                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2182                 bypass_lut = true;
2183                 break;
2184         default:
2185                 DRM_ERROR("Unsupported screen format %s\n",
2186                         drm_get_format_name(target_fb->pixel_format));
2187                 return -EINVAL;
2188         }
2189
2190         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2191                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2192
2193                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2194                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2195                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2196                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2197                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2198
2199                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2200                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2201                                           ARRAY_2D_TILED_THIN1);
2202                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2203                                           tile_split);
2204                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2205                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2206                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2207                                           mtaspect);
2208                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2209                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2210         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2211                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2212                                           ARRAY_1D_TILED_THIN1);
2213         }
2214
2215         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2216                                   pipe_config);
2217
2218         dce_v10_0_vga_enable(crtc, false);
2219
2220         /* Make sure surface address is updated at vertical blank rather than
2221          * horizontal blank
2222          */
2223         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2224         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2225                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2226         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2227
2228         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2229                upper_32_bits(fb_location));
2230         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2231                upper_32_bits(fb_location));
2232         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2233                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2234         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2235                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2236         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2237         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2238
2239         /*
2240          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2241          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2242          * retain the full precision throughout the pipeline.
2243          */
2244         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2245         if (bypass_lut)
2246                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2247         else
2248                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2249         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2250
2251         if (bypass_lut)
2252                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2253
2254         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2255         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2256         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2257         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2258         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2259         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2260
2261         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2262         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2263
2264         dce_v10_0_grph_enable(crtc, true);
2265
2266         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2267                target_fb->height);
2268
2269         x &= ~3;
2270         y &= ~1;
2271         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2272                (x << 16) | y);
2273         viewport_w = crtc->mode.hdisplay;
2274         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2275         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2276                (viewport_w << 16) | viewport_h);
2277
2278         /* set pageflip to happen only at start of vblank interval (front porch) */
2279         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2280
2281         if (!atomic && fb && fb != crtc->primary->fb) {
2282                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2283                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2284                 r = amdgpu_bo_reserve(rbo, false);
2285                 if (unlikely(r != 0))
2286                         return r;
2287                 amdgpu_bo_unpin(rbo);
2288                 amdgpu_bo_unreserve(rbo);
2289         }
2290
2291         /* Bytes per pixel may have changed */
2292         dce_v10_0_bandwidth_update(adev);
2293
2294         return 0;
2295 }
2296
2297 static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2298                                      struct drm_display_mode *mode)
2299 {
2300         struct drm_device *dev = crtc->dev;
2301         struct amdgpu_device *adev = dev->dev_private;
2302         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2303         u32 tmp;
2304
2305         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2306         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2307                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2308         else
2309                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2310         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2311 }
2312
2313 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2314 {
2315         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2316         struct drm_device *dev = crtc->dev;
2317         struct amdgpu_device *adev = dev->dev_private;
2318         int i;
2319         u32 tmp;
2320
2321         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2322
2323         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2324         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2325         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2326         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2327
2328         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2329         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2330         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2331
2332         tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2333         tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2334         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2335
2336         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2337         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2338         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2339         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2340
2341         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2342
2343         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2344         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2345         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2346
2347         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2348         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2349         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2350
2351         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2352         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2353
2354         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2355         for (i = 0; i < 256; i++) {
2356                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2357                        (amdgpu_crtc->lut_r[i] << 20) |
2358                        (amdgpu_crtc->lut_g[i] << 10) |
2359                        (amdgpu_crtc->lut_b[i] << 0));
2360         }
2361
2362         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2363         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2364         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2365         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2366         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2367
2368         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2369         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2370         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2371         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2372
2373         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2374         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2375         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2376         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2377
2378         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2379         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2380         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2381         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2382
2383         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2384         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2385         /* XXX this only needs to be programmed once per crtc at startup,
2386          * not sure where the best place for it is
2387          */
2388         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2389         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2390         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2391 }
2392
2393 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2394 {
2395         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2396         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2397
2398         switch (amdgpu_encoder->encoder_id) {
2399         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2400                 if (dig->linkb)
2401                         return 1;
2402                 else
2403                         return 0;
2404                 break;
2405         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2406                 if (dig->linkb)
2407                         return 3;
2408                 else
2409                         return 2;
2410                 break;
2411         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2412                 if (dig->linkb)
2413                         return 5;
2414                 else
2415                         return 4;
2416                 break;
2417         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2418                 return 6;
2419                 break;
2420         default:
2421                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2422                 return 0;
2423         }
2424 }
2425
2426 /**
2427  * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2428  *
2429  * @crtc: drm crtc
2430  *
2431  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2432  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2433  * monitors a dedicated PPLL must be used.  If a particular board has
2434  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2435  * as there is no need to program the PLL itself.  If we are not able to
2436  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2437  * avoid messing up an existing monitor.
2438  *
2439  * Asic specific PLL information
2440  *
2441  * DCE 10.x
2442  * Tonga
2443  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2444  * CI
2445  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2446  *
2447  */
2448 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2449 {
2450         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2451         struct drm_device *dev = crtc->dev;
2452         struct amdgpu_device *adev = dev->dev_private;
2453         u32 pll_in_use;
2454         int pll;
2455
2456         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2457                 if (adev->clock.dp_extclk)
2458                         /* skip PPLL programming if using ext clock */
2459                         return ATOM_PPLL_INVALID;
2460                 else {
2461                         /* use the same PPLL for all DP monitors */
2462                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2463                         if (pll != ATOM_PPLL_INVALID)
2464                                 return pll;
2465                 }
2466         } else {
2467                 /* use the same PPLL for all monitors with the same clock */
2468                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2469                 if (pll != ATOM_PPLL_INVALID)
2470                         return pll;
2471         }
2472
2473         /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2474         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2475         if (!(pll_in_use & (1 << ATOM_PPLL2)))
2476                 return ATOM_PPLL2;
2477         if (!(pll_in_use & (1 << ATOM_PPLL1)))
2478                 return ATOM_PPLL1;
2479         if (!(pll_in_use & (1 << ATOM_PPLL0)))
2480                 return ATOM_PPLL0;
2481         DRM_ERROR("unable to allocate a PPLL\n");
2482         return ATOM_PPLL_INVALID;
2483 }
2484
2485 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2486 {
2487         struct amdgpu_device *adev = crtc->dev->dev_private;
2488         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2489         uint32_t cur_lock;
2490
2491         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2492         if (lock)
2493                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2494         else
2495                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2496         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2497 }
2498
2499 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2500 {
2501         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2502         struct amdgpu_device *adev = crtc->dev->dev_private;
2503         u32 tmp;
2504
2505         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2506         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2507         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2508 }
2509
2510 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2511 {
2512         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2513         struct amdgpu_device *adev = crtc->dev->dev_private;
2514         u32 tmp;
2515
2516         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2517                upper_32_bits(amdgpu_crtc->cursor_addr));
2518         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2519                lower_32_bits(amdgpu_crtc->cursor_addr));
2520
2521         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2522         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2523         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2524         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2525 }
2526
2527 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2528                                         int x, int y)
2529 {
2530         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2531         struct amdgpu_device *adev = crtc->dev->dev_private;
2532         int xorigin = 0, yorigin = 0;
2533
2534         /* avivo cursor are offset into the total surface */
2535         x += crtc->x;
2536         y += crtc->y;
2537         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2538
2539         if (x < 0) {
2540                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2541                 x = 0;
2542         }
2543         if (y < 0) {
2544                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2545                 y = 0;
2546         }
2547
2548         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2549         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2550         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2551                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2552
2553         amdgpu_crtc->cursor_x = x;
2554         amdgpu_crtc->cursor_y = y;
2555
2556         return 0;
2557 }
2558
2559 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2560                                       int x, int y)
2561 {
2562         int ret;
2563
2564         dce_v10_0_lock_cursor(crtc, true);
2565         ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2566         dce_v10_0_lock_cursor(crtc, false);
2567
2568         return ret;
2569 }
2570
2571 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2572                                       struct drm_file *file_priv,
2573                                       uint32_t handle,
2574                                       uint32_t width,
2575                                       uint32_t height,
2576                                       int32_t hot_x,
2577                                       int32_t hot_y)
2578 {
2579         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2580         struct drm_gem_object *obj;
2581         struct amdgpu_bo *aobj;
2582         int ret;
2583
2584         if (!handle) {
2585                 /* turn off cursor */
2586                 dce_v10_0_hide_cursor(crtc);
2587                 obj = NULL;
2588                 goto unpin;
2589         }
2590
2591         if ((width > amdgpu_crtc->max_cursor_width) ||
2592             (height > amdgpu_crtc->max_cursor_height)) {
2593                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2594                 return -EINVAL;
2595         }
2596
2597         obj = drm_gem_object_lookup(file_priv, handle);
2598         if (!obj) {
2599                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2600                 return -ENOENT;
2601         }
2602
2603         aobj = gem_to_amdgpu_bo(obj);
2604         ret = amdgpu_bo_reserve(aobj, false);
2605         if (ret != 0) {
2606                 drm_gem_object_unreference_unlocked(obj);
2607                 return ret;
2608         }
2609
2610         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2611         amdgpu_bo_unreserve(aobj);
2612         if (ret) {
2613                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2614                 drm_gem_object_unreference_unlocked(obj);
2615                 return ret;
2616         }
2617
2618         amdgpu_crtc->cursor_width = width;
2619         amdgpu_crtc->cursor_height = height;
2620
2621         dce_v10_0_lock_cursor(crtc, true);
2622
2623         if (hot_x != amdgpu_crtc->cursor_hot_x ||
2624             hot_y != amdgpu_crtc->cursor_hot_y) {
2625                 int x, y;
2626
2627                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2628                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2629
2630                 dce_v10_0_cursor_move_locked(crtc, x, y);
2631
2632                 amdgpu_crtc->cursor_hot_x = hot_x;
2633                 amdgpu_crtc->cursor_hot_y = hot_y;
2634         }
2635
2636         dce_v10_0_show_cursor(crtc);
2637         dce_v10_0_lock_cursor(crtc, false);
2638
2639 unpin:
2640         if (amdgpu_crtc->cursor_bo) {
2641                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2642                 ret = amdgpu_bo_reserve(aobj, false);
2643                 if (likely(ret == 0)) {
2644                         amdgpu_bo_unpin(aobj);
2645                         amdgpu_bo_unreserve(aobj);
2646                 }
2647                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2648         }
2649
2650         amdgpu_crtc->cursor_bo = obj;
2651         return 0;
2652 }
2653
2654 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2655 {
2656         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2657
2658         if (amdgpu_crtc->cursor_bo) {
2659                 dce_v10_0_lock_cursor(crtc, true);
2660
2661                 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2662                                              amdgpu_crtc->cursor_y);
2663
2664                 dce_v10_0_show_cursor(crtc);
2665
2666                 dce_v10_0_lock_cursor(crtc, false);
2667         }
2668 }
2669
2670 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2671                                     u16 *blue, uint32_t size)
2672 {
2673         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2674         int i;
2675
2676         /* userspace palettes are always correct as is */
2677         for (i = 0; i < size; i++) {
2678                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2679                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2680                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2681         }
2682         dce_v10_0_crtc_load_lut(crtc);
2683
2684         return 0;
2685 }
2686
2687 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2688 {
2689         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2690
2691         drm_crtc_cleanup(crtc);
2692         kfree(amdgpu_crtc);
2693 }
2694
2695 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2696         .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2697         .cursor_move = dce_v10_0_crtc_cursor_move,
2698         .gamma_set = dce_v10_0_crtc_gamma_set,
2699         .set_config = amdgpu_crtc_set_config,
2700         .destroy = dce_v10_0_crtc_destroy,
2701         .page_flip = amdgpu_crtc_page_flip,
2702 };
2703
2704 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2705 {
2706         struct drm_device *dev = crtc->dev;
2707         struct amdgpu_device *adev = dev->dev_private;
2708         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2709         unsigned type;
2710
2711         switch (mode) {
2712         case DRM_MODE_DPMS_ON:
2713                 amdgpu_crtc->enabled = true;
2714                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2715                 dce_v10_0_vga_enable(crtc, true);
2716                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2717                 dce_v10_0_vga_enable(crtc, false);
2718                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2719                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2720                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2721                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2722                 drm_crtc_vblank_on(crtc);
2723                 dce_v10_0_crtc_load_lut(crtc);
2724                 break;
2725         case DRM_MODE_DPMS_STANDBY:
2726         case DRM_MODE_DPMS_SUSPEND:
2727         case DRM_MODE_DPMS_OFF:
2728                 drm_crtc_vblank_off(crtc);
2729                 if (amdgpu_crtc->enabled) {
2730                         dce_v10_0_vga_enable(crtc, true);
2731                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2732                         dce_v10_0_vga_enable(crtc, false);
2733                 }
2734                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2735                 amdgpu_crtc->enabled = false;
2736                 break;
2737         }
2738         /* adjust pm to dpms */
2739         amdgpu_pm_compute_clocks(adev);
2740 }
2741
2742 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2743 {
2744         /* disable crtc pair power gating before programming */
2745         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2746         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2747         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2748 }
2749
2750 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2751 {
2752         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2753         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2754 }
2755
2756 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2757 {
2758         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2759         struct drm_device *dev = crtc->dev;
2760         struct amdgpu_device *adev = dev->dev_private;
2761         struct amdgpu_atom_ss ss;
2762         int i;
2763
2764         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2765         if (crtc->primary->fb) {
2766                 int r;
2767                 struct amdgpu_framebuffer *amdgpu_fb;
2768                 struct amdgpu_bo *rbo;
2769
2770                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2771                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2772                 r = amdgpu_bo_reserve(rbo, false);
2773                 if (unlikely(r))
2774                         DRM_ERROR("failed to reserve rbo before unpin\n");
2775                 else {
2776                         amdgpu_bo_unpin(rbo);
2777                         amdgpu_bo_unreserve(rbo);
2778                 }
2779         }
2780         /* disable the GRPH */
2781         dce_v10_0_grph_enable(crtc, false);
2782
2783         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2784
2785         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2786                 if (adev->mode_info.crtcs[i] &&
2787                     adev->mode_info.crtcs[i]->enabled &&
2788                     i != amdgpu_crtc->crtc_id &&
2789                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2790                         /* one other crtc is using this pll don't turn
2791                          * off the pll
2792                          */
2793                         goto done;
2794                 }
2795         }
2796
2797         switch (amdgpu_crtc->pll_id) {
2798         case ATOM_PPLL0:
2799         case ATOM_PPLL1:
2800         case ATOM_PPLL2:
2801                 /* disable the ppll */
2802                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2803                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2804                 break;
2805         default:
2806                 break;
2807         }
2808 done:
2809         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2810         amdgpu_crtc->adjusted_clock = 0;
2811         amdgpu_crtc->encoder = NULL;
2812         amdgpu_crtc->connector = NULL;
2813 }
2814
2815 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2816                                   struct drm_display_mode *mode,
2817                                   struct drm_display_mode *adjusted_mode,
2818                                   int x, int y, struct drm_framebuffer *old_fb)
2819 {
2820         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2821
2822         if (!amdgpu_crtc->adjusted_clock)
2823                 return -EINVAL;
2824
2825         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2826         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2827         dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2828         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2829         amdgpu_atombios_crtc_scaler_setup(crtc);
2830         dce_v10_0_cursor_reset(crtc);
2831         /* update the hw version fpr dpm */
2832         amdgpu_crtc->hw_mode = *adjusted_mode;
2833
2834         return 0;
2835 }
2836
2837 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2838                                      const struct drm_display_mode *mode,
2839                                      struct drm_display_mode *adjusted_mode)
2840 {
2841         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2842         struct drm_device *dev = crtc->dev;
2843         struct drm_encoder *encoder;
2844
2845         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2846         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2847                 if (encoder->crtc == crtc) {
2848                         amdgpu_crtc->encoder = encoder;
2849                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2850                         break;
2851                 }
2852         }
2853         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2854                 amdgpu_crtc->encoder = NULL;
2855                 amdgpu_crtc->connector = NULL;
2856                 return false;
2857         }
2858         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2859                 return false;
2860         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2861                 return false;
2862         /* pick pll */
2863         amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2864         /* if we can't get a PPLL for a non-DP encoder, fail */
2865         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2866             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2867                 return false;
2868
2869         return true;
2870 }
2871
2872 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2873                                   struct drm_framebuffer *old_fb)
2874 {
2875         return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2876 }
2877
2878 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2879                                          struct drm_framebuffer *fb,
2880                                          int x, int y, enum mode_set_atomic state)
2881 {
2882        return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2883 }
2884
2885 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2886         .dpms = dce_v10_0_crtc_dpms,
2887         .mode_fixup = dce_v10_0_crtc_mode_fixup,
2888         .mode_set = dce_v10_0_crtc_mode_set,
2889         .mode_set_base = dce_v10_0_crtc_set_base,
2890         .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2891         .prepare = dce_v10_0_crtc_prepare,
2892         .commit = dce_v10_0_crtc_commit,
2893         .load_lut = dce_v10_0_crtc_load_lut,
2894         .disable = dce_v10_0_crtc_disable,
2895 };
2896
2897 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2898 {
2899         struct amdgpu_crtc *amdgpu_crtc;
2900         int i;
2901
2902         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2903                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2904         if (amdgpu_crtc == NULL)
2905                 return -ENOMEM;
2906
2907         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2908
2909         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2910         amdgpu_crtc->crtc_id = index;
2911         adev->mode_info.crtcs[index] = amdgpu_crtc;
2912
2913         amdgpu_crtc->max_cursor_width = 128;
2914         amdgpu_crtc->max_cursor_height = 128;
2915         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2916         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2917
2918         for (i = 0; i < 256; i++) {
2919                 amdgpu_crtc->lut_r[i] = i << 2;
2920                 amdgpu_crtc->lut_g[i] = i << 2;
2921                 amdgpu_crtc->lut_b[i] = i << 2;
2922         }
2923
2924         switch (amdgpu_crtc->crtc_id) {
2925         case 0:
2926         default:
2927                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2928                 break;
2929         case 1:
2930                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2931                 break;
2932         case 2:
2933                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2934                 break;
2935         case 3:
2936                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2937                 break;
2938         case 4:
2939                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2940                 break;
2941         case 5:
2942                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2943                 break;
2944         }
2945
2946         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2947         amdgpu_crtc->adjusted_clock = 0;
2948         amdgpu_crtc->encoder = NULL;
2949         amdgpu_crtc->connector = NULL;
2950         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2951
2952         return 0;
2953 }
2954
2955 static int dce_v10_0_early_init(void *handle)
2956 {
2957         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2958
2959         adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2960         adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2961
2962         dce_v10_0_set_display_funcs(adev);
2963         dce_v10_0_set_irq_funcs(adev);
2964
2965         switch (adev->asic_type) {
2966         case CHIP_FIJI:
2967         case CHIP_TONGA:
2968                 adev->mode_info.num_crtc = 6; /* XXX 7??? */
2969                 adev->mode_info.num_hpd = 6;
2970                 adev->mode_info.num_dig = 7;
2971                 break;
2972         default:
2973                 /* FIXME: not supported yet */
2974                 return -EINVAL;
2975         }
2976
2977         return 0;
2978 }
2979
2980 static int dce_v10_0_sw_init(void *handle)
2981 {
2982         int r, i;
2983         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2984
2985         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2986                 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2987                 if (r)
2988                         return r;
2989         }
2990
2991         for (i = 8; i < 20; i += 2) {
2992                 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2993                 if (r)
2994                         return r;
2995         }
2996
2997         /* HPD hotplug */
2998         r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2999         if (r)
3000                 return r;
3001
3002         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
3003
3004         adev->ddev->mode_config.async_page_flip = true;
3005
3006         adev->ddev->mode_config.max_width = 16384;
3007         adev->ddev->mode_config.max_height = 16384;
3008
3009         adev->ddev->mode_config.preferred_depth = 24;
3010         adev->ddev->mode_config.prefer_shadow = 1;
3011
3012         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
3013
3014         r = amdgpu_modeset_create_props(adev);
3015         if (r)
3016                 return r;
3017
3018         adev->ddev->mode_config.max_width = 16384;
3019         adev->ddev->mode_config.max_height = 16384;
3020
3021         /* allocate crtcs */
3022         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3023                 r = dce_v10_0_crtc_init(adev, i);
3024                 if (r)
3025                         return r;
3026         }
3027
3028         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3029                 amdgpu_print_display_setup(adev->ddev);
3030         else
3031                 return -EINVAL;
3032
3033         /* setup afmt */
3034         r = dce_v10_0_afmt_init(adev);
3035         if (r)
3036                 return r;
3037
3038         r = dce_v10_0_audio_init(adev);
3039         if (r)
3040                 return r;
3041
3042         drm_kms_helper_poll_init(adev->ddev);
3043
3044         adev->mode_info.mode_config_initialized = true;
3045         return 0;
3046 }
3047
3048 static int dce_v10_0_sw_fini(void *handle)
3049 {
3050         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3051
3052         kfree(adev->mode_info.bios_hardcoded_edid);
3053
3054         drm_kms_helper_poll_fini(adev->ddev);
3055
3056         dce_v10_0_audio_fini(adev);
3057
3058         dce_v10_0_afmt_fini(adev);
3059
3060         drm_mode_config_cleanup(adev->ddev);
3061         adev->mode_info.mode_config_initialized = false;
3062
3063         return 0;
3064 }
3065
3066 static int dce_v10_0_hw_init(void *handle)
3067 {
3068         int i;
3069         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3070
3071         dce_v10_0_init_golden_registers(adev);
3072
3073         /* init dig PHYs, disp eng pll */
3074         amdgpu_atombios_encoder_init_dig(adev);
3075         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3076
3077         /* initialize hpd */
3078         dce_v10_0_hpd_init(adev);
3079
3080         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3081                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3082         }
3083
3084         dce_v10_0_pageflip_interrupt_init(adev);
3085
3086         return 0;
3087 }
3088
3089 static int dce_v10_0_hw_fini(void *handle)
3090 {
3091         int i;
3092         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3093
3094         dce_v10_0_hpd_fini(adev);
3095
3096         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3097                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3098         }
3099
3100         dce_v10_0_pageflip_interrupt_fini(adev);
3101
3102         return 0;
3103 }
3104
3105 static int dce_v10_0_suspend(void *handle)
3106 {
3107         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3108
3109         amdgpu_atombios_scratch_regs_save(adev);
3110
3111         return dce_v10_0_hw_fini(handle);
3112 }
3113
3114 static int dce_v10_0_resume(void *handle)
3115 {
3116         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3117         int ret;
3118
3119         ret = dce_v10_0_hw_init(handle);
3120
3121         amdgpu_atombios_scratch_regs_restore(adev);
3122
3123         /* turn on the BL */
3124         if (adev->mode_info.bl_encoder) {
3125                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3126                                                                   adev->mode_info.bl_encoder);
3127                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3128                                                     bl_level);
3129         }
3130
3131         return ret;
3132 }
3133
3134 static bool dce_v10_0_is_idle(void *handle)
3135 {
3136         return true;
3137 }
3138
3139 static int dce_v10_0_wait_for_idle(void *handle)
3140 {
3141         return 0;
3142 }
3143
3144 static int dce_v10_0_check_soft_reset(void *handle)
3145 {
3146         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3147
3148         if (dce_v10_0_is_display_hung(adev))
3149                 adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang = true;
3150         else
3151                 adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang = false;
3152
3153         return 0;
3154 }
3155
3156 static int dce_v10_0_soft_reset(void *handle)
3157 {
3158         u32 srbm_soft_reset = 0, tmp;
3159         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3160
3161         if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang)
3162                 return 0;
3163
3164         if (dce_v10_0_is_display_hung(adev))
3165                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3166
3167         if (srbm_soft_reset) {
3168                 tmp = RREG32(mmSRBM_SOFT_RESET);
3169                 tmp |= srbm_soft_reset;
3170                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3171                 WREG32(mmSRBM_SOFT_RESET, tmp);
3172                 tmp = RREG32(mmSRBM_SOFT_RESET);
3173
3174                 udelay(50);
3175
3176                 tmp &= ~srbm_soft_reset;
3177                 WREG32(mmSRBM_SOFT_RESET, tmp);
3178                 tmp = RREG32(mmSRBM_SOFT_RESET);
3179
3180                 /* Wait a little for things to settle down */
3181                 udelay(50);
3182         }
3183         return 0;
3184 }
3185
3186 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3187                                                      int crtc,
3188                                                      enum amdgpu_interrupt_state state)
3189 {
3190         u32 lb_interrupt_mask;
3191
3192         if (crtc >= adev->mode_info.num_crtc) {
3193                 DRM_DEBUG("invalid crtc %d\n", crtc);
3194                 return;
3195         }
3196
3197         switch (state) {
3198         case AMDGPU_IRQ_STATE_DISABLE:
3199                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3200                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3201                                                   VBLANK_INTERRUPT_MASK, 0);
3202                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3203                 break;
3204         case AMDGPU_IRQ_STATE_ENABLE:
3205                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3206                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3207                                                   VBLANK_INTERRUPT_MASK, 1);
3208                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3209                 break;
3210         default:
3211                 break;
3212         }
3213 }
3214
3215 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3216                                                     int crtc,
3217                                                     enum amdgpu_interrupt_state state)
3218 {
3219         u32 lb_interrupt_mask;
3220
3221         if (crtc >= adev->mode_info.num_crtc) {
3222                 DRM_DEBUG("invalid crtc %d\n", crtc);
3223                 return;
3224         }
3225
3226         switch (state) {
3227         case AMDGPU_IRQ_STATE_DISABLE:
3228                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3229                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3230                                                   VLINE_INTERRUPT_MASK, 0);
3231                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3232                 break;
3233         case AMDGPU_IRQ_STATE_ENABLE:
3234                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3235                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3236                                                   VLINE_INTERRUPT_MASK, 1);
3237                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3238                 break;
3239         default:
3240                 break;
3241         }
3242 }
3243
3244 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3245                                        struct amdgpu_irq_src *source,
3246                                        unsigned hpd,
3247                                        enum amdgpu_interrupt_state state)
3248 {
3249         u32 tmp;
3250
3251         if (hpd >= adev->mode_info.num_hpd) {
3252                 DRM_DEBUG("invalid hdp %d\n", hpd);
3253                 return 0;
3254         }
3255
3256         switch (state) {
3257         case AMDGPU_IRQ_STATE_DISABLE:
3258                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3259                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3260                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3261                 break;
3262         case AMDGPU_IRQ_STATE_ENABLE:
3263                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3264                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3265                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3266                 break;
3267         default:
3268                 break;
3269         }
3270
3271         return 0;
3272 }
3273
3274 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3275                                         struct amdgpu_irq_src *source,
3276                                         unsigned type,
3277                                         enum amdgpu_interrupt_state state)
3278 {
3279         switch (type) {
3280         case AMDGPU_CRTC_IRQ_VBLANK1:
3281                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3282                 break;
3283         case AMDGPU_CRTC_IRQ_VBLANK2:
3284                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3285                 break;
3286         case AMDGPU_CRTC_IRQ_VBLANK3:
3287                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3288                 break;
3289         case AMDGPU_CRTC_IRQ_VBLANK4:
3290                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3291                 break;
3292         case AMDGPU_CRTC_IRQ_VBLANK5:
3293                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3294                 break;
3295         case AMDGPU_CRTC_IRQ_VBLANK6:
3296                 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3297                 break;
3298         case AMDGPU_CRTC_IRQ_VLINE1:
3299                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3300                 break;
3301         case AMDGPU_CRTC_IRQ_VLINE2:
3302                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3303                 break;
3304         case AMDGPU_CRTC_IRQ_VLINE3:
3305                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3306                 break;
3307         case AMDGPU_CRTC_IRQ_VLINE4:
3308                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3309                 break;
3310         case AMDGPU_CRTC_IRQ_VLINE5:
3311                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3312                 break;
3313         case AMDGPU_CRTC_IRQ_VLINE6:
3314                 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3315                 break;
3316         default:
3317                 break;
3318         }
3319         return 0;
3320 }
3321
3322 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3323                                             struct amdgpu_irq_src *src,
3324                                             unsigned type,
3325                                             enum amdgpu_interrupt_state state)
3326 {
3327         u32 reg;
3328
3329         if (type >= adev->mode_info.num_crtc) {
3330                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3331                 return -EINVAL;
3332         }
3333
3334         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3335         if (state == AMDGPU_IRQ_STATE_DISABLE)
3336                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3337                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3338         else
3339                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3340                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3341
3342         return 0;
3343 }
3344
3345 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3346                                   struct amdgpu_irq_src *source,
3347                                   struct amdgpu_iv_entry *entry)
3348 {
3349         unsigned long flags;
3350         unsigned crtc_id;
3351         struct amdgpu_crtc *amdgpu_crtc;
3352         struct amdgpu_flip_work *works;
3353
3354         crtc_id = (entry->src_id - 8) >> 1;
3355         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3356
3357         if (crtc_id >= adev->mode_info.num_crtc) {
3358                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3359                 return -EINVAL;
3360         }
3361
3362         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3363             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3364                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3365                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3366
3367         /* IRQ could occur when in initial stage */
3368         if (amdgpu_crtc == NULL)
3369                 return 0;
3370
3371         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3372         works = amdgpu_crtc->pflip_works;
3373         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3374                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3375                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3376                                                  amdgpu_crtc->pflip_status,
3377                                                  AMDGPU_FLIP_SUBMITTED);
3378                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3379                 return 0;
3380         }
3381
3382         /* page flip completed. clean up */
3383         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3384         amdgpu_crtc->pflip_works = NULL;
3385
3386         /* wakeup usersapce */
3387         if (works->event)
3388                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3389
3390         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3391
3392         drm_crtc_vblank_put(&amdgpu_crtc->base);
3393         schedule_work(&works->unpin_work);
3394
3395         return 0;
3396 }
3397
3398 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3399                                   int hpd)
3400 {
3401         u32 tmp;
3402
3403         if (hpd >= adev->mode_info.num_hpd) {
3404                 DRM_DEBUG("invalid hdp %d\n", hpd);
3405                 return;
3406         }
3407
3408         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3409         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3410         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3411 }
3412
3413 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3414                                           int crtc)
3415 {
3416         u32 tmp;
3417
3418         if (crtc >= adev->mode_info.num_crtc) {
3419                 DRM_DEBUG("invalid crtc %d\n", crtc);
3420                 return;
3421         }
3422
3423         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3424         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3425         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3426 }
3427
3428 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3429                                          int crtc)
3430 {
3431         u32 tmp;
3432
3433         if (crtc >= adev->mode_info.num_crtc) {
3434                 DRM_DEBUG("invalid crtc %d\n", crtc);
3435                 return;
3436         }
3437
3438         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3439         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3440         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3441 }
3442
3443 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3444                               struct amdgpu_irq_src *source,
3445                               struct amdgpu_iv_entry *entry)
3446 {
3447         unsigned crtc = entry->src_id - 1;
3448         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3449         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3450
3451         switch (entry->src_data) {
3452         case 0: /* vblank */
3453                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3454                         dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3455                 else
3456                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3457
3458                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3459                         drm_handle_vblank(adev->ddev, crtc);
3460                 }
3461                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3462
3463                 break;
3464         case 1: /* vline */
3465                 if (disp_int & interrupt_status_offsets[crtc].vline)
3466                         dce_v10_0_crtc_vline_int_ack(adev, crtc);
3467                 else
3468                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3469
3470                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3471
3472                 break;
3473         default:
3474                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3475                 break;
3476         }
3477
3478         return 0;
3479 }
3480
3481 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3482                              struct amdgpu_irq_src *source,
3483                              struct amdgpu_iv_entry *entry)
3484 {
3485         uint32_t disp_int, mask;
3486         unsigned hpd;
3487
3488         if (entry->src_data >= adev->mode_info.num_hpd) {
3489                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3490                 return 0;
3491         }
3492
3493         hpd = entry->src_data;
3494         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3495         mask = interrupt_status_offsets[hpd].hpd;
3496
3497         if (disp_int & mask) {
3498                 dce_v10_0_hpd_int_ack(adev, hpd);
3499                 schedule_work(&adev->hotplug_work);
3500                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3501         }
3502
3503         return 0;
3504 }
3505
3506 static int dce_v10_0_set_clockgating_state(void *handle,
3507                                           enum amd_clockgating_state state)
3508 {
3509         return 0;
3510 }
3511
3512 static int dce_v10_0_set_powergating_state(void *handle,
3513                                           enum amd_powergating_state state)
3514 {
3515         return 0;
3516 }
3517
3518 const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3519         .name = "dce_v10_0",
3520         .early_init = dce_v10_0_early_init,
3521         .late_init = NULL,
3522         .sw_init = dce_v10_0_sw_init,
3523         .sw_fini = dce_v10_0_sw_fini,
3524         .hw_init = dce_v10_0_hw_init,
3525         .hw_fini = dce_v10_0_hw_fini,
3526         .suspend = dce_v10_0_suspend,
3527         .resume = dce_v10_0_resume,
3528         .is_idle = dce_v10_0_is_idle,
3529         .wait_for_idle = dce_v10_0_wait_for_idle,
3530         .check_soft_reset = dce_v10_0_check_soft_reset,
3531         .soft_reset = dce_v10_0_soft_reset,
3532         .set_clockgating_state = dce_v10_0_set_clockgating_state,
3533         .set_powergating_state = dce_v10_0_set_powergating_state,
3534 };
3535
3536 static void
3537 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3538                           struct drm_display_mode *mode,
3539                           struct drm_display_mode *adjusted_mode)
3540 {
3541         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3542
3543         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3544
3545         /* need to call this here rather than in prepare() since we need some crtc info */
3546         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3547
3548         /* set scaler clears this on some chips */
3549         dce_v10_0_set_interleave(encoder->crtc, mode);
3550
3551         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3552                 dce_v10_0_afmt_enable(encoder, true);
3553                 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3554         }
3555 }
3556
3557 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3558 {
3559         struct amdgpu_device *adev = encoder->dev->dev_private;
3560         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3561         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3562
3563         if ((amdgpu_encoder->active_device &
3564              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3565             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3566              ENCODER_OBJECT_ID_NONE)) {
3567                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3568                 if (dig) {
3569                         dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3570                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3571                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3572                 }
3573         }
3574
3575         amdgpu_atombios_scratch_regs_lock(adev, true);
3576
3577         if (connector) {
3578                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3579
3580                 /* select the clock/data port if it uses a router */
3581                 if (amdgpu_connector->router.cd_valid)
3582                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3583
3584                 /* turn eDP panel on for mode set */
3585                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3586                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3587                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3588         }
3589
3590         /* this is needed for the pll/ss setup to work correctly in some cases */
3591         amdgpu_atombios_encoder_set_crtc_source(encoder);
3592         /* set up the FMT blocks */
3593         dce_v10_0_program_fmt(encoder);
3594 }
3595
3596 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3597 {
3598         struct drm_device *dev = encoder->dev;
3599         struct amdgpu_device *adev = dev->dev_private;
3600
3601         /* need to call this here as we need the crtc set up */
3602         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3603         amdgpu_atombios_scratch_regs_lock(adev, false);
3604 }
3605
3606 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3607 {
3608         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3609         struct amdgpu_encoder_atom_dig *dig;
3610
3611         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3612
3613         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3614                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3615                         dce_v10_0_afmt_enable(encoder, false);
3616                 dig = amdgpu_encoder->enc_priv;
3617                 dig->dig_encoder = -1;
3618         }
3619         amdgpu_encoder->active_device = 0;
3620 }
3621
3622 /* these are handled by the primary encoders */
3623 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3624 {
3625
3626 }
3627
3628 static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3629 {
3630
3631 }
3632
3633 static void
3634 dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3635                       struct drm_display_mode *mode,
3636                       struct drm_display_mode *adjusted_mode)
3637 {
3638
3639 }
3640
3641 static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3642 {
3643
3644 }
3645
3646 static void
3647 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3648 {
3649
3650 }
3651
3652 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3653         .dpms = dce_v10_0_ext_dpms,
3654         .prepare = dce_v10_0_ext_prepare,
3655         .mode_set = dce_v10_0_ext_mode_set,
3656         .commit = dce_v10_0_ext_commit,
3657         .disable = dce_v10_0_ext_disable,
3658         /* no detect for TMDS/LVDS yet */
3659 };
3660
3661 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3662         .dpms = amdgpu_atombios_encoder_dpms,
3663         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3664         .prepare = dce_v10_0_encoder_prepare,
3665         .mode_set = dce_v10_0_encoder_mode_set,
3666         .commit = dce_v10_0_encoder_commit,
3667         .disable = dce_v10_0_encoder_disable,
3668         .detect = amdgpu_atombios_encoder_dig_detect,
3669 };
3670
3671 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3672         .dpms = amdgpu_atombios_encoder_dpms,
3673         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3674         .prepare = dce_v10_0_encoder_prepare,
3675         .mode_set = dce_v10_0_encoder_mode_set,
3676         .commit = dce_v10_0_encoder_commit,
3677         .detect = amdgpu_atombios_encoder_dac_detect,
3678 };
3679
3680 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3681 {
3682         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3683         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3684                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3685         kfree(amdgpu_encoder->enc_priv);
3686         drm_encoder_cleanup(encoder);
3687         kfree(amdgpu_encoder);
3688 }
3689
3690 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3691         .destroy = dce_v10_0_encoder_destroy,
3692 };
3693
3694 static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3695                                  uint32_t encoder_enum,
3696                                  uint32_t supported_device,
3697                                  u16 caps)
3698 {
3699         struct drm_device *dev = adev->ddev;
3700         struct drm_encoder *encoder;
3701         struct amdgpu_encoder *amdgpu_encoder;
3702
3703         /* see if we already added it */
3704         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3705                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3706                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3707                         amdgpu_encoder->devices |= supported_device;
3708                         return;
3709                 }
3710
3711         }
3712
3713         /* add a new one */
3714         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3715         if (!amdgpu_encoder)
3716                 return;
3717
3718         encoder = &amdgpu_encoder->base;
3719         switch (adev->mode_info.num_crtc) {
3720         case 1:
3721                 encoder->possible_crtcs = 0x1;
3722                 break;
3723         case 2:
3724         default:
3725                 encoder->possible_crtcs = 0x3;
3726                 break;
3727         case 4:
3728                 encoder->possible_crtcs = 0xf;
3729                 break;
3730         case 6:
3731                 encoder->possible_crtcs = 0x3f;
3732                 break;
3733         }
3734
3735         amdgpu_encoder->enc_priv = NULL;
3736
3737         amdgpu_encoder->encoder_enum = encoder_enum;
3738         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3739         amdgpu_encoder->devices = supported_device;
3740         amdgpu_encoder->rmx_type = RMX_OFF;
3741         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3742         amdgpu_encoder->is_ext_encoder = false;
3743         amdgpu_encoder->caps = caps;
3744
3745         switch (amdgpu_encoder->encoder_id) {
3746         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3747         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3748                 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3749                                  DRM_MODE_ENCODER_DAC, NULL);
3750                 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3751                 break;
3752         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3753         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3754         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3755         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3756         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3757                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3758                         amdgpu_encoder->rmx_type = RMX_FULL;
3759                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3760                                          DRM_MODE_ENCODER_LVDS, NULL);
3761                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3762                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3763                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3764                                          DRM_MODE_ENCODER_DAC, NULL);
3765                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3766                 } else {
3767                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3768                                          DRM_MODE_ENCODER_TMDS, NULL);
3769                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3770                 }
3771                 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3772                 break;
3773         case ENCODER_OBJECT_ID_SI170B:
3774         case ENCODER_OBJECT_ID_CH7303:
3775         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3776         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3777         case ENCODER_OBJECT_ID_TITFP513:
3778         case ENCODER_OBJECT_ID_VT1623:
3779         case ENCODER_OBJECT_ID_HDMI_SI1930:
3780         case ENCODER_OBJECT_ID_TRAVIS:
3781         case ENCODER_OBJECT_ID_NUTMEG:
3782                 /* these are handled by the primary encoders */
3783                 amdgpu_encoder->is_ext_encoder = true;
3784                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3785                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3786                                          DRM_MODE_ENCODER_LVDS, NULL);
3787                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3788                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3789                                          DRM_MODE_ENCODER_DAC, NULL);
3790                 else
3791                         drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3792                                          DRM_MODE_ENCODER_TMDS, NULL);
3793                 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3794                 break;
3795         }
3796 }
3797
3798 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3799         .set_vga_render_state = &dce_v10_0_set_vga_render_state,
3800         .bandwidth_update = &dce_v10_0_bandwidth_update,
3801         .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3802         .vblank_wait = &dce_v10_0_vblank_wait,
3803         .is_display_hung = &dce_v10_0_is_display_hung,
3804         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3805         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3806         .hpd_sense = &dce_v10_0_hpd_sense,
3807         .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3808         .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3809         .page_flip = &dce_v10_0_page_flip,
3810         .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3811         .add_encoder = &dce_v10_0_encoder_add,
3812         .add_connector = &amdgpu_connector_add,
3813         .stop_mc_access = &dce_v10_0_stop_mc_access,
3814         .resume_mc_access = &dce_v10_0_resume_mc_access,
3815 };
3816
3817 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3818 {
3819         if (adev->mode_info.funcs == NULL)
3820                 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3821 }
3822
3823 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3824         .set = dce_v10_0_set_crtc_irq_state,
3825         .process = dce_v10_0_crtc_irq,
3826 };
3827
3828 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3829         .set = dce_v10_0_set_pageflip_irq_state,
3830         .process = dce_v10_0_pageflip_irq,
3831 };
3832
3833 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3834         .set = dce_v10_0_set_hpd_irq_state,
3835         .process = dce_v10_0_hpd_irq,
3836 };
3837
3838 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3839 {
3840         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3841         adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3842
3843         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3844         adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3845
3846         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3847         adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3848 }