drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "vid.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34
  35 #include "dce/dce_11_0_d.h"
  36 #include "dce/dce_11_0_sh_mask.h"
  37 #include "dce/dce_11_0_enum.h"
  38 #include "oss/oss_3_0_d.h"
  39 #include "oss/oss_3_0_sh_mask.h"
  40 #include "gmc/gmc_8_1_d.h"
  41 #include "gmc/gmc_8_1_sh_mask.h"
  42
  43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
  44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
  45
  46 static const u32 crtc_offsets[] =
  47 {
  48         CRTC0_REGISTER_OFFSET,
  49         CRTC1_REGISTER_OFFSET,
  50         CRTC2_REGISTER_OFFSET,
  51         CRTC3_REGISTER_OFFSET,
  52         CRTC4_REGISTER_OFFSET,
  53         CRTC5_REGISTER_OFFSET,
  54         CRTC6_REGISTER_OFFSET
  55 };
  56
  57 static const u32 hpd_offsets[] =
  58 {
  59         HPD0_REGISTER_OFFSET,
  60         HPD1_REGISTER_OFFSET,
  61         HPD2_REGISTER_OFFSET,
  62         HPD3_REGISTER_OFFSET,
  63         HPD4_REGISTER_OFFSET,
  64         HPD5_REGISTER_OFFSET
  65 };
  66
  67 static const uint32_t dig_offsets[] = {
  68         DIG0_REGISTER_OFFSET,
  69         DIG1_REGISTER_OFFSET,
  70         DIG2_REGISTER_OFFSET,
  71         DIG3_REGISTER_OFFSET,
  72         DIG4_REGISTER_OFFSET,
  73         DIG5_REGISTER_OFFSET,
  74         DIG6_REGISTER_OFFSET,
  75         DIG7_REGISTER_OFFSET,
  76         DIG8_REGISTER_OFFSET
  77 };
  78
  79 static const struct {
  80         uint32_t        reg;
  81         uint32_t        vblank;
  82         uint32_t        vline;
  83         uint32_t        hpd;
  84
  85 } interrupt_status_offsets[] = { {
  86         .reg = mmDISP_INTERRUPT_STATUS,
  87         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  88         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  89         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  90 }, {
  91         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  92         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  93         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  94         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  95 }, {
  96         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  97         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  98         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  99         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 100 }, {
 101         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 102         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 103         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 104         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 105 }, {
 106         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 107         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 108         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 109         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 110 }, {
 111         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 112         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 113         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 114         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 115 } };
 116
 117 static const u32 cz_golden_settings_a11[] =
 118 {
 119         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 120         mmFBC_MISC, 0x1f311fff, 0x14300000,
 121 };
 122
 123 static const u32 cz_mgcg_cgcg_init[] =
 124 {
 125         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 126         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 127 };
 128
 129 static const u32 stoney_golden_settings_a11[] =
 130 {
 131         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 132         mmFBC_MISC, 0x1f311fff, 0x14302000,
 133 };
 134
 135
 136 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
 137 {
 138         switch (adev->asic_type) {
 139         case CHIP_CARRIZO:
 140                 amdgpu_program_register_sequence(adev,
 141                                                  cz_mgcg_cgcg_init,
 142                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 143                 amdgpu_program_register_sequence(adev,
 144                                                  cz_golden_settings_a11,
 145                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 146                 break;
 147         case CHIP_STONEY:
 148                 amdgpu_program_register_sequence(adev,
 149                                                  stoney_golden_settings_a11,
 150                                                  (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
 151                 break;
 152         default:
 153                 break;
 154         }
 155 }
 156
 157 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
 158                                      u32 block_offset, u32 reg)
 159 {
 160         unsigned long flags;
 161         u32 r;
 162
 163         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 164         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 165         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 166         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 167
 168         return r;
 169 }
 170
 171 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
 172                                       u32 block_offset, u32 reg, u32 v)
 173 {
 174         unsigned long flags;
 175
 176         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 177         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 178         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 179         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 180 }
 181
 182 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 183 {
 184         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 185                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 186                 return true;
 187         else
 188                 return false;
 189 }
 190
 191 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 192 {
 193         u32 pos1, pos2;
 194
 195         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 196         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 197
 198         if (pos1 != pos2)
 199                 return true;
 200         else
 201                 return false;
 202 }
 203
 204 /**
 205  * dce_v11_0_vblank_wait - vblank wait asic callback.
 206  *
 207  * @adev: amdgpu_device pointer
 208  * @crtc: crtc to wait for vblank on
 209  *
 210  * Wait for vblank on the requested crtc (evergreen+).
 211  */
 212 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 213 {
 214         unsigned i = 0;
 215
 216         if (crtc >= adev->mode_info.num_crtc)
 217                 return;
 218
 219         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 220                 return;
 221
 222         /* depending on when we hit vblank, we may be close to active; if so,
 223          * wait for another frame.
 224          */
 225         while (dce_v11_0_is_in_vblank(adev, crtc)) {
 226                 if (i++ % 100 == 0) {
 227                         if (!dce_v11_0_is_counter_moving(adev, crtc))
 228                                 break;
 229                 }
 230         }
 231
 232         while (!dce_v11_0_is_in_vblank(adev, crtc)) {
 233                 if (i++ % 100 == 0) {
 234                         if (!dce_v11_0_is_counter_moving(adev, crtc))
 235                                 break;
 236                 }
 237         }
 238 }
 239
 240 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 241 {
 242         if (crtc >= adev->mode_info.num_crtc)
 243                 return 0;
 244         else
 245                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 246 }
 247
 248 /**
 249  * dce_v11_0_page_flip - pageflip callback.
 250  *
 251  * @adev: amdgpu_device pointer
 252  * @crtc_id: crtc to cleanup pageflip on
 253  * @crtc_base: new address of the crtc (GPU MC address)
 254  *
 255  * Triggers the actual pageflip by updating the primary
 256  * surface base address.
 257  */
 258 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
 259                               int crtc_id, u64 crtc_base)
 260 {
 261         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 262
 263         /* update the scanout addresses */
 264         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 265                upper_32_bits(crtc_base));
 266         /* writing to the low address triggers the update */
 267         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 268                lower_32_bits(crtc_base));
 269         /* post the write */
 270         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 271 }
 272
 273 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 274                                         u32 *vbl, u32 *position)
 275 {
 276         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 277                 return -EINVAL;
 278
 279         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 280         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 281
 282         return 0;
 283 }
 284
 285 /**
 286  * dce_v11_0_hpd_sense - hpd sense callback.
 287  *
 288  * @adev: amdgpu_device pointer
 289  * @hpd: hpd (hotplug detect) pin
 290  *
 291  * Checks if a digital monitor is connected (evergreen+).
 292  * Returns true if connected, false if not connected.
 293  */
 294 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
 295                                enum amdgpu_hpd_id hpd)
 296 {
 297         int idx;
 298         bool connected = false;
 299
 300         switch (hpd) {
 301         case AMDGPU_HPD_1:
 302                 idx = 0;
 303                 break;
 304         case AMDGPU_HPD_2:
 305                 idx = 1;
 306                 break;
 307         case AMDGPU_HPD_3:
 308                 idx = 2;
 309                 break;
 310         case AMDGPU_HPD_4:
 311                 idx = 3;
 312                 break;
 313         case AMDGPU_HPD_5:
 314                 idx = 4;
 315                 break;
 316         case AMDGPU_HPD_6:
 317                 idx = 5;
 318                 break;
 319         default:
 320                 return connected;
 321         }
 322
 323         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
 324             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 325                 connected = true;
 326
 327         return connected;
 328 }
 329
 330 /**
 331  * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
 332  *
 333  * @adev: amdgpu_device pointer
 334  * @hpd: hpd (hotplug detect) pin
 335  *
 336  * Set the polarity of the hpd pin (evergreen+).
 337  */
 338 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
 339                                       enum amdgpu_hpd_id hpd)
 340 {
 341         u32 tmp;
 342         bool connected = dce_v11_0_hpd_sense(adev, hpd);
 343         int idx;
 344
 345         switch (hpd) {
 346         case AMDGPU_HPD_1:
 347                 idx = 0;
 348                 break;
 349         case AMDGPU_HPD_2:
 350                 idx = 1;
 351                 break;
 352         case AMDGPU_HPD_3:
 353                 idx = 2;
 354                 break;
 355         case AMDGPU_HPD_4:
 356                 idx = 3;
 357                 break;
 358         case AMDGPU_HPD_5:
 359                 idx = 4;
 360                 break;
 361         case AMDGPU_HPD_6:
 362                 idx = 5;
 363                 break;
 364         default:
 365                 return;
 366         }
 367
 368         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
 369         if (connected)
 370                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 371         else
 372                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 373         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
 374 }
 375
 376 /**
 377  * dce_v11_0_hpd_init - hpd setup callback.
 378  *
 379  * @adev: amdgpu_device pointer
 380  *
 381  * Setup the hpd pins used by the card (evergreen+).
 382  * Enable the pin, set the polarity, and enable the hpd interrupts.
 383  */
 384 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
 385 {
 386         struct drm_device *dev = adev->ddev;
 387         struct drm_connector *connector;
 388         u32 tmp;
 389         int idx;
 390
 391         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 392                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 393
 394                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 395                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 396                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 397                          * aux dp channel on imac and help (but not completely fix)
 398                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 399                          * also avoid interrupt storms during dpms.
 400                          */
 401                         continue;
 402                 }
 403
 404                 switch (amdgpu_connector->hpd.hpd) {
 405                 case AMDGPU_HPD_1:
 406                         idx = 0;
 407                         break;
 408                 case AMDGPU_HPD_2:
 409                         idx = 1;
 410                         break;
 411                 case AMDGPU_HPD_3:
 412                         idx = 2;
 413                         break;
 414                 case AMDGPU_HPD_4:
 415                         idx = 3;
 416                         break;
 417                 case AMDGPU_HPD_5:
 418                         idx = 4;
 419                         break;
 420                 case AMDGPU_HPD_6:
 421                         idx = 5;
 422                         break;
 423                 default:
 424                         continue;
 425                 }
 426
 427                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 428                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 429                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 430
 431                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
 432                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 433                                     DC_HPD_CONNECT_INT_DELAY,
 434                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 435                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 436                                     DC_HPD_DISCONNECT_INT_DELAY,
 437                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 438                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
 439
 440                 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 441                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 442         }
 443 }
 444
 445 /**
 446  * dce_v11_0_hpd_fini - hpd tear down callback.
 447  *
 448  * @adev: amdgpu_device pointer
 449  *
 450  * Tear down the hpd pins used by the card (evergreen+).
 451  * Disable the hpd interrupts.
 452  */
 453 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
 454 {
 455         struct drm_device *dev = adev->ddev;
 456         struct drm_connector *connector;
 457         u32 tmp;
 458         int idx;
 459
 460         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 461                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 462
 463                 switch (amdgpu_connector->hpd.hpd) {
 464                 case AMDGPU_HPD_1:
 465                         idx = 0;
 466                         break;
 467                 case AMDGPU_HPD_2:
 468                         idx = 1;
 469                         break;
 470                 case AMDGPU_HPD_3:
 471                         idx = 2;
 472                         break;
 473                 case AMDGPU_HPD_4:
 474                         idx = 3;
 475                         break;
 476                 case AMDGPU_HPD_5:
 477                         idx = 4;
 478                         break;
 479                 case AMDGPU_HPD_6:
 480                         idx = 5;
 481                         break;
 482                 default:
 483                         continue;
 484                 }
 485
 486                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 487                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 488                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 489
 490                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 491         }
 492 }
 493
 494 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 495 {
 496         return mmDC_GPIO_HPD_A;
 497 }
 498
 499 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
 500 {
 501         u32 crtc_hung = 0;
 502         u32 crtc_status[6];
 503         u32 i, j, tmp;
 504
 505         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 506                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 507                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 508                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 509                         crtc_hung |= (1 << i);
 510                 }
 511         }
 512
 513         for (j = 0; j < 10; j++) {
 514                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 515                         if (crtc_hung & (1 << i)) {
 516                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 517                                 if (tmp != crtc_status[i])
 518                                         crtc_hung &= ~(1 << i);
 519                         }
 520                 }
 521                 if (crtc_hung == 0)
 522                         return false;
 523                 udelay(100);
 524         }
 525
 526         return true;
 527 }
 528
 529 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
 530                                      struct amdgpu_mode_mc_save *save)
 531 {
 532         u32 crtc_enabled, tmp;
 533         int i;
 534
 535         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 536         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 537
 538         /* disable VGA render */
 539         tmp = RREG32(mmVGA_RENDER_CONTROL);
 540         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 541         WREG32(mmVGA_RENDER_CONTROL, tmp);
 542
 543         /* blank the display controllers */
 544         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 545                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 546                                              CRTC_CONTROL, CRTC_MASTER_EN);
 547                 if (crtc_enabled) {
 548 #if 0
 549                         u32 frame_count;
 550                         int j;
 551
 552                         save->crtc_enabled[i] = true;
 553                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 554                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
 555                                 amdgpu_display_vblank_wait(adev, i);
 556                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 557                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
 558                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 559                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 560                         }
 561                         /* wait for the next frame */
 562                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 563                         for (j = 0; j < adev->usec_timeout; j++) {
 564                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 565                                         break;
 566                                 udelay(1);
 567                         }
 568                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 569                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
 570                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
 571                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 572                         }
 573                         tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
 574                         if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
 575                                 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
 576                                 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 577                         }
 578 #else
 579                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 580                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 581                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 582                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 583                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 584                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 585                         save->crtc_enabled[i] = false;
 586                         /* ***** */
 587 #endif
 588                 } else {
 589                         save->crtc_enabled[i] = false;
 590                 }
 591         }
 592 }
 593
 594 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
 595                                        struct amdgpu_mode_mc_save *save)
 596 {
 597         u32 tmp, frame_count;
 598         int i, j;
 599
 600         /* update crtc base addresses */
 601         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 602                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 603                        upper_32_bits(adev->mc.vram_start));
 604                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 605                        upper_32_bits(adev->mc.vram_start));
 606                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 607                        (u32)adev->mc.vram_start);
 608                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 609                        (u32)adev->mc.vram_start);
 610
 611                 if (save->crtc_enabled[i]) {
 612                         tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]);
 613                         if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
 614                                 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
 615                                 WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
 616                         }
 617                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 618                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
 619                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
 620                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 621                         }
 622                         tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
 623                         if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
 624                                 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
 625                                 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 626                         }
 627                         for (j = 0; j < adev->usec_timeout; j++) {
 628                                 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 629                                 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
 630                                         break;
 631                                 udelay(1);
 632                         }
 633                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 634                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
 635                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 636                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 637                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 638                         /* wait for the next frame */
 639                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 640                         for (j = 0; j < adev->usec_timeout; j++) {
 641                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 642                                         break;
 643                                 udelay(1);
 644                         }
 645                 }
 646         }
 647
 648         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 649         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
 650
 651         /* Unlock vga access */
 652         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 653         mdelay(1);
 654         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 655 }
 656
 657 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
 658                                            bool render)
 659 {
 660         u32 tmp;
 661
 662         /* Lockout access through VGA aperture*/
 663         tmp = RREG32(mmVGA_HDP_CONTROL);
 664         if (render)
 665                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 666         else
 667                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 668         WREG32(mmVGA_HDP_CONTROL, tmp);
 669
 670         /* disable VGA render */
 671         tmp = RREG32(mmVGA_RENDER_CONTROL);
 672         if (render)
 673                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 674         else
 675                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 676         WREG32(mmVGA_RENDER_CONTROL, tmp);
 677 }
 678
 679 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
 680 {
 681         struct drm_device *dev = encoder->dev;
 682         struct amdgpu_device *adev = dev->dev_private;
 683         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 684         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 685         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 686         int bpc = 0;
 687         u32 tmp = 0;
 688         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 689
 690         if (connector) {
 691                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 692                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 693                 dither = amdgpu_connector->dither;
 694         }
 695
 696         /* LVDS/eDP FMT is set up by atom */
 697         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 698                 return;
 699
 700         /* not needed for analog */
 701         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 702             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 703                 return;
 704
 705         if (bpc == 0)
 706                 return;
 707
 708         switch (bpc) {
 709         case 6:
 710                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 711                         /* XXX sort out optimal dither settings */
 712                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 713                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 714                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 715                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 716                 } else {
 717                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 718                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 719                 }
 720                 break;
 721         case 8:
 722                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 723                         /* XXX sort out optimal dither settings */
 724                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 725                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 726                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 727                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 728                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 729                 } else {
 730                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 731                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 732                 }
 733                 break;
 734         case 10:
 735                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 736                         /* XXX sort out optimal dither settings */
 737                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 738                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 739                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 740                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 741                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 742                 } else {
 743                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 744                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 745                 }
 746                 break;
 747         default:
 748                 /* not needed */
 749                 break;
 750         }
 751
 752         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 753 }
 754
 755
 756 /* display watermark setup */
 757 /**
 758  * dce_v11_0_line_buffer_adjust - Set up the line buffer
 759  *
 760  * @adev: amdgpu_device pointer
 761  * @amdgpu_crtc: the selected display controller
 762  * @mode: the current display mode on the selected display
 763  * controller
 764  *
 765  * Setup up the line buffer allocation for
 766  * the selected display controller (CIK).
 767  * Returns the line buffer size in pixels.
 768  */
 769 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
 770                                        struct amdgpu_crtc *amdgpu_crtc,
 771                                        struct drm_display_mode *mode)
 772 {
 773         u32 tmp, buffer_alloc, i, mem_cfg;
 774         u32 pipe_offset = amdgpu_crtc->crtc_id;
 775         /*
 776          * Line Buffer Setup
 777          * There are 6 line buffers, one for each display controllers.
 778          * There are 3 partitions per LB. Select the number of partitions
 779          * to enable based on the display width.  For display widths larger
 780          * than 4096, you need use to use 2 display controllers and combine
 781          * them using the stereo blender.
 782          */
 783         if (amdgpu_crtc->base.enabled && mode) {
 784                 if (mode->crtc_hdisplay < 1920) {
 785                         mem_cfg = 1;
 786                         buffer_alloc = 2;
 787                 } else if (mode->crtc_hdisplay < 2560) {
 788                         mem_cfg = 2;
 789                         buffer_alloc = 2;
 790                 } else if (mode->crtc_hdisplay < 4096) {
 791                         mem_cfg = 0;
 792                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 793                 } else {
 794                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 795                         mem_cfg = 0;
 796                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 797                 }
 798         } else {
 799                 mem_cfg = 1;
 800                 buffer_alloc = 0;
 801         }
 802
 803         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 804         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 805         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 806
 807         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 808         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 809         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 810
 811         for (i = 0; i < adev->usec_timeout; i++) {
 812                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 813                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 814                         break;
 815                 udelay(1);
 816         }
 817
 818         if (amdgpu_crtc->base.enabled && mode) {
 819                 switch (mem_cfg) {
 820                 case 0:
 821                 default:
 822                         return 4096 * 2;
 823                 case 1:
 824                         return 1920 * 2;
 825                 case 2:
 826                         return 2560 * 2;
 827                 }
 828         }
 829
 830         /* controller not enabled, so no lb used */
 831         return 0;
 832 }
 833
 834 /**
 835  * cik_get_number_of_dram_channels - get the number of dram channels
 836  *
 837  * @adev: amdgpu_device pointer
 838  *
 839  * Look up the number of video ram channels (CIK).
 840  * Used for display watermark bandwidth calculations
 841  * Returns the number of dram channels
 842  */
 843 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 844 {
 845         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 846
 847         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 848         case 0:
 849         default:
 850                 return 1;
 851         case 1:
 852                 return 2;
 853         case 2:
 854                 return 4;
 855         case 3:
 856                 return 8;
 857         case 4:
 858                 return 3;
 859         case 5:
 860                 return 6;
 861         case 6:
 862                 return 10;
 863         case 7:
 864                 return 12;
 865         case 8:
 866                 return 16;
 867         }
 868 }
 869
 870 struct dce10_wm_params {
 871         u32 dram_channels; /* number of dram channels */
 872         u32 yclk;          /* bandwidth per dram data pin in kHz */
 873         u32 sclk;          /* engine clock in kHz */
 874         u32 disp_clk;      /* display clock in kHz */
 875         u32 src_width;     /* viewport width */
 876         u32 active_time;   /* active display time in ns */
 877         u32 blank_time;    /* blank time in ns */
 878         bool interlaced;    /* mode is interlaced */
 879         fixed20_12 vsc;    /* vertical scale ratio */
 880         u32 num_heads;     /* number of active crtcs */
 881         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 882         u32 lb_size;       /* line buffer allocated to pipe */
 883         u32 vtaps;         /* vertical scaler taps */
 884 };
 885
 886 /**
 887  * dce_v11_0_dram_bandwidth - get the dram bandwidth
 888  *
 889  * @wm: watermark calculation data
 890  *
 891  * Calculate the raw dram bandwidth (CIK).
 892  * Used for display watermark bandwidth calculations
 893  * Returns the dram bandwidth in MBytes/s
 894  */
 895 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
 896 {
 897         /* Calculate raw DRAM Bandwidth */
 898         fixed20_12 dram_efficiency; /* 0.7 */
 899         fixed20_12 yclk, dram_channels, bandwidth;
 900         fixed20_12 a;
 901
 902         a.full = dfixed_const(1000);
 903         yclk.full = dfixed_const(wm->yclk);
 904         yclk.full = dfixed_div(yclk, a);
 905         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 906         a.full = dfixed_const(10);
 907         dram_efficiency.full = dfixed_const(7);
 908         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 909         bandwidth.full = dfixed_mul(dram_channels, yclk);
 910         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 911
 912         return dfixed_trunc(bandwidth);
 913 }
 914
 915 /**
 916  * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
 917  *
 918  * @wm: watermark calculation data
 919  *
 920  * Calculate the dram bandwidth used for display (CIK).
 921  * Used for display watermark bandwidth calculations
 922  * Returns the dram bandwidth for display in MBytes/s
 923  */
 924 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 925 {
 926         /* Calculate DRAM Bandwidth and the part allocated to display. */
 927         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 928         fixed20_12 yclk, dram_channels, bandwidth;
 929         fixed20_12 a;
 930
 931         a.full = dfixed_const(1000);
 932         yclk.full = dfixed_const(wm->yclk);
 933         yclk.full = dfixed_div(yclk, a);
 934         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 935         a.full = dfixed_const(10);
 936         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 937         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 938         bandwidth.full = dfixed_mul(dram_channels, yclk);
 939         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 940
 941         return dfixed_trunc(bandwidth);
 942 }
 943
 944 /**
 945  * dce_v11_0_data_return_bandwidth - get the data return bandwidth
 946  *
 947  * @wm: watermark calculation data
 948  *
 949  * Calculate the data return bandwidth used for display (CIK).
 950  * Used for display watermark bandwidth calculations
 951  * Returns the data return bandwidth in MBytes/s
 952  */
 953 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
 954 {
 955         /* Calculate the display Data return Bandwidth */
 956         fixed20_12 return_efficiency; /* 0.8 */
 957         fixed20_12 sclk, bandwidth;
 958         fixed20_12 a;
 959
 960         a.full = dfixed_const(1000);
 961         sclk.full = dfixed_const(wm->sclk);
 962         sclk.full = dfixed_div(sclk, a);
 963         a.full = dfixed_const(10);
 964         return_efficiency.full = dfixed_const(8);
 965         return_efficiency.full = dfixed_div(return_efficiency, a);
 966         a.full = dfixed_const(32);
 967         bandwidth.full = dfixed_mul(a, sclk);
 968         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 969
 970         return dfixed_trunc(bandwidth);
 971 }
 972
 973 /**
 974  * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
 975  *
 976  * @wm: watermark calculation data
 977  *
 978  * Calculate the dmif bandwidth used for display (CIK).
 979  * Used for display watermark bandwidth calculations
 980  * Returns the dmif bandwidth in MBytes/s
 981  */
 982 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
 983 {
 984         /* Calculate the DMIF Request Bandwidth */
 985         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 986         fixed20_12 disp_clk, bandwidth;
 987         fixed20_12 a, b;
 988
 989         a.full = dfixed_const(1000);
 990         disp_clk.full = dfixed_const(wm->disp_clk);
 991         disp_clk.full = dfixed_div(disp_clk, a);
 992         a.full = dfixed_const(32);
 993         b.full = dfixed_mul(a, disp_clk);
 994
 995         a.full = dfixed_const(10);
 996         disp_clk_request_efficiency.full = dfixed_const(8);
 997         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 998
 999         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1000
1001         return dfixed_trunc(bandwidth);
1002 }
1003
1004 /**
1005  * dce_v11_0_available_bandwidth - get the min available bandwidth
1006  *
1007  * @wm: watermark calculation data
1008  *
1009  * Calculate the min available bandwidth used for display (CIK).
1010  * Used for display watermark bandwidth calculations
1011  * Returns the min available bandwidth in MBytes/s
1012  */
1013 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
1014 {
1015         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1016         u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
1017         u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
1018         u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
1019
1020         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1021 }
1022
1023 /**
1024  * dce_v11_0_average_bandwidth - get the average available bandwidth
1025  *
1026  * @wm: watermark calculation data
1027  *
1028  * Calculate the average available bandwidth used for display (CIK).
1029  * Used for display watermark bandwidth calculations
1030  * Returns the average available bandwidth in MBytes/s
1031  */
1032 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
1033 {
1034         /* Calculate the display mode Average Bandwidth
1035          * DisplayMode should contain the source and destination dimensions,
1036          * timing, etc.
1037          */
1038         fixed20_12 bpp;
1039         fixed20_12 line_time;
1040         fixed20_12 src_width;
1041         fixed20_12 bandwidth;
1042         fixed20_12 a;
1043
1044         a.full = dfixed_const(1000);
1045         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1046         line_time.full = dfixed_div(line_time, a);
1047         bpp.full = dfixed_const(wm->bytes_per_pixel);
1048         src_width.full = dfixed_const(wm->src_width);
1049         bandwidth.full = dfixed_mul(src_width, bpp);
1050         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1051         bandwidth.full = dfixed_div(bandwidth, line_time);
1052
1053         return dfixed_trunc(bandwidth);
1054 }
1055
1056 /**
1057  * dce_v11_0_latency_watermark - get the latency watermark
1058  *
1059  * @wm: watermark calculation data
1060  *
1061  * Calculate the latency watermark (CIK).
1062  * Used for display watermark bandwidth calculations
1063  * Returns the latency watermark in ns
1064  */
1065 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1066 {
1067         /* First calculate the latency in ns */
1068         u32 mc_latency = 2000; /* 2000 ns. */
1069         u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1070         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1071         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1072         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1073         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1074                 (wm->num_heads * cursor_line_pair_return_time);
1075         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1076         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1077         u32 tmp, dmif_size = 12288;
1078         fixed20_12 a, b, c;
1079
1080         if (wm->num_heads == 0)
1081                 return 0;
1082
1083         a.full = dfixed_const(2);
1084         b.full = dfixed_const(1);
1085         if ((wm->vsc.full > a.full) ||
1086             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1087             (wm->vtaps >= 5) ||
1088             ((wm->vsc.full >= a.full) && wm->interlaced))
1089                 max_src_lines_per_dst_line = 4;
1090         else
1091                 max_src_lines_per_dst_line = 2;
1092
1093         a.full = dfixed_const(available_bandwidth);
1094         b.full = dfixed_const(wm->num_heads);
1095         a.full = dfixed_div(a, b);
1096
1097         b.full = dfixed_const(mc_latency + 512);
1098         c.full = dfixed_const(wm->disp_clk);
1099         b.full = dfixed_div(b, c);
1100
1101         c.full = dfixed_const(dmif_size);
1102         b.full = dfixed_div(c, b);
1103
1104         tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1105
1106         b.full = dfixed_const(1000);
1107         c.full = dfixed_const(wm->disp_clk);
1108         b.full = dfixed_div(c, b);
1109         c.full = dfixed_const(wm->bytes_per_pixel);
1110         b.full = dfixed_mul(b, c);
1111
1112         lb_fill_bw = min(tmp, dfixed_trunc(b));
1113
1114         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1115         b.full = dfixed_const(1000);
1116         c.full = dfixed_const(lb_fill_bw);
1117         b.full = dfixed_div(c, b);
1118         a.full = dfixed_div(a, b);
1119         line_fill_time = dfixed_trunc(a);
1120
1121         if (line_fill_time < wm->active_time)
1122                 return latency;
1123         else
1124                 return latency + (line_fill_time - wm->active_time);
1125
1126 }
1127
1128 /**
1129  * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1130  * average and available dram bandwidth
1131  *
1132  * @wm: watermark calculation data
1133  *
1134  * Check if the display average bandwidth fits in the display
1135  * dram bandwidth (CIK).
1136  * Used for display watermark bandwidth calculations
1137  * Returns true if the display fits, false if not.
1138  */
1139 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1140 {
1141         if (dce_v11_0_average_bandwidth(wm) <=
1142             (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1143                 return true;
1144         else
1145                 return false;
1146 }
1147
1148 /**
1149  * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1150  * average and available bandwidth
1151  *
1152  * @wm: watermark calculation data
1153  *
1154  * Check if the display average bandwidth fits in the display
1155  * available bandwidth (CIK).
1156  * Used for display watermark bandwidth calculations
1157  * Returns true if the display fits, false if not.
1158  */
1159 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1160 {
1161         if (dce_v11_0_average_bandwidth(wm) <=
1162             (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1163                 return true;
1164         else
1165                 return false;
1166 }
1167
1168 /**
1169  * dce_v11_0_check_latency_hiding - check latency hiding
1170  *
1171  * @wm: watermark calculation data
1172  *
1173  * Check latency hiding (CIK).
1174  * Used for display watermark bandwidth calculations
1175  * Returns true if the display fits, false if not.
1176  */
1177 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1178 {
1179         u32 lb_partitions = wm->lb_size / wm->src_width;
1180         u32 line_time = wm->active_time + wm->blank_time;
1181         u32 latency_tolerant_lines;
1182         u32 latency_hiding;
1183         fixed20_12 a;
1184
1185         a.full = dfixed_const(1);
1186         if (wm->vsc.full > a.full)
1187                 latency_tolerant_lines = 1;
1188         else {
1189                 if (lb_partitions <= (wm->vtaps + 1))
1190                         latency_tolerant_lines = 1;
1191                 else
1192                         latency_tolerant_lines = 2;
1193         }
1194
1195         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1196
1197         if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1198                 return true;
1199         else
1200                 return false;
1201 }
1202
1203 /**
1204  * dce_v11_0_program_watermarks - program display watermarks
1205  *
1206  * @adev: amdgpu_device pointer
1207  * @amdgpu_crtc: the selected display controller
1208  * @lb_size: line buffer size
1209  * @num_heads: number of display controllers in use
1210  *
1211  * Calculate and program the display watermarks for the
1212  * selected display controller (CIK).
1213  */
1214 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1215                                         struct amdgpu_crtc *amdgpu_crtc,
1216                                         u32 lb_size, u32 num_heads)
1217 {
1218         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1219         struct dce10_wm_params wm_low, wm_high;
1220         u32 pixel_period;
1221         u32 line_time = 0;
1222         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1223         u32 tmp, wm_mask;
1224
1225         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1226                 pixel_period = 1000000 / (u32)mode->clock;
1227                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1228
1229                 /* watermark for high clocks */
1230                 if (adev->pm.dpm_enabled) {
1231                         wm_high.yclk =
1232                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1233                         wm_high.sclk =
1234                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1235                 } else {
1236                         wm_high.yclk = adev->pm.current_mclk * 10;
1237                         wm_high.sclk = adev->pm.current_sclk * 10;
1238                 }
1239
1240                 wm_high.disp_clk = mode->clock;
1241                 wm_high.src_width = mode->crtc_hdisplay;
1242                 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1243                 wm_high.blank_time = line_time - wm_high.active_time;
1244                 wm_high.interlaced = false;
1245                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1246                         wm_high.interlaced = true;
1247                 wm_high.vsc = amdgpu_crtc->vsc;
1248                 wm_high.vtaps = 1;
1249                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1250                         wm_high.vtaps = 2;
1251                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1252                 wm_high.lb_size = lb_size;
1253                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1254                 wm_high.num_heads = num_heads;
1255
1256                 /* set for high clocks */
1257                 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1258
1259                 /* possibly force display priority to high */
1260                 /* should really do this at mode validation time... */
1261                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1262                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1263                     !dce_v11_0_check_latency_hiding(&wm_high) ||
1264                     (adev->mode_info.disp_priority == 2)) {
1265                         DRM_DEBUG_KMS("force priority to high\n");
1266                 }
1267
1268                 /* watermark for low clocks */
1269                 if (adev->pm.dpm_enabled) {
1270                         wm_low.yclk =
1271                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1272                         wm_low.sclk =
1273                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1274                 } else {
1275                         wm_low.yclk = adev->pm.current_mclk * 10;
1276                         wm_low.sclk = adev->pm.current_sclk * 10;
1277                 }
1278
1279                 wm_low.disp_clk = mode->clock;
1280                 wm_low.src_width = mode->crtc_hdisplay;
1281                 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1282                 wm_low.blank_time = line_time - wm_low.active_time;
1283                 wm_low.interlaced = false;
1284                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1285                         wm_low.interlaced = true;
1286                 wm_low.vsc = amdgpu_crtc->vsc;
1287                 wm_low.vtaps = 1;
1288                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1289                         wm_low.vtaps = 2;
1290                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1291                 wm_low.lb_size = lb_size;
1292                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1293                 wm_low.num_heads = num_heads;
1294
1295                 /* set for low clocks */
1296                 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1297
1298                 /* possibly force display priority to high */
1299                 /* should really do this at mode validation time... */
1300                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1301                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1302                     !dce_v11_0_check_latency_hiding(&wm_low) ||
1303                     (adev->mode_info.disp_priority == 2)) {
1304                         DRM_DEBUG_KMS("force priority to high\n");
1305                 }
1306         }
1307
1308         /* select wm A */
1309         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1310         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1311         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1312         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1313         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1314         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1315         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1316         /* select wm B */
1317         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1318         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1319         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1320         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1321         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1322         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1323         /* restore original selection */
1324         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1325
1326         /* save values for DPM */
1327         amdgpu_crtc->line_time = line_time;
1328         amdgpu_crtc->wm_high = latency_watermark_a;
1329         amdgpu_crtc->wm_low = latency_watermark_b;
1330 }
1331
1332 /**
1333  * dce_v11_0_bandwidth_update - program display watermarks
1334  *
1335  * @adev: amdgpu_device pointer
1336  *
1337  * Calculate and program the display watermarks and line
1338  * buffer allocation (CIK).
1339  */
1340 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1341 {
1342         struct drm_display_mode *mode = NULL;
1343         u32 num_heads = 0, lb_size;
1344         int i;
1345
1346         amdgpu_update_display_priority(adev);
1347
1348         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1349                 if (adev->mode_info.crtcs[i]->base.enabled)
1350                         num_heads++;
1351         }
1352         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1353                 mode = &adev->mode_info.crtcs[i]->base.mode;
1354                 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1355                 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1356                                             lb_size, num_heads);
1357         }
1358 }
1359
1360 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1361 {
1362         int i;
1363         u32 offset, tmp;
1364
1365         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1366                 offset = adev->mode_info.audio.pin[i].offset;
1367                 tmp = RREG32_AUDIO_ENDPT(offset,
1368                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1369                 if (((tmp &
1370                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1371                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1372                         adev->mode_info.audio.pin[i].connected = false;
1373                 else
1374                         adev->mode_info.audio.pin[i].connected = true;
1375         }
1376 }
1377
1378 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1379 {
1380         int i;
1381
1382         dce_v11_0_audio_get_connected_pins(adev);
1383
1384         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1385                 if (adev->mode_info.audio.pin[i].connected)
1386                         return &adev->mode_info.audio.pin[i];
1387         }
1388         DRM_ERROR("No connected audio pins found!\n");
1389         return NULL;
1390 }
1391
1392 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1393 {
1394         struct amdgpu_device *adev = encoder->dev->dev_private;
1395         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1396         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1397         u32 tmp;
1398
1399         if (!dig || !dig->afmt || !dig->afmt->pin)
1400                 return;
1401
1402         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1403         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1404         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1405 }
1406
1407 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1408                                                 struct drm_display_mode *mode)
1409 {
1410         struct amdgpu_device *adev = encoder->dev->dev_private;
1411         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1412         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1413         struct drm_connector *connector;
1414         struct amdgpu_connector *amdgpu_connector = NULL;
1415         u32 tmp;
1416         int interlace = 0;
1417
1418         if (!dig || !dig->afmt || !dig->afmt->pin)
1419                 return;
1420
1421         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1422                 if (connector->encoder == encoder) {
1423                         amdgpu_connector = to_amdgpu_connector(connector);
1424                         break;
1425                 }
1426         }
1427
1428         if (!amdgpu_connector) {
1429                 DRM_ERROR("Couldn't find encoder's connector\n");
1430                 return;
1431         }
1432
1433         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1434                 interlace = 1;
1435         if (connector->latency_present[interlace]) {
1436                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1437                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1438                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1439                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1440         } else {
1441                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1442                                     VIDEO_LIPSYNC, 0);
1443                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1444                                     AUDIO_LIPSYNC, 0);
1445         }
1446         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1447                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1448 }
1449
1450 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1451 {
1452         struct amdgpu_device *adev = encoder->dev->dev_private;
1453         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1454         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1455         struct drm_connector *connector;
1456         struct amdgpu_connector *amdgpu_connector = NULL;
1457         u32 tmp;
1458         u8 *sadb = NULL;
1459         int sad_count;
1460
1461         if (!dig || !dig->afmt || !dig->afmt->pin)
1462                 return;
1463
1464         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1465                 if (connector->encoder == encoder) {
1466                         amdgpu_connector = to_amdgpu_connector(connector);
1467                         break;
1468                 }
1469         }
1470
1471         if (!amdgpu_connector) {
1472                 DRM_ERROR("Couldn't find encoder's connector\n");
1473                 return;
1474         }
1475
1476         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1477         if (sad_count < 0) {
1478                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1479                 sad_count = 0;
1480         }
1481
1482         /* program the speaker allocation */
1483         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1484                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1485         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1486                             DP_CONNECTION, 0);
1487         /* set HDMI mode */
1488         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1489                             HDMI_CONNECTION, 1);
1490         if (sad_count)
1491                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1492                                     SPEAKER_ALLOCATION, sadb[0]);
1493         else
1494                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1495                                     SPEAKER_ALLOCATION, 5); /* stereo */
1496         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1497                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1498
1499         kfree(sadb);
1500 }
1501
1502 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1503 {
1504         struct amdgpu_device *adev = encoder->dev->dev_private;
1505         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1506         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1507         struct drm_connector *connector;
1508         struct amdgpu_connector *amdgpu_connector = NULL;
1509         struct cea_sad *sads;
1510         int i, sad_count;
1511
1512         static const u16 eld_reg_to_type[][2] = {
1513                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1514                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1515                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1516                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1517                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1518                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1519                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1520                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1521                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1522                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1523                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1524                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1525         };
1526
1527         if (!dig || !dig->afmt || !dig->afmt->pin)
1528                 return;
1529
1530         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1531                 if (connector->encoder == encoder) {
1532                         amdgpu_connector = to_amdgpu_connector(connector);
1533                         break;
1534                 }
1535         }
1536
1537         if (!amdgpu_connector) {
1538                 DRM_ERROR("Couldn't find encoder's connector\n");
1539                 return;
1540         }
1541
1542         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1543         if (sad_count <= 0) {
1544                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1545                 return;
1546         }
1547         BUG_ON(!sads);
1548
1549         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1550                 u32 tmp = 0;
1551                 u8 stereo_freqs = 0;
1552                 int max_channels = -1;
1553                 int j;
1554
1555                 for (j = 0; j < sad_count; j++) {
1556                         struct cea_sad *sad = &sads[j];
1557
1558                         if (sad->format == eld_reg_to_type[i][1]) {
1559                                 if (sad->channels > max_channels) {
1560                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1561                                                             MAX_CHANNELS, sad->channels);
1562                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1563                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1564                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1565                                                             SUPPORTED_FREQUENCIES, sad->freq);
1566                                         max_channels = sad->channels;
1567                                 }
1568
1569                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1570                                         stereo_freqs |= sad->freq;
1571                                 else
1572                                         break;
1573                         }
1574                 }
1575
1576                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1577                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1578                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1579         }
1580
1581         kfree(sads);
1582 }
1583
1584 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1585                                   struct amdgpu_audio_pin *pin,
1586                                   bool enable)
1587 {
1588         if (!pin)
1589                 return;
1590
1591         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1592                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1593 }
1594
1595 static const u32 pin_offsets[] =
1596 {
1597         AUD0_REGISTER_OFFSET,
1598         AUD1_REGISTER_OFFSET,
1599         AUD2_REGISTER_OFFSET,
1600         AUD3_REGISTER_OFFSET,
1601         AUD4_REGISTER_OFFSET,
1602         AUD5_REGISTER_OFFSET,
1603         AUD6_REGISTER_OFFSET,
1604 };
1605
1606 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1607 {
1608         int i;
1609
1610         if (!amdgpu_audio)
1611                 return 0;
1612
1613         adev->mode_info.audio.enabled = true;
1614
1615         adev->mode_info.audio.num_pins = 7;
1616
1617         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1618                 adev->mode_info.audio.pin[i].channels = -1;
1619                 adev->mode_info.audio.pin[i].rate = -1;
1620                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1621                 adev->mode_info.audio.pin[i].status_bits = 0;
1622                 adev->mode_info.audio.pin[i].category_code = 0;
1623                 adev->mode_info.audio.pin[i].connected = false;
1624                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1625                 adev->mode_info.audio.pin[i].id = i;
1626                 /* disable audio.  it will be set up later */
1627                 /* XXX remove once we switch to ip funcs */
1628                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1629         }
1630
1631         return 0;
1632 }
1633
1634 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1635 {
1636         int i;
1637
1638         if (!adev->mode_info.audio.enabled)
1639                 return;
1640
1641         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1642                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1643
1644         adev->mode_info.audio.enabled = false;
1645 }
1646
1647 /*
1648  * update the N and CTS parameters for a given pixel clock rate
1649  */
1650 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1651 {
1652         struct drm_device *dev = encoder->dev;
1653         struct amdgpu_device *adev = dev->dev_private;
1654         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1655         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1656         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1657         u32 tmp;
1658
1659         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1660         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1661         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1662         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1663         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1664         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1665
1666         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1667         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1668         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1669         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1670         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1671         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1672
1673         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1674         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1675         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1676         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1677         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1678         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1679
1680 }
1681
1682 /*
1683  * build a HDMI Video Info Frame
1684  */
1685 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1686                                                void *buffer, size_t size)
1687 {
1688         struct drm_device *dev = encoder->dev;
1689         struct amdgpu_device *adev = dev->dev_private;
1690         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1691         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1692         uint8_t *frame = buffer + 3;
1693         uint8_t *header = buffer;
1694
1695         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1696                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1697         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1698                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1699         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1700                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1701         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1702                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1703 }
1704
1705 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1706 {
1707         struct drm_device *dev = encoder->dev;
1708         struct amdgpu_device *adev = dev->dev_private;
1709         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1710         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1711         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1712         u32 dto_phase = 24 * 1000;
1713         u32 dto_modulo = clock;
1714         u32 tmp;
1715
1716         if (!dig || !dig->afmt)
1717                 return;
1718
1719         /* XXX two dtos; generally use dto0 for hdmi */
1720         /* Express [24MHz / target pixel clock] as an exact rational
1721          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1722          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1723          */
1724         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1725         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1726                             amdgpu_crtc->crtc_id);
1727         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1728         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1729         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1730 }
1731
1732 /*
1733  * update the info frames with the data from the current display mode
1734  */
1735 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1736                                   struct drm_display_mode *mode)
1737 {
1738         struct drm_device *dev = encoder->dev;
1739         struct amdgpu_device *adev = dev->dev_private;
1740         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1741         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1742         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1743         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1744         struct hdmi_avi_infoframe frame;
1745         ssize_t err;
1746         u32 tmp;
1747         int bpc = 8;
1748
1749         if (!dig || !dig->afmt)
1750                 return;
1751
1752         /* Silent, r600_hdmi_enable will raise WARN for us */
1753         if (!dig->afmt->enabled)
1754                 return;
1755
1756         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1757         if (encoder->crtc) {
1758                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1759                 bpc = amdgpu_crtc->bpc;
1760         }
1761
1762         /* disable audio prior to setting up hw */
1763         dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1764         dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1765
1766         dce_v11_0_audio_set_dto(encoder, mode->clock);
1767
1768         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1769         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1770         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1771
1772         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1773
1774         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1775         switch (bpc) {
1776         case 0:
1777         case 6:
1778         case 8:
1779         case 16:
1780         default:
1781                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1782                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1783                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1784                           connector->name, bpc);
1785                 break;
1786         case 10:
1787                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1788                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1789                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1790                           connector->name);
1791                 break;
1792         case 12:
1793                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1794                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1795                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1796                           connector->name);
1797                 break;
1798         }
1799         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1800
1801         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1802         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1803         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1804         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1805         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1806
1807         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1808         /* enable audio info frames (frames won't be set until audio is enabled) */
1809         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1810         /* required for audio info values to be updated */
1811         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1812         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1813
1814         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1815         /* required for audio info values to be updated */
1816         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1817         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1818
1819         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1820         /* anything other than 0 */
1821         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1822         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1823
1824         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1825
1826         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1827         /* set the default audio delay */
1828         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1829         /* should be suffient for all audio modes and small enough for all hblanks */
1830         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1831         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1832
1833         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1834         /* allow 60958 channel status fields to be updated */
1835         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1836         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1837
1838         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1839         if (bpc > 8)
1840                 /* clear SW CTS value */
1841                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1842         else
1843                 /* select SW CTS value */
1844                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1845         /* allow hw to sent ACR packets when required */
1846         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1847         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1848
1849         dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1850
1851         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1852         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1853         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1854
1855         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1856         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1857         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1858
1859         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1860         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1861         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1862         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1863         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1864         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1865         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1866         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1867
1868         dce_v11_0_audio_write_speaker_allocation(encoder);
1869
1870         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1871                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1872
1873         dce_v11_0_afmt_audio_select_pin(encoder);
1874         dce_v11_0_audio_write_sad_regs(encoder);
1875         dce_v11_0_audio_write_latency_fields(encoder, mode);
1876
1877         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1878         if (err < 0) {
1879                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1880                 return;
1881         }
1882
1883         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1884         if (err < 0) {
1885                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1886                 return;
1887         }
1888
1889         dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1890
1891         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1892         /* enable AVI info frames */
1893         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1894         /* required for audio info values to be updated */
1895         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1896         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1897
1898         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1899         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1900         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1901
1902         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1903         /* send audio packets */
1904         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1905         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1906
1907         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1908         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1909         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1910         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1911
1912         /* enable audio after to setting up hw */
1913         dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1914 }
1915
1916 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1917 {
1918         struct drm_device *dev = encoder->dev;
1919         struct amdgpu_device *adev = dev->dev_private;
1920         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1921         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1922
1923         if (!dig || !dig->afmt)
1924                 return;
1925
1926         /* Silent, r600_hdmi_enable will raise WARN for us */
1927         if (enable && dig->afmt->enabled)
1928                 return;
1929         if (!enable && !dig->afmt->enabled)
1930                 return;
1931
1932         if (!enable && dig->afmt->pin) {
1933                 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1934                 dig->afmt->pin = NULL;
1935         }
1936
1937         dig->afmt->enabled = enable;
1938
1939         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1940                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1941 }
1942
1943 static void dce_v11_0_afmt_init(struct amdgpu_device *adev)
1944 {
1945         int i;
1946
1947         for (i = 0; i < adev->mode_info.num_dig; i++)
1948                 adev->mode_info.afmt[i] = NULL;
1949
1950         /* DCE11 has audio blocks tied to DIG encoders */
1951         for (i = 0; i < adev->mode_info.num_dig; i++) {
1952                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1953                 if (adev->mode_info.afmt[i]) {
1954                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1955                         adev->mode_info.afmt[i]->id = i;
1956                 }
1957         }
1958 }
1959
1960 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1961 {
1962         int i;
1963
1964         for (i = 0; i < adev->mode_info.num_dig; i++) {
1965                 kfree(adev->mode_info.afmt[i]);
1966                 adev->mode_info.afmt[i] = NULL;
1967         }
1968 }
1969
1970 static const u32 vga_control_regs[6] =
1971 {
1972         mmD1VGA_CONTROL,
1973         mmD2VGA_CONTROL,
1974         mmD3VGA_CONTROL,
1975         mmD4VGA_CONTROL,
1976         mmD5VGA_CONTROL,
1977         mmD6VGA_CONTROL,
1978 };
1979
1980 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1981 {
1982         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1983         struct drm_device *dev = crtc->dev;
1984         struct amdgpu_device *adev = dev->dev_private;
1985         u32 vga_control;
1986
1987         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1988         if (enable)
1989                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1990         else
1991                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1992 }
1993
1994 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1995 {
1996         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1997         struct drm_device *dev = crtc->dev;
1998         struct amdgpu_device *adev = dev->dev_private;
1999
2000         if (enable)
2001                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2002         else
2003                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2004 }
2005
2006 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2007                                      struct drm_framebuffer *fb,
2008                                      int x, int y, int atomic)
2009 {
2010         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2011         struct drm_device *dev = crtc->dev;
2012         struct amdgpu_device *adev = dev->dev_private;
2013         struct amdgpu_framebuffer *amdgpu_fb;
2014         struct drm_framebuffer *target_fb;
2015         struct drm_gem_object *obj;
2016         struct amdgpu_bo *rbo;
2017         uint64_t fb_location, tiling_flags;
2018         uint32_t fb_format, fb_pitch_pixels;
2019         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2020         u32 pipe_config;
2021         u32 tmp, viewport_w, viewport_h;
2022         int r;
2023         bool bypass_lut = false;
2024
2025         /* no fb bound */
2026         if (!atomic && !crtc->primary->fb) {
2027                 DRM_DEBUG_KMS("No FB bound\n");
2028                 return 0;
2029         }
2030
2031         if (atomic) {
2032                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2033                 target_fb = fb;
2034         }
2035         else {
2036                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2037                 target_fb = crtc->primary->fb;
2038         }
2039
2040         /* If atomic, assume fb object is pinned & idle & fenced and
2041          * just update base pointers
2042          */
2043         obj = amdgpu_fb->obj;
2044         rbo = gem_to_amdgpu_bo(obj);
2045         r = amdgpu_bo_reserve(rbo, false);
2046         if (unlikely(r != 0))
2047                 return r;
2048
2049         if (atomic)
2050                 fb_location = amdgpu_bo_gpu_offset(rbo);
2051         else {
2052                 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2053                 if (unlikely(r != 0)) {
2054                         amdgpu_bo_unreserve(rbo);
2055                         return -EINVAL;
2056                 }
2057         }
2058
2059         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2060         amdgpu_bo_unreserve(rbo);
2061
2062         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2063
2064         switch (target_fb->pixel_format) {
2065         case DRM_FORMAT_C8:
2066                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2067                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2068                 break;
2069         case DRM_FORMAT_XRGB4444:
2070         case DRM_FORMAT_ARGB4444:
2071                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2072                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2073 #ifdef __BIG_ENDIAN
2074                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2075                                         ENDIAN_8IN16);
2076 #endif
2077                 break;
2078         case DRM_FORMAT_XRGB1555:
2079         case DRM_FORMAT_ARGB1555:
2080                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2081                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2082 #ifdef __BIG_ENDIAN
2083                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2084                                         ENDIAN_8IN16);
2085 #endif
2086                 break;
2087         case DRM_FORMAT_BGRX5551:
2088         case DRM_FORMAT_BGRA5551:
2089                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2090                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2091 #ifdef __BIG_ENDIAN
2092                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2093                                         ENDIAN_8IN16);
2094 #endif
2095                 break;
2096         case DRM_FORMAT_RGB565:
2097                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2098                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2099 #ifdef __BIG_ENDIAN
2100                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2101                                         ENDIAN_8IN16);
2102 #endif
2103                 break;
2104         case DRM_FORMAT_XRGB8888:
2105         case DRM_FORMAT_ARGB8888:
2106                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2107                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2108 #ifdef __BIG_ENDIAN
2109                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2110                                         ENDIAN_8IN32);
2111 #endif
2112                 break;
2113         case DRM_FORMAT_XRGB2101010:
2114         case DRM_FORMAT_ARGB2101010:
2115                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2116                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2117 #ifdef __BIG_ENDIAN
2118                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2119                                         ENDIAN_8IN32);
2120 #endif
2121                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2122                 bypass_lut = true;
2123                 break;
2124         case DRM_FORMAT_BGRX1010102:
2125         case DRM_FORMAT_BGRA1010102:
2126                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2127                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2128 #ifdef __BIG_ENDIAN
2129                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2130                                         ENDIAN_8IN32);
2131 #endif
2132                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2133                 bypass_lut = true;
2134                 break;
2135         default:
2136                 DRM_ERROR("Unsupported screen format %s\n",
2137                         drm_get_format_name(target_fb->pixel_format));
2138                 return -EINVAL;
2139         }
2140
2141         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2142                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2143
2144                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2145                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2146                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2147                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2148                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2149
2150                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2151                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2152                                           ARRAY_2D_TILED_THIN1);
2153                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2154                                           tile_split);
2155                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2156                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2157                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2158                                           mtaspect);
2159                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2160                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2161         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2162                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2163                                           ARRAY_1D_TILED_THIN1);
2164         }
2165
2166         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2167                                   pipe_config);
2168
2169         dce_v11_0_vga_enable(crtc, false);
2170
2171         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2172                upper_32_bits(fb_location));
2173         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2174                upper_32_bits(fb_location));
2175         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2176                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2177         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2178                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2179         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2180         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2181
2182         /*
2183          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2184          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2185          * retain the full precision throughout the pipeline.
2186          */
2187         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2188         if (bypass_lut)
2189                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2190         else
2191                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2192         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2193
2194         if (bypass_lut)
2195                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2196
2197         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2198         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2199         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2200         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2201         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2202         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2203
2204         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2205         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2206
2207         dce_v11_0_grph_enable(crtc, true);
2208
2209         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2210                target_fb->height);
2211
2212         x &= ~3;
2213         y &= ~1;
2214         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2215                (x << 16) | y);
2216         viewport_w = crtc->mode.hdisplay;
2217         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2218         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2219                (viewport_w << 16) | viewport_h);
2220
2221         /* pageflip setup */
2222         /* make sure flip is at vb rather than hb */
2223         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2224         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2225                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2226         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2227
2228         /* set pageflip to happen only at start of vblank interval (front porch) */
2229         WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2230
2231         if (!atomic && fb && fb != crtc->primary->fb) {
2232                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2233                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2234                 r = amdgpu_bo_reserve(rbo, false);
2235                 if (unlikely(r != 0))
2236                         return r;
2237                 amdgpu_bo_unpin(rbo);
2238                 amdgpu_bo_unreserve(rbo);
2239         }
2240
2241         /* Bytes per pixel may have changed */
2242         dce_v11_0_bandwidth_update(adev);
2243
2244         return 0;
2245 }
2246
2247 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2248                                      struct drm_display_mode *mode)
2249 {
2250         struct drm_device *dev = crtc->dev;
2251         struct amdgpu_device *adev = dev->dev_private;
2252         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2253         u32 tmp;
2254
2255         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2256         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2257                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2258         else
2259                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2260         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2261 }
2262
2263 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2264 {
2265         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2266         struct drm_device *dev = crtc->dev;
2267         struct amdgpu_device *adev = dev->dev_private;
2268         int i;
2269         u32 tmp;
2270
2271         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2272
2273         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2274         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2275         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2276
2277         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2278         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2279         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2280
2281         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2282         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2283         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2284
2285         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2286
2287         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2288         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2289         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2290
2291         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2292         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2293         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2294
2295         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2296         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2297
2298         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2299         for (i = 0; i < 256; i++) {
2300                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2301                        (amdgpu_crtc->lut_r[i] << 20) |
2302                        (amdgpu_crtc->lut_g[i] << 10) |
2303                        (amdgpu_crtc->lut_b[i] << 0));
2304         }
2305
2306         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2307         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2308         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2309         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2310         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2311
2312         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2313         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2314         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2315
2316         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2317         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2318         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2319
2320         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2321         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2322         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2323
2324         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2325         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2326         /* XXX this only needs to be programmed once per crtc at startup,
2327          * not sure where the best place for it is
2328          */
2329         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2330         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2331         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2332 }
2333
2334 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2335 {
2336         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2337         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2338
2339         switch (amdgpu_encoder->encoder_id) {
2340         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2341                 if (dig->linkb)
2342                         return 1;
2343                 else
2344                         return 0;
2345                 break;
2346         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2347                 if (dig->linkb)
2348                         return 3;
2349                 else
2350                         return 2;
2351                 break;
2352         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2353                 if (dig->linkb)
2354                         return 5;
2355                 else
2356                         return 4;
2357                 break;
2358         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2359                 return 6;
2360                 break;
2361         default:
2362                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2363                 return 0;
2364         }
2365 }
2366
2367 /**
2368  * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2369  *
2370  * @crtc: drm crtc
2371  *
2372  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2373  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2374  * monitors a dedicated PPLL must be used.  If a particular board has
2375  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2376  * as there is no need to program the PLL itself.  If we are not able to
2377  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2378  * avoid messing up an existing monitor.
2379  *
2380  * Asic specific PLL information
2381  *
2382  * DCE 10.x
2383  * Tonga
2384  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2385  * CI
2386  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2387  *
2388  */
2389 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2390 {
2391         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2392         struct drm_device *dev = crtc->dev;
2393         struct amdgpu_device *adev = dev->dev_private;
2394         u32 pll_in_use;
2395         int pll;
2396
2397         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2398                 if (adev->clock.dp_extclk)
2399                         /* skip PPLL programming if using ext clock */
2400                         return ATOM_PPLL_INVALID;
2401                 else {
2402                         /* use the same PPLL for all DP monitors */
2403                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2404                         if (pll != ATOM_PPLL_INVALID)
2405                                 return pll;
2406                 }
2407         } else {
2408                 /* use the same PPLL for all monitors with the same clock */
2409                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2410                 if (pll != ATOM_PPLL_INVALID)
2411                         return pll;
2412         }
2413
2414         /* XXX need to determine what plls are available on each DCE11 part */
2415         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2416         if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2417                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2418                         return ATOM_PPLL1;
2419                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2420                         return ATOM_PPLL0;
2421                 DRM_ERROR("unable to allocate a PPLL\n");
2422                 return ATOM_PPLL_INVALID;
2423         } else {
2424                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2425                         return ATOM_PPLL2;
2426                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2427                         return ATOM_PPLL1;
2428                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2429                         return ATOM_PPLL0;
2430                 DRM_ERROR("unable to allocate a PPLL\n");
2431                 return ATOM_PPLL_INVALID;
2432         }
2433         return ATOM_PPLL_INVALID;
2434 }
2435
2436 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2437 {
2438         struct amdgpu_device *adev = crtc->dev->dev_private;
2439         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2440         uint32_t cur_lock;
2441
2442         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2443         if (lock)
2444                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2445         else
2446                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2447         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2448 }
2449
2450 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2451 {
2452         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2453         struct amdgpu_device *adev = crtc->dev->dev_private;
2454         u32 tmp;
2455
2456         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2457         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2458         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2459 }
2460
2461 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2462 {
2463         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2464         struct amdgpu_device *adev = crtc->dev->dev_private;
2465         u32 tmp;
2466
2467         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2468                upper_32_bits(amdgpu_crtc->cursor_addr));
2469         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2470                lower_32_bits(amdgpu_crtc->cursor_addr));
2471
2472         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2473         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2474         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2475         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2476 }
2477
2478 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2479                                         int x, int y)
2480 {
2481         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2482         struct amdgpu_device *adev = crtc->dev->dev_private;
2483         int xorigin = 0, yorigin = 0;
2484
2485         /* avivo cursor are offset into the total surface */
2486         x += crtc->x;
2487         y += crtc->y;
2488         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2489
2490         if (x < 0) {
2491                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2492                 x = 0;
2493         }
2494         if (y < 0) {
2495                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2496                 y = 0;
2497         }
2498
2499         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2500         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2501         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2502                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2503
2504         amdgpu_crtc->cursor_x = x;
2505         amdgpu_crtc->cursor_y = y;
2506
2507         return 0;
2508 }
2509
2510 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2511                                       int x, int y)
2512 {
2513         int ret;
2514
2515         dce_v11_0_lock_cursor(crtc, true);
2516         ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2517         dce_v11_0_lock_cursor(crtc, false);
2518
2519         return ret;
2520 }
2521
2522 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2523                                       struct drm_file *file_priv,
2524                                       uint32_t handle,
2525                                       uint32_t width,
2526                                       uint32_t height,
2527                                       int32_t hot_x,
2528                                       int32_t hot_y)
2529 {
2530         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2531         struct drm_gem_object *obj;
2532         struct amdgpu_bo *aobj;
2533         int ret;
2534
2535         if (!handle) {
2536                 /* turn off cursor */
2537                 dce_v11_0_hide_cursor(crtc);
2538                 obj = NULL;
2539                 goto unpin;
2540         }
2541
2542         if ((width > amdgpu_crtc->max_cursor_width) ||
2543             (height > amdgpu_crtc->max_cursor_height)) {
2544                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2545                 return -EINVAL;
2546         }
2547
2548         obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
2549         if (!obj) {
2550                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2551                 return -ENOENT;
2552         }
2553
2554         aobj = gem_to_amdgpu_bo(obj);
2555         ret = amdgpu_bo_reserve(aobj, false);
2556         if (ret != 0) {
2557                 drm_gem_object_unreference_unlocked(obj);
2558                 return ret;
2559         }
2560
2561         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2562         amdgpu_bo_unreserve(aobj);
2563         if (ret) {
2564                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2565                 drm_gem_object_unreference_unlocked(obj);
2566                 return ret;
2567         }
2568
2569         amdgpu_crtc->cursor_width = width;
2570         amdgpu_crtc->cursor_height = height;
2571
2572         dce_v11_0_lock_cursor(crtc, true);
2573
2574         if (hot_x != amdgpu_crtc->cursor_hot_x ||
2575             hot_y != amdgpu_crtc->cursor_hot_y) {
2576                 int x, y;
2577
2578                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2579                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2580
2581                 dce_v11_0_cursor_move_locked(crtc, x, y);
2582
2583                 amdgpu_crtc->cursor_hot_x = hot_x;
2584                 amdgpu_crtc->cursor_hot_y = hot_y;
2585         }
2586
2587         dce_v11_0_show_cursor(crtc);
2588         dce_v11_0_lock_cursor(crtc, false);
2589
2590 unpin:
2591         if (amdgpu_crtc->cursor_bo) {
2592                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2593                 ret = amdgpu_bo_reserve(aobj, false);
2594                 if (likely(ret == 0)) {
2595                         amdgpu_bo_unpin(aobj);
2596                         amdgpu_bo_unreserve(aobj);
2597                 }
2598                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2599         }
2600
2601         amdgpu_crtc->cursor_bo = obj;
2602         return 0;
2603 }
2604
2605 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2606 {
2607         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2608
2609         if (amdgpu_crtc->cursor_bo) {
2610                 dce_v11_0_lock_cursor(crtc, true);
2611
2612                 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2613                                              amdgpu_crtc->cursor_y);
2614
2615                 dce_v11_0_show_cursor(crtc);
2616
2617                 dce_v11_0_lock_cursor(crtc, false);
2618         }
2619 }
2620
2621 static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2622                                     u16 *blue, uint32_t start, uint32_t size)
2623 {
2624         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2625         int end = (start + size > 256) ? 256 : start + size, i;
2626
2627         /* userspace palettes are always correct as is */
2628         for (i = start; i < end; i++) {
2629                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2630                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2631                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2632         }
2633         dce_v11_0_crtc_load_lut(crtc);
2634 }
2635
2636 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2637 {
2638         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2639
2640         drm_crtc_cleanup(crtc);
2641         destroy_workqueue(amdgpu_crtc->pflip_queue);
2642         kfree(amdgpu_crtc);
2643 }
2644
2645 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2646         .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2647         .cursor_move = dce_v11_0_crtc_cursor_move,
2648         .gamma_set = dce_v11_0_crtc_gamma_set,
2649         .set_config = amdgpu_crtc_set_config,
2650         .destroy = dce_v11_0_crtc_destroy,
2651         .page_flip = amdgpu_crtc_page_flip,
2652 };
2653
2654 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2655 {
2656         struct drm_device *dev = crtc->dev;
2657         struct amdgpu_device *adev = dev->dev_private;
2658         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2659         unsigned type;
2660
2661         switch (mode) {
2662         case DRM_MODE_DPMS_ON:
2663                 amdgpu_crtc->enabled = true;
2664                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2665                 dce_v11_0_vga_enable(crtc, true);
2666                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2667                 dce_v11_0_vga_enable(crtc, false);
2668                 /* Make sure VBLANK interrupt is still enabled */
2669                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2670                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2671                 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2672                 dce_v11_0_crtc_load_lut(crtc);
2673                 break;
2674         case DRM_MODE_DPMS_STANDBY:
2675         case DRM_MODE_DPMS_SUSPEND:
2676         case DRM_MODE_DPMS_OFF:
2677                 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
2678                 if (amdgpu_crtc->enabled) {
2679                         dce_v11_0_vga_enable(crtc, true);
2680                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2681                         dce_v11_0_vga_enable(crtc, false);
2682                 }
2683                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2684                 amdgpu_crtc->enabled = false;
2685                 break;
2686         }
2687         /* adjust pm to dpms */
2688         amdgpu_pm_compute_clocks(adev);
2689 }
2690
2691 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2692 {
2693         /* disable crtc pair power gating before programming */
2694         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2695         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2696         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2697 }
2698
2699 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2700 {
2701         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2702         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2703 }
2704
2705 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2706 {
2707         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2708         struct drm_device *dev = crtc->dev;
2709         struct amdgpu_device *adev = dev->dev_private;
2710         struct amdgpu_atom_ss ss;
2711         int i;
2712
2713         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2714         if (crtc->primary->fb) {
2715                 int r;
2716                 struct amdgpu_framebuffer *amdgpu_fb;
2717                 struct amdgpu_bo *rbo;
2718
2719                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2720                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2721                 r = amdgpu_bo_reserve(rbo, false);
2722                 if (unlikely(r))
2723                         DRM_ERROR("failed to reserve rbo before unpin\n");
2724                 else {
2725                         amdgpu_bo_unpin(rbo);
2726                         amdgpu_bo_unreserve(rbo);
2727                 }
2728         }
2729         /* disable the GRPH */
2730         dce_v11_0_grph_enable(crtc, false);
2731
2732         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2733
2734         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2735                 if (adev->mode_info.crtcs[i] &&
2736                     adev->mode_info.crtcs[i]->enabled &&
2737                     i != amdgpu_crtc->crtc_id &&
2738                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2739                         /* one other crtc is using this pll don't turn
2740                          * off the pll
2741                          */
2742                         goto done;
2743                 }
2744         }
2745
2746         switch (amdgpu_crtc->pll_id) {
2747         case ATOM_PPLL0:
2748         case ATOM_PPLL1:
2749         case ATOM_PPLL2:
2750                 /* disable the ppll */
2751                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2752                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2753                 break;
2754         default:
2755                 break;
2756         }
2757 done:
2758         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2759         amdgpu_crtc->adjusted_clock = 0;
2760         amdgpu_crtc->encoder = NULL;
2761         amdgpu_crtc->connector = NULL;
2762 }
2763
2764 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2765                                   struct drm_display_mode *mode,
2766                                   struct drm_display_mode *adjusted_mode,
2767                                   int x, int y, struct drm_framebuffer *old_fb)
2768 {
2769         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2770
2771         if (!amdgpu_crtc->adjusted_clock)
2772                 return -EINVAL;
2773
2774         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2775         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2776         dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2777         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2778         amdgpu_atombios_crtc_scaler_setup(crtc);
2779         dce_v11_0_cursor_reset(crtc);
2780         /* update the hw version fpr dpm */
2781         amdgpu_crtc->hw_mode = *adjusted_mode;
2782
2783         return 0;
2784 }
2785
2786 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2787                                      const struct drm_display_mode *mode,
2788                                      struct drm_display_mode *adjusted_mode)
2789 {
2790         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2791         struct drm_device *dev = crtc->dev;
2792         struct drm_encoder *encoder;
2793
2794         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2795         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2796                 if (encoder->crtc == crtc) {
2797                         amdgpu_crtc->encoder = encoder;
2798                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2799                         break;
2800                 }
2801         }
2802         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2803                 amdgpu_crtc->encoder = NULL;
2804                 amdgpu_crtc->connector = NULL;
2805                 return false;
2806         }
2807         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2808                 return false;
2809         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2810                 return false;
2811         /* pick pll */
2812         amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2813         /* if we can't get a PPLL for a non-DP encoder, fail */
2814         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2815             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2816                 return false;
2817
2818         return true;
2819 }
2820
2821 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2822                                   struct drm_framebuffer *old_fb)
2823 {
2824         return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2825 }
2826
2827 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2828                                          struct drm_framebuffer *fb,
2829                                          int x, int y, enum mode_set_atomic state)
2830 {
2831        return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2832 }
2833
2834 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2835         .dpms = dce_v11_0_crtc_dpms,
2836         .mode_fixup = dce_v11_0_crtc_mode_fixup,
2837         .mode_set = dce_v11_0_crtc_mode_set,
2838         .mode_set_base = dce_v11_0_crtc_set_base,
2839         .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2840         .prepare = dce_v11_0_crtc_prepare,
2841         .commit = dce_v11_0_crtc_commit,
2842         .load_lut = dce_v11_0_crtc_load_lut,
2843         .disable = dce_v11_0_crtc_disable,
2844 };
2845
2846 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2847 {
2848         struct amdgpu_crtc *amdgpu_crtc;
2849         int i;
2850
2851         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2852                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2853         if (amdgpu_crtc == NULL)
2854                 return -ENOMEM;
2855
2856         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2857
2858         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2859         amdgpu_crtc->crtc_id = index;
2860         amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
2861         adev->mode_info.crtcs[index] = amdgpu_crtc;
2862
2863         amdgpu_crtc->max_cursor_width = 128;
2864         amdgpu_crtc->max_cursor_height = 128;
2865         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2866         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2867
2868         for (i = 0; i < 256; i++) {
2869                 amdgpu_crtc->lut_r[i] = i << 2;
2870                 amdgpu_crtc->lut_g[i] = i << 2;
2871                 amdgpu_crtc->lut_b[i] = i << 2;
2872         }
2873
2874         switch (amdgpu_crtc->crtc_id) {
2875         case 0:
2876         default:
2877                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2878                 break;
2879         case 1:
2880                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2881                 break;
2882         case 2:
2883                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2884                 break;
2885         case 3:
2886                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2887                 break;
2888         case 4:
2889                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2890                 break;
2891         case 5:
2892                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2893                 break;
2894         }
2895
2896         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2897         amdgpu_crtc->adjusted_clock = 0;
2898         amdgpu_crtc->encoder = NULL;
2899         amdgpu_crtc->connector = NULL;
2900         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2901
2902         return 0;
2903 }
2904
2905 static int dce_v11_0_early_init(void *handle)
2906 {
2907         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2908
2909         adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2910         adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2911
2912         dce_v11_0_set_display_funcs(adev);
2913         dce_v11_0_set_irq_funcs(adev);
2914
2915         switch (adev->asic_type) {
2916         case CHIP_CARRIZO:
2917                 adev->mode_info.num_crtc = 3;
2918                 adev->mode_info.num_hpd = 6;
2919                 adev->mode_info.num_dig = 9;
2920                 break;
2921         case CHIP_STONEY:
2922                 adev->mode_info.num_crtc = 2;
2923                 adev->mode_info.num_hpd = 6;
2924                 adev->mode_info.num_dig = 9;
2925                 break;
2926         default:
2927                 /* FIXME: not supported yet */
2928                 return -EINVAL;
2929         }
2930
2931         return 0;
2932 }
2933
2934 static int dce_v11_0_sw_init(void *handle)
2935 {
2936         int r, i;
2937         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2938
2939         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2940                 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2941                 if (r)
2942                 return r;
2943         }
2944
2945         for (i = 8; i < 20; i += 2) {
2946                 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2947                 if (r)
2948                         return r;
2949         }
2950
2951         /* HPD hotplug */
2952         r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2953         if (r)
2954         return r;
2955
2956         adev->mode_info.mode_config_initialized = true;
2957
2958         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2959
2960         adev->ddev->mode_config.max_width = 16384;
2961         adev->ddev->mode_config.max_height = 16384;
2962
2963         adev->ddev->mode_config.preferred_depth = 24;
2964         adev->ddev->mode_config.prefer_shadow = 1;
2965
2966         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2967
2968         r = amdgpu_modeset_create_props(adev);
2969         if (r)
2970                 return r;
2971
2972         adev->ddev->mode_config.max_width = 16384;
2973         adev->ddev->mode_config.max_height = 16384;
2974
2975         /* allocate crtcs */
2976         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2977                 r = dce_v11_0_crtc_init(adev, i);
2978                 if (r)
2979                         return r;
2980         }
2981
2982         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2983                 amdgpu_print_display_setup(adev->ddev);
2984         else
2985                 return -EINVAL;
2986
2987         /* setup afmt */
2988         dce_v11_0_afmt_init(adev);
2989
2990         r = dce_v11_0_audio_init(adev);
2991         if (r)
2992                 return r;
2993
2994         drm_kms_helper_poll_init(adev->ddev);
2995
2996         return r;
2997 }
2998
2999 static int dce_v11_0_sw_fini(void *handle)
3000 {
3001         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3002
3003         kfree(adev->mode_info.bios_hardcoded_edid);
3004
3005         drm_kms_helper_poll_fini(adev->ddev);
3006
3007         dce_v11_0_audio_fini(adev);
3008
3009         dce_v11_0_afmt_fini(adev);
3010
3011         adev->mode_info.mode_config_initialized = false;
3012
3013         return 0;
3014 }
3015
3016 static int dce_v11_0_hw_init(void *handle)
3017 {
3018         int i;
3019         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3020
3021         dce_v11_0_init_golden_registers(adev);
3022
3023         /* init dig PHYs, disp eng pll */
3024         amdgpu_atombios_crtc_powergate_init(adev);
3025         amdgpu_atombios_encoder_init_dig(adev);
3026         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3027
3028         /* initialize hpd */
3029         dce_v11_0_hpd_init(adev);
3030
3031         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3032                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3033         }
3034
3035         return 0;
3036 }
3037
3038 static int dce_v11_0_hw_fini(void *handle)
3039 {
3040         int i;
3041         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3042
3043         dce_v11_0_hpd_fini(adev);
3044
3045         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3046                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3047         }
3048
3049         return 0;
3050 }
3051
3052 static int dce_v11_0_suspend(void *handle)
3053 {
3054         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3055
3056         amdgpu_atombios_scratch_regs_save(adev);
3057
3058         return dce_v11_0_hw_fini(handle);
3059 }
3060
3061 static int dce_v11_0_resume(void *handle)
3062 {
3063         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3064         int ret;
3065
3066         ret = dce_v11_0_hw_init(handle);
3067
3068         amdgpu_atombios_scratch_regs_restore(adev);
3069
3070         /* turn on the BL */
3071         if (adev->mode_info.bl_encoder) {
3072                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3073                                                                   adev->mode_info.bl_encoder);
3074                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3075                                                     bl_level);
3076         }
3077
3078         return ret;
3079 }
3080
3081 static bool dce_v11_0_is_idle(void *handle)
3082 {
3083         return true;
3084 }
3085
3086 static int dce_v11_0_wait_for_idle(void *handle)
3087 {
3088         return 0;
3089 }
3090
3091 static void dce_v11_0_print_status(void *handle)
3092 {
3093         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3094
3095         dev_info(adev->dev, "DCE 10.x registers\n");
3096         /* XXX todo */
3097 }
3098
3099 static int dce_v11_0_soft_reset(void *handle)
3100 {
3101         u32 srbm_soft_reset = 0, tmp;
3102         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3103
3104         if (dce_v11_0_is_display_hung(adev))
3105                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3106
3107         if (srbm_soft_reset) {
3108                 dce_v11_0_print_status((void *)adev);
3109
3110                 tmp = RREG32(mmSRBM_SOFT_RESET);
3111                 tmp |= srbm_soft_reset;
3112                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3113                 WREG32(mmSRBM_SOFT_RESET, tmp);
3114                 tmp = RREG32(mmSRBM_SOFT_RESET);
3115
3116                 udelay(50);
3117
3118                 tmp &= ~srbm_soft_reset;
3119                 WREG32(mmSRBM_SOFT_RESET, tmp);
3120                 tmp = RREG32(mmSRBM_SOFT_RESET);
3121
3122                 /* Wait a little for things to settle down */
3123                 udelay(50);
3124                 dce_v11_0_print_status((void *)adev);
3125         }
3126         return 0;
3127 }
3128
3129 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3130                                                      int crtc,
3131                                                      enum amdgpu_interrupt_state state)
3132 {
3133         u32 lb_interrupt_mask;
3134
3135         if (crtc >= adev->mode_info.num_crtc) {
3136                 DRM_DEBUG("invalid crtc %d\n", crtc);
3137                 return;
3138         }
3139
3140         switch (state) {
3141         case AMDGPU_IRQ_STATE_DISABLE:
3142                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3143                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3144                                                   VBLANK_INTERRUPT_MASK, 0);
3145                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3146                 break;
3147         case AMDGPU_IRQ_STATE_ENABLE:
3148                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3149                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3150                                                   VBLANK_INTERRUPT_MASK, 1);
3151                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3152                 break;
3153         default:
3154                 break;
3155         }
3156 }
3157
3158 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3159                                                     int crtc,
3160                                                     enum amdgpu_interrupt_state state)
3161 {
3162         u32 lb_interrupt_mask;
3163
3164         if (crtc >= adev->mode_info.num_crtc) {
3165                 DRM_DEBUG("invalid crtc %d\n", crtc);
3166                 return;
3167         }
3168
3169         switch (state) {
3170         case AMDGPU_IRQ_STATE_DISABLE:
3171                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3172                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3173                                                   VLINE_INTERRUPT_MASK, 0);
3174                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3175                 break;
3176         case AMDGPU_IRQ_STATE_ENABLE:
3177                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3178                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3179                                                   VLINE_INTERRUPT_MASK, 1);
3180                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3181                 break;
3182         default:
3183                 break;
3184         }
3185 }
3186
3187 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3188                                         struct amdgpu_irq_src *source,
3189                                         unsigned hpd,
3190                                         enum amdgpu_interrupt_state state)
3191 {
3192         u32 tmp;
3193
3194         if (hpd >= adev->mode_info.num_hpd) {
3195                 DRM_DEBUG("invalid hdp %d\n", hpd);
3196                 return 0;
3197         }
3198
3199         switch (state) {
3200         case AMDGPU_IRQ_STATE_DISABLE:
3201                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3202                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3203                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3204                 break;
3205         case AMDGPU_IRQ_STATE_ENABLE:
3206                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3207                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3208                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3209                 break;
3210         default:
3211                 break;
3212         }
3213
3214         return 0;
3215 }
3216
3217 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3218                                         struct amdgpu_irq_src *source,
3219                                         unsigned type,
3220                                         enum amdgpu_interrupt_state state)
3221 {
3222         switch (type) {
3223         case AMDGPU_CRTC_IRQ_VBLANK1:
3224                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3225                 break;
3226         case AMDGPU_CRTC_IRQ_VBLANK2:
3227                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3228                 break;
3229         case AMDGPU_CRTC_IRQ_VBLANK3:
3230                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3231                 break;
3232         case AMDGPU_CRTC_IRQ_VBLANK4:
3233                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3234                 break;
3235         case AMDGPU_CRTC_IRQ_VBLANK5:
3236                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3237                 break;
3238         case AMDGPU_CRTC_IRQ_VBLANK6:
3239                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3240                 break;
3241         case AMDGPU_CRTC_IRQ_VLINE1:
3242                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3243                 break;
3244         case AMDGPU_CRTC_IRQ_VLINE2:
3245                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3246                 break;
3247         case AMDGPU_CRTC_IRQ_VLINE3:
3248                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3249                 break;
3250         case AMDGPU_CRTC_IRQ_VLINE4:
3251                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3252                 break;
3253         case AMDGPU_CRTC_IRQ_VLINE5:
3254                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3255                 break;
3256          case AMDGPU_CRTC_IRQ_VLINE6:
3257                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3258                 break;
3259         default:
3260                 break;
3261         }
3262         return 0;
3263 }
3264
3265 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3266                                             struct amdgpu_irq_src *src,
3267                                             unsigned type,
3268                                             enum amdgpu_interrupt_state state)
3269 {
3270         u32 reg;
3271
3272         if (type >= adev->mode_info.num_crtc) {
3273                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3274                 return -EINVAL;
3275         }
3276
3277         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3278         if (state == AMDGPU_IRQ_STATE_DISABLE)
3279                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3280                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3281         else
3282                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3283                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3284
3285         return 0;
3286 }
3287
3288 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3289                                   struct amdgpu_irq_src *source,
3290                                   struct amdgpu_iv_entry *entry)
3291 {
3292         unsigned long flags;
3293         unsigned crtc_id;
3294         struct amdgpu_crtc *amdgpu_crtc;
3295         struct amdgpu_flip_work *works;
3296
3297         crtc_id = (entry->src_id - 8) >> 1;
3298         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3299
3300         if (crtc_id >= adev->mode_info.num_crtc) {
3301                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3302                 return -EINVAL;
3303         }
3304
3305         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3306             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3307                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3308                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3309
3310         /* IRQ could occur when in initial stage */
3311         if(amdgpu_crtc == NULL)
3312                 return 0;
3313
3314         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3315         works = amdgpu_crtc->pflip_works;
3316         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3317                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3318                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3319                                                  amdgpu_crtc->pflip_status,
3320                                                  AMDGPU_FLIP_SUBMITTED);
3321                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3322                 return 0;
3323         }
3324
3325         /* page flip completed. clean up */
3326         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3327         amdgpu_crtc->pflip_works = NULL;
3328
3329         /* wakeup usersapce */
3330         if(works->event)
3331                 drm_send_vblank_event(adev->ddev, crtc_id, works->event);
3332
3333         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3334
3335         drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
3336         amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id);
3337         queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
3338
3339         return 0;
3340 }
3341
3342 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3343                                   int hpd)
3344 {
3345         u32 tmp;
3346
3347         if (hpd >= adev->mode_info.num_hpd) {
3348                 DRM_DEBUG("invalid hdp %d\n", hpd);
3349                 return;
3350         }
3351
3352         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3353         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3354         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3355 }
3356
3357 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3358                                           int crtc)
3359 {
3360         u32 tmp;
3361
3362         if (crtc >= adev->mode_info.num_crtc) {
3363                 DRM_DEBUG("invalid crtc %d\n", crtc);
3364                 return;
3365         }
3366
3367         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3368         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3369         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3370 }
3371
3372 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3373                                          int crtc)
3374 {
3375         u32 tmp;
3376
3377         if (crtc >= adev->mode_info.num_crtc) {
3378                 DRM_DEBUG("invalid crtc %d\n", crtc);
3379                 return;
3380         }
3381
3382         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3383         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3384         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3385 }
3386
3387 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3388                                 struct amdgpu_irq_src *source,
3389                                 struct amdgpu_iv_entry *entry)
3390 {
3391         unsigned crtc = entry->src_id - 1;
3392         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3393         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3394
3395         switch (entry->src_data) {
3396         case 0: /* vblank */
3397                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3398                         dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3399                 else
3400                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3401
3402                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3403                         drm_handle_vblank(adev->ddev, crtc);
3404                 }
3405                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3406
3407                 break;
3408         case 1: /* vline */
3409                 if (disp_int & interrupt_status_offsets[crtc].vline)
3410                         dce_v11_0_crtc_vline_int_ack(adev, crtc);
3411                 else
3412                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3413
3414                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3415
3416                 break;
3417         default:
3418                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3419                 break;
3420         }
3421
3422         return 0;
3423 }
3424
3425 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3426                              struct amdgpu_irq_src *source,
3427                              struct amdgpu_iv_entry *entry)
3428 {
3429         uint32_t disp_int, mask;
3430         unsigned hpd;
3431
3432         if (entry->src_data >= adev->mode_info.num_hpd) {
3433                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3434                 return 0;
3435         }
3436
3437         hpd = entry->src_data;
3438         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3439         mask = interrupt_status_offsets[hpd].hpd;
3440
3441         if (disp_int & mask) {
3442                 dce_v11_0_hpd_int_ack(adev, hpd);
3443                 schedule_work(&adev->hotplug_work);
3444                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3445         }
3446
3447         return 0;
3448 }
3449
3450 static int dce_v11_0_set_clockgating_state(void *handle,
3451                                           enum amd_clockgating_state state)
3452 {
3453         return 0;
3454 }
3455
3456 static int dce_v11_0_set_powergating_state(void *handle,
3457                                           enum amd_powergating_state state)
3458 {
3459         return 0;
3460 }
3461
3462 const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3463         .early_init = dce_v11_0_early_init,
3464         .late_init = NULL,
3465         .sw_init = dce_v11_0_sw_init,
3466         .sw_fini = dce_v11_0_sw_fini,
3467         .hw_init = dce_v11_0_hw_init,
3468         .hw_fini = dce_v11_0_hw_fini,
3469         .suspend = dce_v11_0_suspend,
3470         .resume = dce_v11_0_resume,
3471         .is_idle = dce_v11_0_is_idle,
3472         .wait_for_idle = dce_v11_0_wait_for_idle,
3473         .soft_reset = dce_v11_0_soft_reset,
3474         .print_status = dce_v11_0_print_status,
3475         .set_clockgating_state = dce_v11_0_set_clockgating_state,
3476         .set_powergating_state = dce_v11_0_set_powergating_state,
3477 };
3478
3479 static void
3480 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3481                           struct drm_display_mode *mode,
3482                           struct drm_display_mode *adjusted_mode)
3483 {
3484         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3485
3486         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3487
3488         /* need to call this here rather than in prepare() since we need some crtc info */
3489         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3490
3491         /* set scaler clears this on some chips */
3492         dce_v11_0_set_interleave(encoder->crtc, mode);
3493
3494         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3495                 dce_v11_0_afmt_enable(encoder, true);
3496                 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3497         }
3498 }
3499
3500 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3501 {
3502         struct amdgpu_device *adev = encoder->dev->dev_private;
3503         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3504         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3505
3506         if ((amdgpu_encoder->active_device &
3507              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3508             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3509              ENCODER_OBJECT_ID_NONE)) {
3510                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3511                 if (dig) {
3512                         dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3513                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3514                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3515                 }
3516         }
3517
3518         amdgpu_atombios_scratch_regs_lock(adev, true);
3519
3520         if (connector) {
3521                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3522
3523                 /* select the clock/data port if it uses a router */
3524                 if (amdgpu_connector->router.cd_valid)
3525                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3526
3527                 /* turn eDP panel on for mode set */
3528                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3529                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3530                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3531         }
3532
3533         /* this is needed for the pll/ss setup to work correctly in some cases */
3534         amdgpu_atombios_encoder_set_crtc_source(encoder);
3535         /* set up the FMT blocks */
3536         dce_v11_0_program_fmt(encoder);
3537 }
3538
3539 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3540 {
3541         struct drm_device *dev = encoder->dev;
3542         struct amdgpu_device *adev = dev->dev_private;
3543
3544         /* need to call this here as we need the crtc set up */
3545         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3546         amdgpu_atombios_scratch_regs_lock(adev, false);
3547 }
3548
3549 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3550 {
3551         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3552         struct amdgpu_encoder_atom_dig *dig;
3553
3554         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3555
3556         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3557                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3558                         dce_v11_0_afmt_enable(encoder, false);
3559                 dig = amdgpu_encoder->enc_priv;
3560                 dig->dig_encoder = -1;
3561         }
3562         amdgpu_encoder->active_device = 0;
3563 }
3564
3565 /* these are handled by the primary encoders */
3566 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3567 {
3568
3569 }
3570
3571 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3572 {
3573
3574 }
3575
3576 static void
3577 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3578                       struct drm_display_mode *mode,
3579                       struct drm_display_mode *adjusted_mode)
3580 {
3581
3582 }
3583
3584 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3585 {
3586
3587 }
3588
3589 static void
3590 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3591 {
3592
3593 }
3594
3595 static bool dce_v11_0_ext_mode_fixup(struct drm_encoder *encoder,
3596                                     const struct drm_display_mode *mode,
3597                                     struct drm_display_mode *adjusted_mode)
3598 {
3599         return true;
3600 }
3601
3602 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3603         .dpms = dce_v11_0_ext_dpms,
3604         .mode_fixup = dce_v11_0_ext_mode_fixup,
3605         .prepare = dce_v11_0_ext_prepare,
3606         .mode_set = dce_v11_0_ext_mode_set,
3607         .commit = dce_v11_0_ext_commit,
3608         .disable = dce_v11_0_ext_disable,
3609         /* no detect for TMDS/LVDS yet */
3610 };
3611
3612 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3613         .dpms = amdgpu_atombios_encoder_dpms,
3614         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3615         .prepare = dce_v11_0_encoder_prepare,
3616         .mode_set = dce_v11_0_encoder_mode_set,
3617         .commit = dce_v11_0_encoder_commit,
3618         .disable = dce_v11_0_encoder_disable,
3619         .detect = amdgpu_atombios_encoder_dig_detect,
3620 };
3621
3622 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3623         .dpms = amdgpu_atombios_encoder_dpms,
3624         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3625         .prepare = dce_v11_0_encoder_prepare,
3626         .mode_set = dce_v11_0_encoder_mode_set,
3627         .commit = dce_v11_0_encoder_commit,
3628         .detect = amdgpu_atombios_encoder_dac_detect,
3629 };
3630
3631 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3632 {
3633         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3634         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3635                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3636         kfree(amdgpu_encoder->enc_priv);
3637         drm_encoder_cleanup(encoder);
3638         kfree(amdgpu_encoder);
3639 }
3640
3641 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3642         .destroy = dce_v11_0_encoder_destroy,
3643 };
3644
3645 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3646                                  uint32_t encoder_enum,
3647                                  uint32_t supported_device,
3648                                  u16 caps)
3649 {
3650         struct drm_device *dev = adev->ddev;
3651         struct drm_encoder *encoder;
3652         struct amdgpu_encoder *amdgpu_encoder;
3653
3654         /* see if we already added it */
3655         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3656                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3657                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3658                         amdgpu_encoder->devices |= supported_device;
3659                         return;
3660                 }
3661
3662         }
3663
3664         /* add a new one */
3665         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3666         if (!amdgpu_encoder)
3667                 return;
3668
3669         encoder = &amdgpu_encoder->base;
3670         switch (adev->mode_info.num_crtc) {
3671         case 1:
3672                 encoder->possible_crtcs = 0x1;
3673                 break;
3674         case 2:
3675         default:
3676                 encoder->possible_crtcs = 0x3;
3677                 break;
3678         case 4:
3679                 encoder->possible_crtcs = 0xf;
3680                 break;
3681         case 6:
3682                 encoder->possible_crtcs = 0x3f;
3683                 break;
3684         }
3685
3686         amdgpu_encoder->enc_priv = NULL;
3687
3688         amdgpu_encoder->encoder_enum = encoder_enum;
3689         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3690         amdgpu_encoder->devices = supported_device;
3691         amdgpu_encoder->rmx_type = RMX_OFF;
3692         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3693         amdgpu_encoder->is_ext_encoder = false;
3694         amdgpu_encoder->caps = caps;
3695
3696         switch (amdgpu_encoder->encoder_id) {
3697         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3698         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3699                 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3700                                  DRM_MODE_ENCODER_DAC);
3701                 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3702                 break;
3703         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3704         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3705         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3706         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3707         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3708                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3709                         amdgpu_encoder->rmx_type = RMX_FULL;
3710                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3711                                          DRM_MODE_ENCODER_LVDS);
3712                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3713                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3714                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3715                                          DRM_MODE_ENCODER_DAC);
3716                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3717                 } else {
3718                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3719                                          DRM_MODE_ENCODER_TMDS);
3720                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3721                 }
3722                 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3723                 break;
3724         case ENCODER_OBJECT_ID_SI170B:
3725         case ENCODER_OBJECT_ID_CH7303:
3726         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3727         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3728         case ENCODER_OBJECT_ID_TITFP513:
3729         case ENCODER_OBJECT_ID_VT1623:
3730         case ENCODER_OBJECT_ID_HDMI_SI1930:
3731         case ENCODER_OBJECT_ID_TRAVIS:
3732         case ENCODER_OBJECT_ID_NUTMEG:
3733                 /* these are handled by the primary encoders */
3734                 amdgpu_encoder->is_ext_encoder = true;
3735                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3736                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3737                                          DRM_MODE_ENCODER_LVDS);
3738                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3739                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3740                                          DRM_MODE_ENCODER_DAC);
3741                 else
3742                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3743                                          DRM_MODE_ENCODER_TMDS);
3744                 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3745                 break;
3746         }
3747 }
3748
3749 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3750         .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3751         .bandwidth_update = &dce_v11_0_bandwidth_update,
3752         .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3753         .vblank_wait = &dce_v11_0_vblank_wait,
3754         .is_display_hung = &dce_v11_0_is_display_hung,
3755         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3756         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3757         .hpd_sense = &dce_v11_0_hpd_sense,
3758         .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3759         .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3760         .page_flip = &dce_v11_0_page_flip,
3761         .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3762         .add_encoder = &dce_v11_0_encoder_add,
3763         .add_connector = &amdgpu_connector_add,
3764         .stop_mc_access = &dce_v11_0_stop_mc_access,
3765         .resume_mc_access = &dce_v11_0_resume_mc_access,
3766 };
3767
3768 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3769 {
3770         if (adev->mode_info.funcs == NULL)
3771                 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3772 }
3773
3774 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3775         .set = dce_v11_0_set_crtc_irq_state,
3776         .process = dce_v11_0_crtc_irq,
3777 };
3778
3779 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3780         .set = dce_v11_0_set_pageflip_irq_state,
3781         .process = dce_v11_0_pageflip_irq,
3782 };
3783
3784 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3785         .set = dce_v11_0_set_hpd_irq_state,
3786         .process = dce_v11_0_hpd_irq,
3787 };
3788
3789 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3790 {
3791         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3792         adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3793
3794         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3795         adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3796
3797         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3798         adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3799 }