2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "oss/oss_3_0_d.h"
33 #include "oss/oss_3_0_sh_mask.h"
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "tonga_sdma_pkt_open.h"
47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
57 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
59 SDMA0_REGISTER_OFFSET,
63 static const u32 golden_settings_tonga_a11[] =
65 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
66 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
67 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
68 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
69 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
70 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
71 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
72 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
73 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
74 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
77 static const u32 tonga_mgcg_cgcg_init[] =
79 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
80 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
83 static const u32 cz_golden_settings_a11[] =
85 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
86 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
87 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
88 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
89 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
90 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
91 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
92 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
93 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
94 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
95 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
96 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
99 static const u32 cz_mgcg_cgcg_init[] =
101 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
102 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
107 * Starting with CIK, the GPU has new asynchronous
108 * DMA engines. These engines are used for compute
109 * and gfx. There are two DMA engines (SDMA0, SDMA1)
110 * and each one supports 1 ring buffer used for gfx
111 * and 2 queues used for compute.
113 * The programming model is very similar to the CP
114 * (ring buffer, IBs, etc.), but sDMA has it's own
115 * packet format that is different from the PM4 format
116 * used by the CP. sDMA supports copying data, writing
117 * embedded data, solid fills, and a number of other
118 * things. It also has support for tiling/detiling of
122 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
124 switch (adev->asic_type) {
126 amdgpu_program_register_sequence(adev,
127 tonga_mgcg_cgcg_init,
128 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
129 amdgpu_program_register_sequence(adev,
130 golden_settings_tonga_a11,
131 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
134 amdgpu_program_register_sequence(adev,
136 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
137 amdgpu_program_register_sequence(adev,
138 cz_golden_settings_a11,
139 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
147 * sdma_v3_0_init_microcode - load ucode images from disk
149 * @adev: amdgpu_device pointer
151 * Use the firmware interface to load the ucode images into
152 * the driver (not loaded into hw).
153 * Returns 0 on success, error on failure.
155 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
157 const char *chip_name;
160 struct amdgpu_firmware_info *info = NULL;
161 const struct common_firmware_header *header = NULL;
165 switch (adev->asic_type) {
170 chip_name = "carrizo";
175 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
177 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
179 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
180 err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
183 err = amdgpu_ucode_validate(adev->sdma[i].fw);
187 if (adev->firmware.smu_load) {
188 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
189 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
190 info->fw = adev->sdma[i].fw;
191 header = (const struct common_firmware_header *)info->fw->data;
192 adev->firmware.fw_size +=
193 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
199 "sdma_v3_0: Failed to load firmware \"%s\"\n",
201 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
202 release_firmware(adev->sdma[i].fw);
203 adev->sdma[i].fw = NULL;
210 * sdma_v3_0_ring_get_rptr - get the current read pointer
212 * @ring: amdgpu ring pointer
214 * Get the current rptr from the hardware (VI+).
216 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
220 /* XXX check if swapping is necessary on BE */
221 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
227 * sdma_v3_0_ring_get_wptr - get the current write pointer
229 * @ring: amdgpu ring pointer
231 * Get the current wptr from the hardware (VI+).
233 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
235 struct amdgpu_device *adev = ring->adev;
238 if (ring->use_doorbell) {
239 /* XXX check if swapping is necessary on BE */
240 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
242 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
244 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
251 * sdma_v3_0_ring_set_wptr - commit the write pointer
253 * @ring: amdgpu ring pointer
255 * Write the wptr back to the hardware (VI+).
257 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
259 struct amdgpu_device *adev = ring->adev;
261 if (ring->use_doorbell) {
262 /* XXX check if swapping is necessary on BE */
263 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
264 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
266 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
268 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
273 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
275 * @ring: amdgpu ring pointer
276 * @ib: IB object to schedule
278 * Schedule an IB in the DMA ring (VI).
280 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
281 struct amdgpu_ib *ib)
283 u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
284 u32 next_rptr = ring->wptr + 5;
286 while ((next_rptr & 7) != 2)
290 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
291 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
292 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
293 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
294 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
295 amdgpu_ring_write(ring, next_rptr);
297 /* IB packet must end on a 8 DW boundary */
298 while ((ring->wptr & 7) != 2)
299 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_NOP));
301 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
302 SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
303 /* base must be 32 byte aligned */
304 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
305 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
306 amdgpu_ring_write(ring, ib->length_dw);
307 amdgpu_ring_write(ring, 0);
308 amdgpu_ring_write(ring, 0);
313 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
315 * @ring: amdgpu ring pointer
317 * Emit an hdp flush packet on the requested DMA ring.
319 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
321 u32 ref_and_mask = 0;
323 if (ring == &ring->adev->sdma[0].ring)
324 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
326 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
328 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
329 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
330 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
331 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
332 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
333 amdgpu_ring_write(ring, ref_and_mask); /* reference */
334 amdgpu_ring_write(ring, ref_and_mask); /* mask */
335 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
336 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
340 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
342 * @ring: amdgpu ring pointer
343 * @fence: amdgpu fence object
345 * Add a DMA fence packet to the ring to write
346 * the fence seq number and DMA trap packet to generate
347 * an interrupt if needed (VI).
349 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
352 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
353 /* write the fence */
354 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
355 amdgpu_ring_write(ring, lower_32_bits(addr));
356 amdgpu_ring_write(ring, upper_32_bits(addr));
357 amdgpu_ring_write(ring, lower_32_bits(seq));
359 /* optionally write high bits as well */
362 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
363 amdgpu_ring_write(ring, lower_32_bits(addr));
364 amdgpu_ring_write(ring, upper_32_bits(addr));
365 amdgpu_ring_write(ring, upper_32_bits(seq));
368 /* generate an interrupt */
369 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
370 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
375 * sdma_v3_0_ring_emit_semaphore - emit a semaphore on the dma ring
377 * @ring: amdgpu_ring structure holding ring information
378 * @semaphore: amdgpu semaphore object
379 * @emit_wait: wait or signal semaphore
381 * Add a DMA semaphore packet to the ring wait on or signal
384 static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring,
385 struct amdgpu_semaphore *semaphore,
388 u64 addr = semaphore->gpu_addr;
389 u32 sig = emit_wait ? 0 : 1;
391 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
392 SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
393 amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
394 amdgpu_ring_write(ring, upper_32_bits(addr));
400 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
402 * @adev: amdgpu_device pointer
404 * Stop the gfx async dma ring buffers (VI).
406 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
408 struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
409 struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
410 u32 rb_cntl, ib_cntl;
413 if ((adev->mman.buffer_funcs_ring == sdma0) ||
414 (adev->mman.buffer_funcs_ring == sdma1))
415 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
417 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
418 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
419 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
420 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
421 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
422 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
423 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
425 sdma0->ready = false;
426 sdma1->ready = false;
430 * sdma_v3_0_rlc_stop - stop the compute async dma engines
432 * @adev: amdgpu_device pointer
434 * Stop the compute async dma queues (VI).
436 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
442 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
444 * @adev: amdgpu_device pointer
445 * @enable: enable/disable the DMA MEs context switch.
447 * Halt or unhalt the async dma engines context switch (VI).
449 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
454 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
455 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
457 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
458 AUTO_CTXSW_ENABLE, 1);
460 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
461 AUTO_CTXSW_ENABLE, 0);
462 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
467 * sdma_v3_0_enable - stop the async dma engines
469 * @adev: amdgpu_device pointer
470 * @enable: enable/disable the DMA MEs.
472 * Halt or unhalt the async dma engines (VI).
474 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
479 if (enable == false) {
480 sdma_v3_0_gfx_stop(adev);
481 sdma_v3_0_rlc_stop(adev);
484 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
485 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
487 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
489 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
490 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
495 * sdma_v3_0_gfx_resume - setup and start the async dma engines
497 * @adev: amdgpu_device pointer
499 * Set up the gfx DMA ring buffers and enable them (VI).
500 * Returns 0 for success, error for failure.
502 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
504 struct amdgpu_ring *ring;
505 u32 rb_cntl, ib_cntl;
511 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
512 ring = &adev->sdma[i].ring;
513 wb_offset = (ring->rptr_offs * 4);
515 mutex_lock(&adev->srbm_mutex);
516 for (j = 0; j < 16; j++) {
517 vi_srbm_select(adev, 0, 0, 0, j);
519 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
520 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
522 vi_srbm_select(adev, 0, 0, 0, 0);
523 mutex_unlock(&adev->srbm_mutex);
525 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
527 /* Set ring buffer size in dwords */
528 rb_bufsz = order_base_2(ring->ring_size / 4);
529 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
530 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
532 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
533 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
534 RPTR_WRITEBACK_SWAP_ENABLE, 1);
536 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
538 /* Initialize the ring buffer's read and write pointers */
539 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
540 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
542 /* set the wb address whether it's enabled or not */
543 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
544 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
545 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
546 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
548 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
550 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
551 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
554 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
556 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
558 if (ring->use_doorbell) {
559 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
560 OFFSET, ring->doorbell_index);
561 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
563 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
565 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
568 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
569 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
571 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
572 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
574 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
577 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
581 r = amdgpu_ring_test_ring(ring);
587 if (adev->mman.buffer_funcs_ring == ring)
588 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
595 * sdma_v3_0_rlc_resume - setup and start the async dma engines
597 * @adev: amdgpu_device pointer
599 * Set up the compute DMA queues and enable them (VI).
600 * Returns 0 for success, error for failure.
602 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
609 * sdma_v3_0_load_microcode - load the sDMA ME ucode
611 * @adev: amdgpu_device pointer
613 * Loads the sDMA0/1 ucode.
614 * Returns 0 for success, -EINVAL if the ucode is not available.
616 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
618 const struct sdma_firmware_header_v1_0 *hdr;
619 const __le32 *fw_data;
623 if (!adev->sdma[0].fw || !adev->sdma[1].fw)
627 sdma_v3_0_enable(adev, false);
629 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
630 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
631 amdgpu_ucode_print_sdma_hdr(&hdr->header);
632 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
633 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
635 fw_data = (const __le32 *)
636 (adev->sdma[i].fw->data +
637 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
638 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
639 for (j = 0; j < fw_size; j++)
640 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
641 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
648 * sdma_v3_0_start - setup and start the async dma engines
650 * @adev: amdgpu_device pointer
652 * Set up the DMA engines and enable them (VI).
653 * Returns 0 for success, error for failure.
655 static int sdma_v3_0_start(struct amdgpu_device *adev)
659 if (!adev->firmware.smu_load) {
660 r = sdma_v3_0_load_microcode(adev);
664 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
665 AMDGPU_UCODE_ID_SDMA0);
668 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
669 AMDGPU_UCODE_ID_SDMA1);
675 sdma_v3_0_enable(adev, true);
676 /* enable sdma ring preemption */
677 sdma_v3_0_ctx_switch_enable(adev, true);
679 /* start the gfx rings and rlc compute queues */
680 r = sdma_v3_0_gfx_resume(adev);
683 r = sdma_v3_0_rlc_resume(adev);
691 * sdma_v3_0_ring_test_ring - simple async dma engine test
693 * @ring: amdgpu_ring structure holding ring information
695 * Test the DMA engine by writing using it to write an
696 * value to memory. (VI).
697 * Returns 0 for success, error for failure.
699 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
701 struct amdgpu_device *adev = ring->adev;
708 r = amdgpu_wb_get(adev, &index);
710 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
714 gpu_addr = adev->wb.gpu_addr + (index * 4);
716 adev->wb.wb[index] = cpu_to_le32(tmp);
718 r = amdgpu_ring_lock(ring, 5);
720 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
721 amdgpu_wb_free(adev, index);
725 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
726 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
727 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
728 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
729 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
730 amdgpu_ring_write(ring, 0xDEADBEEF);
731 amdgpu_ring_unlock_commit(ring);
733 for (i = 0; i < adev->usec_timeout; i++) {
734 tmp = le32_to_cpu(adev->wb.wb[index]);
735 if (tmp == 0xDEADBEEF)
740 if (i < adev->usec_timeout) {
741 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
743 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
747 amdgpu_wb_free(adev, index);
753 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
755 * @ring: amdgpu_ring structure holding ring information
757 * Test a simple IB in the DMA ring (VI).
758 * Returns 0 on success, error on failure.
760 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
762 struct amdgpu_device *adev = ring->adev;
770 r = amdgpu_wb_get(adev, &index);
772 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
776 gpu_addr = adev->wb.gpu_addr + (index * 4);
778 adev->wb.wb[index] = cpu_to_le32(tmp);
780 r = amdgpu_ib_get(ring, NULL, 256, &ib);
782 amdgpu_wb_free(adev, index);
783 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
787 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
788 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
789 ib.ptr[1] = lower_32_bits(gpu_addr);
790 ib.ptr[2] = upper_32_bits(gpu_addr);
791 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
792 ib.ptr[4] = 0xDEADBEEF;
793 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
794 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
795 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
798 r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
800 amdgpu_ib_free(adev, &ib);
801 amdgpu_wb_free(adev, index);
802 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
805 r = amdgpu_fence_wait(ib.fence, false);
807 amdgpu_ib_free(adev, &ib);
808 amdgpu_wb_free(adev, index);
809 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
812 for (i = 0; i < adev->usec_timeout; i++) {
813 tmp = le32_to_cpu(adev->wb.wb[index]);
814 if (tmp == 0xDEADBEEF)
818 if (i < adev->usec_timeout) {
819 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
820 ib.fence->ring->idx, i);
822 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
825 amdgpu_ib_free(adev, &ib);
826 amdgpu_wb_free(adev, index);
831 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
833 * @ib: indirect buffer to fill with commands
834 * @pe: addr of the page entry
835 * @src: src addr to copy from
836 * @count: number of page entries to update
838 * Update PTEs by copying them from the GART using sDMA (CIK).
840 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
841 uint64_t pe, uint64_t src,
845 unsigned bytes = count * 8;
846 if (bytes > 0x1FFFF8)
849 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
850 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
851 ib->ptr[ib->length_dw++] = bytes;
852 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
853 ib->ptr[ib->length_dw++] = lower_32_bits(src);
854 ib->ptr[ib->length_dw++] = upper_32_bits(src);
855 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
856 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
865 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
867 * @ib: indirect buffer to fill with commands
868 * @pe: addr of the page entry
869 * @addr: dst addr to write into pe
870 * @count: number of page entries to update
871 * @incr: increase next addr by incr bytes
872 * @flags: access flags
874 * Update PTEs by writing them manually using sDMA (CIK).
876 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
878 uint64_t addr, unsigned count,
879 uint32_t incr, uint32_t flags)
889 /* for non-physically contiguous pages (system) */
890 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
891 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
892 ib->ptr[ib->length_dw++] = pe;
893 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
894 ib->ptr[ib->length_dw++] = ndw;
895 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
896 if (flags & AMDGPU_PTE_SYSTEM) {
897 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
898 value &= 0xFFFFFFFFFFFFF000ULL;
899 } else if (flags & AMDGPU_PTE_VALID) {
906 ib->ptr[ib->length_dw++] = value;
907 ib->ptr[ib->length_dw++] = upper_32_bits(value);
913 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
915 * @ib: indirect buffer to fill with commands
916 * @pe: addr of the page entry
917 * @addr: dst addr to write into pe
918 * @count: number of page entries to update
919 * @incr: increase next addr by incr bytes
920 * @flags: access flags
922 * Update the page tables using sDMA (CIK).
924 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib,
926 uint64_t addr, unsigned count,
927 uint32_t incr, uint32_t flags)
937 if (flags & AMDGPU_PTE_VALID)
942 /* for physically contiguous pages (vram) */
943 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
944 ib->ptr[ib->length_dw++] = pe; /* dst addr */
945 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
946 ib->ptr[ib->length_dw++] = flags; /* mask */
947 ib->ptr[ib->length_dw++] = 0;
948 ib->ptr[ib->length_dw++] = value; /* value */
949 ib->ptr[ib->length_dw++] = upper_32_bits(value);
950 ib->ptr[ib->length_dw++] = incr; /* increment size */
951 ib->ptr[ib->length_dw++] = 0;
952 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
961 * sdma_v3_0_vm_pad_ib - pad the IB to the required number of dw
963 * @ib: indirect buffer to fill with padding
966 static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib)
968 while (ib->length_dw & 0x7)
969 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
973 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
975 * @ring: amdgpu_ring pointer
976 * @vm: amdgpu_vm pointer
978 * Update the page table base and flush the VM TLB
981 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
982 unsigned vm_id, uint64_t pd_addr)
984 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
985 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
987 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
989 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
991 amdgpu_ring_write(ring, pd_addr >> 12);
994 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
995 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
996 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
997 amdgpu_ring_write(ring, 1 << vm_id);
1000 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1001 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1002 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1003 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1004 amdgpu_ring_write(ring, 0);
1005 amdgpu_ring_write(ring, 0); /* reference */
1006 amdgpu_ring_write(ring, 0); /* mask */
1007 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1008 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1011 static int sdma_v3_0_early_init(void *handle)
1013 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1015 sdma_v3_0_set_ring_funcs(adev);
1016 sdma_v3_0_set_buffer_funcs(adev);
1017 sdma_v3_0_set_vm_pte_funcs(adev);
1018 sdma_v3_0_set_irq_funcs(adev);
1023 static int sdma_v3_0_sw_init(void *handle)
1025 struct amdgpu_ring *ring;
1027 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1029 /* SDMA trap event */
1030 r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
1034 /* SDMA Privileged inst */
1035 r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
1039 /* SDMA Privileged inst */
1040 r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
1044 r = sdma_v3_0_init_microcode(adev);
1046 DRM_ERROR("Failed to load sdma firmware!\n");
1050 ring = &adev->sdma[0].ring;
1051 ring->ring_obj = NULL;
1052 ring->use_doorbell = true;
1053 ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE0;
1055 ring = &adev->sdma[1].ring;
1056 ring->ring_obj = NULL;
1057 ring->use_doorbell = true;
1058 ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE1;
1060 ring = &adev->sdma[0].ring;
1061 sprintf(ring->name, "sdma0");
1062 r = amdgpu_ring_init(adev, ring, 256 * 1024,
1063 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1064 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
1065 AMDGPU_RING_TYPE_SDMA);
1069 ring = &adev->sdma[1].ring;
1070 sprintf(ring->name, "sdma1");
1071 r = amdgpu_ring_init(adev, ring, 256 * 1024,
1072 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1073 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
1074 AMDGPU_RING_TYPE_SDMA);
1081 static int sdma_v3_0_sw_fini(void *handle)
1083 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1085 amdgpu_ring_fini(&adev->sdma[0].ring);
1086 amdgpu_ring_fini(&adev->sdma[1].ring);
1091 static int sdma_v3_0_hw_init(void *handle)
1094 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1096 sdma_v3_0_init_golden_registers(adev);
1098 r = sdma_v3_0_start(adev);
1105 static int sdma_v3_0_hw_fini(void *handle)
1107 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1109 sdma_v3_0_ctx_switch_enable(adev, false);
1110 sdma_v3_0_enable(adev, false);
1115 static int sdma_v3_0_suspend(void *handle)
1117 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1119 return sdma_v3_0_hw_fini(adev);
1122 static int sdma_v3_0_resume(void *handle)
1124 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1126 return sdma_v3_0_hw_init(adev);
1129 static bool sdma_v3_0_is_idle(void *handle)
1131 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1132 u32 tmp = RREG32(mmSRBM_STATUS2);
1134 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1135 SRBM_STATUS2__SDMA1_BUSY_MASK))
1141 static int sdma_v3_0_wait_for_idle(void *handle)
1145 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1147 for (i = 0; i < adev->usec_timeout; i++) {
1148 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1149 SRBM_STATUS2__SDMA1_BUSY_MASK);
1158 static void sdma_v3_0_print_status(void *handle)
1161 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1163 dev_info(adev->dev, "VI SDMA registers\n");
1164 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1165 RREG32(mmSRBM_STATUS2));
1166 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
1167 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
1168 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1169 dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n",
1170 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1171 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
1172 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1173 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1174 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1175 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1176 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1177 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1178 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1179 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1180 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1181 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1182 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1183 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1184 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1185 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1186 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1187 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1188 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1189 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1190 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1191 dev_info(adev->dev, " SDMA%d_GFX_DOORBELL=0x%08X\n",
1192 i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]));
1193 mutex_lock(&adev->srbm_mutex);
1194 for (j = 0; j < 16; j++) {
1195 vi_srbm_select(adev, 0, 0, 0, j);
1196 dev_info(adev->dev, " VM %d:\n", j);
1197 dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1198 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1199 dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1200 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1202 vi_srbm_select(adev, 0, 0, 0, 0);
1203 mutex_unlock(&adev->srbm_mutex);
1207 static int sdma_v3_0_soft_reset(void *handle)
1209 u32 srbm_soft_reset = 0;
1210 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1211 u32 tmp = RREG32(mmSRBM_STATUS2);
1213 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1215 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1216 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1217 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1218 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1220 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1222 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1223 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1224 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1225 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1228 if (srbm_soft_reset) {
1229 sdma_v3_0_print_status((void *)adev);
1231 tmp = RREG32(mmSRBM_SOFT_RESET);
1232 tmp |= srbm_soft_reset;
1233 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1234 WREG32(mmSRBM_SOFT_RESET, tmp);
1235 tmp = RREG32(mmSRBM_SOFT_RESET);
1239 tmp &= ~srbm_soft_reset;
1240 WREG32(mmSRBM_SOFT_RESET, tmp);
1241 tmp = RREG32(mmSRBM_SOFT_RESET);
1243 /* Wait a little for things to settle down */
1246 sdma_v3_0_print_status((void *)adev);
1252 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1253 struct amdgpu_irq_src *source,
1255 enum amdgpu_interrupt_state state)
1260 case AMDGPU_SDMA_IRQ_TRAP0:
1262 case AMDGPU_IRQ_STATE_DISABLE:
1263 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1264 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1265 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1267 case AMDGPU_IRQ_STATE_ENABLE:
1268 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1269 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1270 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1276 case AMDGPU_SDMA_IRQ_TRAP1:
1278 case AMDGPU_IRQ_STATE_DISABLE:
1279 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1280 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1281 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1283 case AMDGPU_IRQ_STATE_ENABLE:
1284 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1285 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1286 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1298 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1299 struct amdgpu_irq_src *source,
1300 struct amdgpu_iv_entry *entry)
1302 u8 instance_id, queue_id;
1304 instance_id = (entry->ring_id & 0x3) >> 0;
1305 queue_id = (entry->ring_id & 0xc) >> 2;
1306 DRM_DEBUG("IH: SDMA trap\n");
1307 switch (instance_id) {
1311 amdgpu_fence_process(&adev->sdma[0].ring);
1324 amdgpu_fence_process(&adev->sdma[1].ring);
1338 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1339 struct amdgpu_irq_src *source,
1340 struct amdgpu_iv_entry *entry)
1342 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1343 schedule_work(&adev->reset_work);
1347 static int sdma_v3_0_set_clockgating_state(void *handle,
1348 enum amd_clockgating_state state)
1353 static int sdma_v3_0_set_powergating_state(void *handle,
1354 enum amd_powergating_state state)
1359 const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1360 .early_init = sdma_v3_0_early_init,
1362 .sw_init = sdma_v3_0_sw_init,
1363 .sw_fini = sdma_v3_0_sw_fini,
1364 .hw_init = sdma_v3_0_hw_init,
1365 .hw_fini = sdma_v3_0_hw_fini,
1366 .suspend = sdma_v3_0_suspend,
1367 .resume = sdma_v3_0_resume,
1368 .is_idle = sdma_v3_0_is_idle,
1369 .wait_for_idle = sdma_v3_0_wait_for_idle,
1370 .soft_reset = sdma_v3_0_soft_reset,
1371 .print_status = sdma_v3_0_print_status,
1372 .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1373 .set_powergating_state = sdma_v3_0_set_powergating_state,
1377 * sdma_v3_0_ring_is_lockup - Check if the DMA engine is locked up
1379 * @ring: amdgpu_ring structure holding ring information
1381 * Check if the async DMA engine is locked up (VI).
1382 * Returns true if the engine appears to be locked up, false if not.
1384 static bool sdma_v3_0_ring_is_lockup(struct amdgpu_ring *ring)
1387 if (sdma_v3_0_is_idle(ring->adev)) {
1388 amdgpu_ring_lockup_update(ring);
1391 return amdgpu_ring_test_lockup(ring);
1394 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1395 .get_rptr = sdma_v3_0_ring_get_rptr,
1396 .get_wptr = sdma_v3_0_ring_get_wptr,
1397 .set_wptr = sdma_v3_0_ring_set_wptr,
1399 .emit_ib = sdma_v3_0_ring_emit_ib,
1400 .emit_fence = sdma_v3_0_ring_emit_fence,
1401 .emit_semaphore = sdma_v3_0_ring_emit_semaphore,
1402 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1403 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1404 .test_ring = sdma_v3_0_ring_test_ring,
1405 .test_ib = sdma_v3_0_ring_test_ib,
1406 .is_lockup = sdma_v3_0_ring_is_lockup,
1409 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1411 adev->sdma[0].ring.funcs = &sdma_v3_0_ring_funcs;
1412 adev->sdma[1].ring.funcs = &sdma_v3_0_ring_funcs;
1415 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1416 .set = sdma_v3_0_set_trap_irq_state,
1417 .process = sdma_v3_0_process_trap_irq,
1420 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1421 .process = sdma_v3_0_process_illegal_inst_irq,
1424 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1426 adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1427 adev->sdma_trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1428 adev->sdma_illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1432 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1434 * @ring: amdgpu_ring structure holding ring information
1435 * @src_offset: src GPU address
1436 * @dst_offset: dst GPU address
1437 * @byte_count: number of bytes to xfer
1439 * Copy GPU buffers using the DMA engine (VI).
1440 * Used by the amdgpu ttm implementation to move pages if
1441 * registered as the asic copy callback.
1443 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ring *ring,
1444 uint64_t src_offset,
1445 uint64_t dst_offset,
1446 uint32_t byte_count)
1448 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1449 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR));
1450 amdgpu_ring_write(ring, byte_count);
1451 amdgpu_ring_write(ring, 0); /* src/dst endian swap */
1452 amdgpu_ring_write(ring, lower_32_bits(src_offset));
1453 amdgpu_ring_write(ring, upper_32_bits(src_offset));
1454 amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1455 amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1459 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1461 * @ring: amdgpu_ring structure holding ring information
1462 * @src_data: value to write to buffer
1463 * @dst_offset: dst GPU address
1464 * @byte_count: number of bytes to xfer
1466 * Fill GPU buffers using the DMA engine (VI).
1468 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ring *ring,
1470 uint64_t dst_offset,
1471 uint32_t byte_count)
1473 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL));
1474 amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1475 amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1476 amdgpu_ring_write(ring, src_data);
1477 amdgpu_ring_write(ring, byte_count);
1480 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1481 .copy_max_bytes = 0x1fffff,
1483 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1485 .fill_max_bytes = 0x1fffff,
1487 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1490 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1492 if (adev->mman.buffer_funcs == NULL) {
1493 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1494 adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
1498 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1499 .copy_pte = sdma_v3_0_vm_copy_pte,
1500 .write_pte = sdma_v3_0_vm_write_pte,
1501 .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1502 .pad_ib = sdma_v3_0_vm_pad_ib,
1505 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1507 if (adev->vm_manager.vm_pte_funcs == NULL) {
1508 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1509 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;