drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/fb.h>
  26 #include <asm/div64.h>
  27 #include "linux/delay.h"
  28 #include "pp_acpi.h"
  29 #include "hwmgr.h"
  30 #include "polaris10_hwmgr.h"
  31 #include "polaris10_powertune.h"
  32 #include "polaris10_dyn_defaults.h"
  33 #include "polaris10_smumgr.h"
  34 #include "pp_debug.h"
  35 #include "ppatomctrl.h"
  36 #include "atombios.h"
  37 #include "tonga_pptable.h"
  38 #include "pppcielanes.h"
  39 #include "amd_pcie_helpers.h"
  40 #include "hardwaremanager.h"
  41 #include "tonga_processpptables.h"
  42 #include "cgs_common.h"
  43 #include "smu74.h"
  44 #include "smu_ucode_xfer_vi.h"
  45 #include "smu74_discrete.h"
  46 #include "smu/smu_7_1_3_d.h"
  47 #include "smu/smu_7_1_3_sh_mask.h"
  48 #include "gmc/gmc_8_1_d.h"
  49 #include "gmc/gmc_8_1_sh_mask.h"
  50 #include "oss/oss_3_0_d.h"
  51 #include "gca/gfx_8_0_d.h"
  52 #include "bif/bif_5_0_d.h"
  53 #include "bif/bif_5_0_sh_mask.h"
  54 #include "gmc/gmc_8_1_d.h"
  55 #include "gmc/gmc_8_1_sh_mask.h"
  56 #include "bif/bif_5_0_d.h"
  57 #include "bif/bif_5_0_sh_mask.h"
  58 #include "dce/dce_10_0_d.h"
  59 #include "dce/dce_10_0_sh_mask.h"
  60
  61 #include "polaris10_thermal.h"
  62 #include "polaris10_clockpowergating.h"
  63
  64 #define MC_CG_ARB_FREQ_F0           0x0a
  65 #define MC_CG_ARB_FREQ_F1           0x0b
  66 #define MC_CG_ARB_FREQ_F2           0x0c
  67 #define MC_CG_ARB_FREQ_F3           0x0d
  68
  69 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  70 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  71 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  72 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  73
  74
  75 #define SMC_RAM_END 0x40000
  76
  77 #define SMC_CG_IND_START            0xc0030000
  78 #define SMC_CG_IND_END              0xc0040000
  79
  80 #define VOLTAGE_SCALE               4
  81 #define VOLTAGE_VID_OFFSET_SCALE1   625
  82 #define VOLTAGE_VID_OFFSET_SCALE2   100
  83
  84 #define VDDC_VDDCI_DELTA            200
  85
  86 #define MEM_FREQ_LOW_LATENCY        25000
  87 #define MEM_FREQ_HIGH_LATENCY       80000
  88
  89 #define MEM_LATENCY_HIGH            45
  90 #define MEM_LATENCY_LOW             35
  91 #define MEM_LATENCY_ERR             0xFFFF
  92
  93 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  94 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  95 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  96
  97
  98 #define PCIE_BUS_CLK                10000
  99 #define TCLK                        (PCIE_BUS_CLK / 10)
 100
 101
 102 static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
 103 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
 104
 105 /*  [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
 106 static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
 107 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
 108   { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
 109
 110 /*  [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
 111 static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
 112 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
 113
 114 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 115 enum DPM_EVENT_SRC {
 116         DPM_EVENT_SRC_ANALOG = 0,
 117         DPM_EVENT_SRC_EXTERNAL = 1,
 118         DPM_EVENT_SRC_DIGITAL = 2,
 119         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
 120         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 121 };
 122
 123 static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
 124
 125 struct polaris10_power_state *cast_phw_polaris10_power_state(
 126                                   struct pp_hw_power_state *hw_ps)
 127 {
 128         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 129                                 "Invalid Powerstate Type!",
 130                                  return NULL);
 131
 132         return (struct polaris10_power_state *)hw_ps;
 133 }
 134
 135 const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
 136                                  const struct pp_hw_power_state *hw_ps)
 137 {
 138         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 139                                 "Invalid Powerstate Type!",
 140                                  return NULL);
 141
 142         return (const struct polaris10_power_state *)hw_ps;
 143 }
 144
 145 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
 146 {
 147         return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
 148                         CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
 149                         ? true : false;
 150 }
 151
 152 /**
 153  * Find the MC microcode version and store it in the HwMgr struct
 154  *
 155  * @param    hwmgr  the address of the powerplay hardware manager.
 156  * @return   always 0
 157  */
 158 int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
 159 {
 160         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 161
 162         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
 163
 164         return 0;
 165 }
 166
 167 uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 168 {
 169         uint32_t speedCntl = 0;
 170
 171         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 172         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 173                         ixPCIE_LC_SPEED_CNTL);
 174         return((uint16_t)PHM_GET_FIELD(speedCntl,
 175                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 176 }
 177
 178 int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 179 {
 180         uint32_t link_width;
 181
 182         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 183         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 184                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 185
 186         PP_ASSERT_WITH_CODE((7 >= link_width),
 187                         "Invalid PCIe lane width!", return 0);
 188
 189         return decode_pcie_lane_width(link_width);
 190 }
 191
 192 /**
 193 * Enable voltage control
 194 *
 195 * @param    pHwMgr  the address of the powerplay hardware manager.
 196 * @return   always PP_Result_OK
 197 */
 198 int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
 199 {
 200         PP_ASSERT_WITH_CODE(
 201                 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
 202                 "Failed to enable voltage DPM during DPM Start Function!",
 203                 return 1;
 204         );
 205
 206         return 0;
 207 }
 208
 209 /**
 210 * Checks if we want to support voltage control
 211 *
 212 * @param    hwmgr  the address of the powerplay hardware manager.
 213 */
 214 static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
 215 {
 216         const struct polaris10_hwmgr *data =
 217                         (const struct polaris10_hwmgr *)(hwmgr->backend);
 218
 219         return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
 220 }
 221
 222 /**
 223 * Enable voltage control
 224 *
 225 * @param    hwmgr  the address of the powerplay hardware manager.
 226 * @return   always 0
 227 */
 228 static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
 229 {
 230         /* enable voltage control */
 231         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 232                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 233
 234         return 0;
 235 }
 236
 237 /**
 238 * Create Voltage Tables.
 239 *
 240 * @param    hwmgr  the address of the powerplay hardware manager.
 241 * @return   always 0
 242 */
 243 static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
 244 {
 245         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 246         struct phm_ppt_v1_information *table_info =
 247                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 248         int result;
 249
 250         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 251                 result = atomctrl_get_voltage_table_v3(hwmgr,
 252                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
 253                                 &(data->mvdd_voltage_table));
 254                 PP_ASSERT_WITH_CODE((0 == result),
 255                                 "Failed to retrieve MVDD table.",
 256                                 return result);
 257         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
 258                 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
 259                                 table_info->vdd_dep_on_mclk);
 260                 PP_ASSERT_WITH_CODE((0 == result),
 261                                 "Failed to retrieve SVI2 MVDD table from dependancy table.",
 262                                 return result;);
 263         }
 264
 265         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 266                 result = atomctrl_get_voltage_table_v3(hwmgr,
 267                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
 268                                 &(data->vddci_voltage_table));
 269                 PP_ASSERT_WITH_CODE((0 == result),
 270                                 "Failed to retrieve VDDCI table.",
 271                                 return result);
 272         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
 273                 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
 274                                 table_info->vdd_dep_on_mclk);
 275                 PP_ASSERT_WITH_CODE((0 == result),
 276                                 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
 277                                 return result);
 278         }
 279
 280         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 281                 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
 282                                 table_info->vddc_lookup_table);
 283                 PP_ASSERT_WITH_CODE((0 == result),
 284                                 "Failed to retrieve SVI2 VDDC table from lookup table.",
 285                                 return result);
 286         }
 287
 288         PP_ASSERT_WITH_CODE(
 289                         (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
 290                         "Too many voltage values for VDDC. Trimming to fit state table.",
 291                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
 292                                                                 &(data->vddc_voltage_table)));
 293
 294         PP_ASSERT_WITH_CODE(
 295                         (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
 296                         "Too many voltage values for VDDCI. Trimming to fit state table.",
 297                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
 298                                         &(data->vddci_voltage_table)));
 299
 300         PP_ASSERT_WITH_CODE(
 301                         (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
 302                         "Too many voltage values for MVDD. Trimming to fit state table.",
 303                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
 304                                                            &(data->mvdd_voltage_table)));
 305
 306         return 0;
 307 }
 308
 309 /**
 310 * Programs static screed detection parameters
 311 *
 312 * @param    hwmgr  the address of the powerplay hardware manager.
 313 * @return   always 0
 314 */
 315 static int polaris10_program_static_screen_threshold_parameters(
 316                                                         struct pp_hwmgr *hwmgr)
 317 {
 318         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 319
 320         /* Set static screen threshold unit */
 321         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 322                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
 323                         data->static_screen_threshold_unit);
 324         /* Set static screen threshold */
 325         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 326                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
 327                         data->static_screen_threshold);
 328
 329         return 0;
 330 }
 331
 332 /**
 333 * Setup display gap for glitch free memory clock switching.
 334 *
 335 * @param    hwmgr  the address of the powerplay hardware manager.
 336 * @return   always  0
 337 */
 338 static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
 339 {
 340         uint32_t display_gap =
 341                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 342                                         ixCG_DISPLAY_GAP_CNTL);
 343
 344         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 345                         DISP_GAP, DISPLAY_GAP_IGNORE);
 346
 347         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 348                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
 349
 350         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 351                         ixCG_DISPLAY_GAP_CNTL, display_gap);
 352
 353         return 0;
 354 }
 355
 356 /**
 357 * Programs activity state transition voting clients
 358 *
 359 * @param    hwmgr  the address of the powerplay hardware manager.
 360 * @return   always  0
 361 */
 362 static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
 363 {
 364         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 365
 366         /* Clear reset for voting clients before enabling DPM */
 367         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 368                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
 369         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 370                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
 371
 372         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 373                         ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
 374         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 375                         ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
 376         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 377                         ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
 378         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 379                         ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
 380         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 381                         ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
 382         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 383                         ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
 384         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 385                         ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
 386         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 387                         ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
 388
 389         return 0;
 390 }
 391
 392 /**
 393 * Get the location of various tables inside the FW image.
 394 *
 395 * @param    hwmgr  the address of the powerplay hardware manager.
 396 * @return   always  0
 397 */
 398 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
 399 {
 400         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 401         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
 402         uint32_t tmp;
 403         int result;
 404         bool error = false;
 405
 406         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 407                         SMU7_FIRMWARE_HEADER_LOCATION +
 408                         offsetof(SMU74_Firmware_Header, DpmTable),
 409                         &tmp, data->sram_end);
 410
 411         if (0 == result)
 412                 data->dpm_table_start = tmp;
 413
 414         error |= (0 != result);
 415
 416         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 417                         SMU7_FIRMWARE_HEADER_LOCATION +
 418                         offsetof(SMU74_Firmware_Header, SoftRegisters),
 419                         &tmp, data->sram_end);
 420
 421         if (!result) {
 422                 data->soft_regs_start = tmp;
 423                 smu_data->soft_regs_start = tmp;
 424         }
 425
 426         error |= (0 != result);
 427
 428         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 429                         SMU7_FIRMWARE_HEADER_LOCATION +
 430                         offsetof(SMU74_Firmware_Header, mcRegisterTable),
 431                         &tmp, data->sram_end);
 432
 433         if (!result)
 434                 data->mc_reg_table_start = tmp;
 435
 436         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 437                         SMU7_FIRMWARE_HEADER_LOCATION +
 438                         offsetof(SMU74_Firmware_Header, FanTable),
 439                         &tmp, data->sram_end);
 440
 441         if (!result)
 442                 data->fan_table_start = tmp;
 443
 444         error |= (0 != result);
 445
 446         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 447                         SMU7_FIRMWARE_HEADER_LOCATION +
 448                         offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
 449                         &tmp, data->sram_end);
 450
 451         if (!result)
 452                 data->arb_table_start = tmp;
 453
 454         error |= (0 != result);
 455
 456         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 457                         SMU7_FIRMWARE_HEADER_LOCATION +
 458                         offsetof(SMU74_Firmware_Header, Version),
 459                         &tmp, data->sram_end);
 460
 461         if (!result)
 462                 hwmgr->microcode_version_info.SMC = tmp;
 463
 464         error |= (0 != result);
 465
 466         return error ? -1 : 0;
 467 }
 468
 469 /* Copy one arb setting to another and then switch the active set.
 470  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
 471  */
 472 static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
 473                 uint32_t arb_src, uint32_t arb_dest)
 474 {
 475         uint32_t mc_arb_dram_timing;
 476         uint32_t mc_arb_dram_timing2;
 477         uint32_t burst_time;
 478         uint32_t mc_cg_config;
 479
 480         switch (arb_src) {
 481         case MC_CG_ARB_FREQ_F0:
 482                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
 483                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
 484                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
 485                 break;
 486         case MC_CG_ARB_FREQ_F1:
 487                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
 488                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
 489                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
 490                 break;
 491         default:
 492                 return -EINVAL;
 493         }
 494
 495         switch (arb_dest) {
 496         case MC_CG_ARB_FREQ_F0:
 497                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 498                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 499                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
 500                 break;
 501         case MC_CG_ARB_FREQ_F1:
 502                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 503                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 504                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
 505                 break;
 506         default:
 507                 return -EINVAL;
 508         }
 509
 510         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
 511         mc_cg_config |= 0x0000000F;
 512         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
 513         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
 514
 515         return 0;
 516 }
 517
 518 /**
 519 * Initial switch from ARB F0->F1
 520 *
 521 * @param    hwmgr  the address of the powerplay hardware manager.
 522 * @return   always 0
 523 * This function is to be called from the SetPowerState table.
 524 */
 525 static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
 526 {
 527         return polaris10_copy_and_switch_arb_sets(hwmgr,
 528                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
 529 }
 530
 531 static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 532 {
 533         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 534         struct phm_ppt_v1_information *table_info =
 535                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 536         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
 537         uint32_t i, max_entry;
 538
 539         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
 540                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
 541                         return -EINVAL);
 542
 543         if (data->use_pcie_performance_levels &&
 544                         !data->use_pcie_power_saving_levels) {
 545                 data->pcie_gen_power_saving = data->pcie_gen_performance;
 546                 data->pcie_lane_power_saving = data->pcie_lane_performance;
 547         } else if (!data->use_pcie_performance_levels &&
 548                         data->use_pcie_power_saving_levels) {
 549                 data->pcie_gen_performance = data->pcie_gen_power_saving;
 550                 data->pcie_lane_performance = data->pcie_lane_power_saving;
 551         }
 552
 553         phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
 554                                         SMU74_MAX_LEVELS_LINK,
 555                                         MAX_REGULAR_DPM_NUMBER);
 556
 557         if (pcie_table != NULL) {
 558                 /* max_entry is used to make sure we reserve one PCIE level
 559                  * for boot level (fix for A+A PSPP issue).
 560                  * If PCIE table from PPTable have ULV entry + 8 entries,
 561                  * then ignore the last entry.*/
 562                 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
 563                                 SMU74_MAX_LEVELS_LINK : pcie_table->count;
 564                 for (i = 1; i < max_entry; i++) {
 565                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
 566                                         get_pcie_gen_support(data->pcie_gen_cap,
 567                                                         pcie_table->entries[i].gen_speed),
 568                                         get_pcie_lane_support(data->pcie_lane_cap,
 569                                                         pcie_table->entries[i].lane_width));
 570                 }
 571                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
 572
 573                 /* Setup BIF_SCLK levels */
 574                 for (i = 0; i < max_entry; i++)
 575                         data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
 576         } else {
 577                 /* Hardcode Pcie Table */
 578                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
 579                                 get_pcie_gen_support(data->pcie_gen_cap,
 580                                                 PP_Min_PCIEGen),
 581                                 get_pcie_lane_support(data->pcie_lane_cap,
 582                                                 PP_Max_PCIELane));
 583                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
 584                                 get_pcie_gen_support(data->pcie_gen_cap,
 585                                                 PP_Min_PCIEGen),
 586                                 get_pcie_lane_support(data->pcie_lane_cap,
 587                                                 PP_Max_PCIELane));
 588                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
 589                                 get_pcie_gen_support(data->pcie_gen_cap,
 590                                                 PP_Max_PCIEGen),
 591                                 get_pcie_lane_support(data->pcie_lane_cap,
 592                                                 PP_Max_PCIELane));
 593                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
 594                                 get_pcie_gen_support(data->pcie_gen_cap,
 595                                                 PP_Max_PCIEGen),
 596                                 get_pcie_lane_support(data->pcie_lane_cap,
 597                                                 PP_Max_PCIELane));
 598                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
 599                                 get_pcie_gen_support(data->pcie_gen_cap,
 600                                                 PP_Max_PCIEGen),
 601                                 get_pcie_lane_support(data->pcie_lane_cap,
 602                                                 PP_Max_PCIELane));
 603                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
 604                                 get_pcie_gen_support(data->pcie_gen_cap,
 605                                                 PP_Max_PCIEGen),
 606                                 get_pcie_lane_support(data->pcie_lane_cap,
 607                                                 PP_Max_PCIELane));
 608
 609                 data->dpm_table.pcie_speed_table.count = 6;
 610         }
 611         /* Populate last level for boot PCIE level, but do not increment count. */
 612         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
 613                         data->dpm_table.pcie_speed_table.count,
 614                         get_pcie_gen_support(data->pcie_gen_cap,
 615                                         PP_Min_PCIEGen),
 616                         get_pcie_lane_support(data->pcie_lane_cap,
 617                                         PP_Max_PCIELane));
 618
 619         return 0;
 620 }
 621
 622 /*
 623  * This function is to initalize all DPM state tables
 624  * for SMU7 based on the dependency table.
 625  * Dynamic state patching function will then trim these
 626  * state tables to the allowed range based
 627  * on the power policy or external client requests,
 628  * such as UVD request, etc.
 629  */
 630 int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 631 {
 632         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 633         struct phm_ppt_v1_information *table_info =
 634                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 635         uint32_t i;
 636
 637         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
 638                         table_info->vdd_dep_on_sclk;
 639         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
 640                         table_info->vdd_dep_on_mclk;
 641
 642         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
 643                         "SCLK dependency table is missing. This table is mandatory",
 644                         return -EINVAL);
 645         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
 646                         "SCLK dependency table has to have is missing."
 647                         "This table is mandatory",
 648                         return -EINVAL);
 649
 650         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
 651                         "MCLK dependency table is missing. This table is mandatory",
 652                         return -EINVAL);
 653         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
 654                         "MCLK dependency table has to have is missing."
 655                         "This table is mandatory",
 656                         return -EINVAL);
 657
 658         /* clear the state table to reset everything to default */
 659         phm_reset_single_dpm_table(
 660                         &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
 661         phm_reset_single_dpm_table(
 662                         &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
 663
 664
 665         /* Initialize Sclk DPM table based on allow Sclk values */
 666         data->dpm_table.sclk_table.count = 0;
 667         for (i = 0; i < dep_sclk_table->count; i++) {
 668                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
 669                                                 dep_sclk_table->entries[i].clk) {
 670
 671                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 672                                         dep_sclk_table->entries[i].clk;
 673
 674                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
 675                                         (i == 0) ? true : false;
 676                         data->dpm_table.sclk_table.count++;
 677                 }
 678         }
 679
 680         /* Initialize Mclk DPM table based on allow Mclk values */
 681         data->dpm_table.mclk_table.count = 0;
 682         for (i = 0; i < dep_mclk_table->count; i++) {
 683                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
 684                                 [data->dpm_table.mclk_table.count - 1].value !=
 685                                                 dep_mclk_table->entries[i].clk) {
 686                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 687                                                         dep_mclk_table->entries[i].clk;
 688                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
 689                                                         (i == 0) ? true : false;
 690                         data->dpm_table.mclk_table.count++;
 691                 }
 692         }
 693
 694         /* setup PCIE gen speed levels */
 695         polaris10_setup_default_pcie_table(hwmgr);
 696
 697         /* save a copy of the default DPM table */
 698         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 699                         sizeof(struct polaris10_dpm_table));
 700
 701         return 0;
 702 }
 703
 704 uint8_t convert_to_vid(uint16_t vddc)
 705 {
 706         return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
 707 }
 708
 709 /**
 710  * Mvdd table preparation for SMC.
 711  *
 712  * @param    *hwmgr The address of the hardware manager.
 713  * @param    *table The SMC DPM table structure to be populated.
 714  * @return   0
 715  */
 716 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
 717                         SMU74_Discrete_DpmTable *table)
 718 {
 719         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 720         uint32_t count, level;
 721
 722         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 723                 count = data->mvdd_voltage_table.count;
 724                 if (count > SMU_MAX_SMIO_LEVELS)
 725                         count = SMU_MAX_SMIO_LEVELS;
 726                 for (level = 0; level < count; level++) {
 727                         table->SmioTable2.Pattern[level].Voltage =
 728                                 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
 729                         /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
 730                         table->SmioTable2.Pattern[level].Smio =
 731                                 (uint8_t) level;
 732                         table->Smio[level] |=
 733                                 data->mvdd_voltage_table.entries[level].smio_low;
 734                 }
 735                 table->SmioMask2 = data->vddci_voltage_table.mask_low;
 736
 737                 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
 738         }
 739
 740         return 0;
 741 }
 742
 743 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
 744                                         struct SMU74_Discrete_DpmTable *table)
 745 {
 746         uint32_t count, level;
 747         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 748
 749         count = data->vddci_voltage_table.count;
 750
 751         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 752                 if (count > SMU_MAX_SMIO_LEVELS)
 753                         count = SMU_MAX_SMIO_LEVELS;
 754                 for (level = 0; level < count; ++level) {
 755                         table->SmioTable1.Pattern[level].Voltage =
 756                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
 757                         table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
 758
 759                         table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
 760                 }
 761         }
 762
 763         table->SmioMask1 = data->vddci_voltage_table.mask_low;
 764
 765         return 0;
 766 }
 767
 768 /**
 769 * Preparation of vddc and vddgfx CAC tables for SMC.
 770 *
 771 * @param    hwmgr  the address of the hardware manager
 772 * @param    table  the SMC DPM table structure to be populated
 773 * @return   always 0
 774 */
 775 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
 776                 struct SMU74_Discrete_DpmTable *table)
 777 {
 778         uint32_t count;
 779         uint8_t index;
 780         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 781         struct phm_ppt_v1_information *table_info =
 782                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 783         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
 784                         table_info->vddc_lookup_table;
 785         /* tables is already swapped, so in order to use the value from it,
 786          * we need to swap it back.
 787          * We are populating vddc CAC data to BapmVddc table
 788          * in split and merged mode
 789          */
 790         for (count = 0; count < lookup_table->count; count++) {
 791                 index = phm_get_voltage_index(lookup_table,
 792                                 data->vddc_voltage_table.entries[count].value);
 793                 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
 794                 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
 795                 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
 796         }
 797
 798         return 0;
 799 }
 800
 801 /**
 802 * Preparation of voltage tables for SMC.
 803 *
 804 * @param    hwmgr   the address of the hardware manager
 805 * @param    table   the SMC DPM table structure to be populated
 806 * @return   always  0
 807 */
 808
 809 int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
 810                 struct SMU74_Discrete_DpmTable *table)
 811 {
 812         polaris10_populate_smc_vddci_table(hwmgr, table);
 813         polaris10_populate_smc_mvdd_table(hwmgr, table);
 814         polaris10_populate_cac_table(hwmgr, table);
 815
 816         return 0;
 817 }
 818
 819 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
 820                 struct SMU74_Discrete_Ulv *state)
 821 {
 822         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 823         struct phm_ppt_v1_information *table_info =
 824                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 825
 826         state->CcPwrDynRm = 0;
 827         state->CcPwrDynRm1 = 0;
 828
 829         state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
 830         state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
 831                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
 832
 833         state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
 834
 835         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
 836         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
 837         CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
 838
 839         return 0;
 840 }
 841
 842 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
 843                 struct SMU74_Discrete_DpmTable *table)
 844 {
 845         return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
 846 }
 847
 848 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
 849                 struct SMU74_Discrete_DpmTable *table)
 850 {
 851         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 852         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
 853         int i;
 854
 855         /* Index (dpm_table->pcie_speed_table.count)
 856          * is reserved for PCIE boot level. */
 857         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
 858                 table->LinkLevel[i].PcieGenSpeed  =
 859                                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
 860                 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
 861                                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
 862                 table->LinkLevel[i].EnabledForActivity = 1;
 863                 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
 864                 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
 865                 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
 866         }
 867
 868         data->smc_state_table.LinkLevelCount =
 869                         (uint8_t)dpm_table->pcie_speed_table.count;
 870         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
 871                         phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
 872
 873         return 0;
 874 }
 875
 876 static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
 877 {
 878         uint32_t reference_clock, tmp;
 879         struct cgs_display_info info = {0};
 880         struct cgs_mode_info mode_info;
 881
 882         info.mode_info = &mode_info;
 883
 884         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
 885
 886         if (tmp)
 887                 return TCLK;
 888
 889         cgs_get_active_displays_info(hwmgr->device, &info);
 890         reference_clock = mode_info.ref_clock;
 891
 892         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
 893
 894         if (0 != tmp)
 895                 return reference_clock / 4;
 896
 897         return reference_clock;
 898 }
 899
 900 /**
 901 * Calculates the SCLK dividers using the provided engine clock
 902 *
 903 * @param    hwmgr  the address of the hardware manager
 904 * @param    clock  the engine clock to use to populate the structure
 905 * @param    sclk   the SMC SCLK structure to be populated
 906 */
 907 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 908                 uint32_t clock, SMU_SclkSetting *sclk_setting)
 909 {
 910         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 911         const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
 912         struct pp_atomctrl_clock_dividers_ai dividers;
 913
 914         uint32_t ref_clock;
 915         uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
 916         uint8_t i;
 917         int result;
 918         uint64_t temp;
 919
 920         sclk_setting->SclkFrequency = clock;
 921         /* get the engine clock dividers for this clock value */
 922         result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
 923         if (result == 0) {
 924                 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
 925                 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
 926                 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
 927                 sclk_setting->PllRange = dividers.ucSclkPllRange;
 928                 sclk_setting->Sclk_slew_rate = 0x400;
 929                 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
 930                 sclk_setting->Pcc_down_slew_rate = 0xffff;
 931                 sclk_setting->SSc_En = dividers.ucSscEnable;
 932                 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
 933                 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
 934                 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
 935                 return result;
 936         }
 937
 938         ref_clock = polaris10_get_xclk(hwmgr);
 939
 940         for (i = 0; i < NUM_SCLK_RANGE; i++) {
 941                 if (clock > data->range_table[i].trans_lower_frequency
 942                 && clock <= data->range_table[i].trans_upper_frequency) {
 943                         sclk_setting->PllRange = i;
 944                         break;
 945                 }
 946         }
 947
 948         sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 949         temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 950         temp <<= 0x10;
 951         do_div(temp, ref_clock);
 952         sclk_setting->Fcw_frac = temp & 0xffff;
 953
 954         pcc_target_percent = 10; /*  Hardcode 10% for now. */
 955         pcc_target_freq = clock - (clock * pcc_target_percent / 100);
 956         sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 957
 958         ss_target_percent = 2; /*  Hardcode 2% for now. */
 959         sclk_setting->SSc_En = 0;
 960         if (ss_target_percent) {
 961                 sclk_setting->SSc_En = 1;
 962                 ss_target_freq = clock - (clock * ss_target_percent / 100);
 963                 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 964                 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 965                 temp <<= 0x10;
 966                 do_div(temp, ref_clock);
 967                 sclk_setting->Fcw1_frac = temp & 0xffff;
 968         }
 969
 970         return 0;
 971 }
 972
 973 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
 974                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
 975                 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
 976 {
 977         uint32_t i;
 978         uint16_t vddci;
 979         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 980
 981         *voltage = *mvdd = 0;
 982
 983         /* clock - voltage dependency table is empty table */
 984         if (dep_table->count == 0)
 985                 return -EINVAL;
 986
 987         for (i = 0; i < dep_table->count; i++) {
 988                 /* find first sclk bigger than request */
 989                 if (dep_table->entries[i].clk >= clock) {
 990                         *voltage |= (dep_table->entries[i].vddc *
 991                                         VOLTAGE_SCALE) << VDDC_SHIFT;
 992                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
 993                                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
 994                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
 995                         else if (dep_table->entries[i].vddci)
 996                                 *voltage |= (dep_table->entries[i].vddci *
 997                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
 998                         else {
 999                                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1000                                                 (dep_table->entries[i].vddc -
1001                                                                 (uint16_t)data->vddc_vddci_delta));
1002                                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1003                         }
1004
1005                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1006                                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1007                                         VOLTAGE_SCALE;
1008                         else if (dep_table->entries[i].mvdd)
1009                                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1010                                         VOLTAGE_SCALE;
1011
1012                         *voltage |= 1 << PHASES_SHIFT;
1013                         return 0;
1014                 }
1015         }
1016
1017         /* sclk is bigger than max sclk in the dependence table */
1018         *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1019
1020         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1021                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1022                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1023         else if (dep_table->entries[i-1].vddci) {
1024                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1025                                 (dep_table->entries[i].vddc -
1026                                                 (uint16_t)data->vddc_vddci_delta));
1027                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1028         }
1029
1030         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1031                 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1032         else if (dep_table->entries[i].mvdd)
1033                 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1034
1035         return 0;
1036 }
1037
1038 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
1039 { {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
1040   {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1041   {VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
1042   {VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
1043   {VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
1044   {VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
1045   {VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
1046   {VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
1047
1048 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
1049 {
1050         uint32_t i, ref_clk;
1051         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1052         SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
1053         struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1054
1055         ref_clk = polaris10_get_xclk(hwmgr);
1056
1057         if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1058                 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1059                         table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1060                         table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1061                         table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1062
1063                         table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1064                         table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1065
1066                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1067                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1068                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1069                 }
1070                 return;
1071         }
1072
1073         for (i = 0; i < NUM_SCLK_RANGE; i++) {
1074
1075                 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1076                 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1077
1078                 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1079                 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1080                 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1081
1082                 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1083                 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1084
1085                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1086                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1087                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1088         }
1089 }
1090
1091 /**
1092 * Populates single SMC SCLK structure using the provided engine clock
1093 *
1094 * @param    hwmgr      the address of the hardware manager
1095 * @param    clock the engine clock to use to populate the structure
1096 * @param    sclk        the SMC SCLK structure to be populated
1097 */
1098
1099 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1100                 uint32_t clock, uint16_t sclk_al_threshold,
1101                 struct SMU74_Discrete_GraphicsLevel *level)
1102 {
1103         int result, i, temp;
1104         /* PP_Clocks minClocks; */
1105         uint32_t mvdd;
1106         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1107         struct phm_ppt_v1_information *table_info =
1108                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1109         SMU_SclkSetting curr_sclk_setting = { 0 };
1110
1111         result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
1112
1113         /* populate graphics levels */
1114         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1115                         table_info->vdd_dep_on_sclk, clock,
1116                         &level->MinVoltage, &mvdd);
1117
1118         PP_ASSERT_WITH_CODE((0 == result),
1119                         "can not find VDDC voltage value for "
1120                         "VDDC engine clock dependency table",
1121                         return result);
1122         level->ActivityLevel = sclk_al_threshold;
1123
1124         level->CcPwrDynRm = 0;
1125         level->CcPwrDynRm1 = 0;
1126         level->EnabledForActivity = 0;
1127         level->EnabledForThrottle = 1;
1128         level->UpHyst = 10;
1129         level->DownHyst = 0;
1130         level->VoltageDownHyst = 0;
1131         level->PowerThrottle = 0;
1132
1133         /*
1134         * TODO: get minimum clocks from dal configaration
1135         * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1136         */
1137         /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1138
1139         /* get level->DeepSleepDivId
1140         if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1141                 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1142         */
1143         PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0);
1144         for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1145                 temp = clock >> i;
1146
1147                 if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0)
1148                         break;
1149         }
1150
1151         level->DeepSleepDivId = i;
1152
1153         /* Default to slow, highest DPM level will be
1154          * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1155          */
1156         if (data->update_up_hyst)
1157                 level->UpHyst = (uint8_t)data->up_hyst;
1158         if (data->update_down_hyst)
1159                 level->DownHyst = (uint8_t)data->down_hyst;
1160
1161         level->SclkSetting = curr_sclk_setting;
1162
1163         CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1164         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1165         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1166         CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1167         CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1168         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1169         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1170         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1171         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1172         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1173         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1174         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1175         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1176         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1177         return 0;
1178 }
1179
1180 /**
1181 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1182 *
1183 * @param    hwmgr      the address of the hardware manager
1184 */
1185 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1186 {
1187         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1188         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1189         struct phm_ppt_v1_information *table_info =
1190                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1191         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1192         uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1193         int result = 0;
1194         uint32_t array = data->dpm_table_start +
1195                         offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1196         uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1197                         SMU74_MAX_LEVELS_GRAPHICS;
1198         struct SMU74_Discrete_GraphicsLevel *levels =
1199                         data->smc_state_table.GraphicsLevel;
1200         uint32_t i, max_entry;
1201         uint8_t hightest_pcie_level_enabled = 0,
1202                 lowest_pcie_level_enabled = 0,
1203                 mid_pcie_level_enabled = 0,
1204                 count = 0;
1205
1206         polaris10_get_sclk_range_table(hwmgr);
1207
1208         for (i = 0; i < dpm_table->sclk_table.count; i++) {
1209
1210                 result = polaris10_populate_single_graphic_level(hwmgr,
1211                                 dpm_table->sclk_table.dpm_levels[i].value,
1212                                 (uint16_t)data->activity_target[i],
1213                                 &(data->smc_state_table.GraphicsLevel[i]));
1214                 if (result)
1215                         return result;
1216
1217                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1218                 if (i > 1)
1219                         levels[i].DeepSleepDivId = 0;
1220         }
1221         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1222                                         PHM_PlatformCaps_SPLLShutdownSupport))
1223                 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1224
1225         data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1226         data->smc_state_table.GraphicsDpmLevelCount =
1227                         (uint8_t)dpm_table->sclk_table.count;
1228         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1229                         phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1230
1231
1232         if (pcie_table != NULL) {
1233                 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1234                                 "There must be 1 or more PCIE levels defined in PPTable.",
1235                                 return -EINVAL);
1236                 max_entry = pcie_entry_cnt - 1;
1237                 for (i = 0; i < dpm_table->sclk_table.count; i++)
1238                         levels[i].pcieDpmLevel =
1239                                         (uint8_t) ((i < max_entry) ? i : max_entry);
1240         } else {
1241                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1242                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1243                                                 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1244                         hightest_pcie_level_enabled++;
1245
1246                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1247                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1248                                                 (1 << lowest_pcie_level_enabled)) == 0))
1249                         lowest_pcie_level_enabled++;
1250
1251                 while ((count < hightest_pcie_level_enabled) &&
1252                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1253                                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1254                         count++;
1255
1256                 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1257                                 hightest_pcie_level_enabled ?
1258                                                 (lowest_pcie_level_enabled + 1 + count) :
1259                                                 hightest_pcie_level_enabled;
1260
1261                 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1262                 for (i = 2; i < dpm_table->sclk_table.count; i++)
1263                         levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1264
1265                 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1266                 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1267
1268                 /* set pcieDpmLevel to mid_pcie_level_enabled */
1269                 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1270         }
1271         /* level count will send to smc once at init smc table and never change */
1272         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1273                         (uint32_t)array_size, data->sram_end);
1274
1275         return result;
1276 }
1277
1278 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1279                 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1280 {
1281         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1282         struct phm_ppt_v1_information *table_info =
1283                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1284         int result = 0;
1285         struct cgs_display_info info = {0, 0, NULL};
1286
1287         cgs_get_active_displays_info(hwmgr->device, &info);
1288
1289         if (table_info->vdd_dep_on_mclk) {
1290                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1291                                 table_info->vdd_dep_on_mclk, clock,
1292                                 &mem_level->MinVoltage, &mem_level->MinMvdd);
1293                 PP_ASSERT_WITH_CODE((0 == result),
1294                                 "can not find MinVddc voltage value from memory "
1295                                 "VDDC voltage dependency table", return result);
1296         }
1297
1298         mem_level->MclkFrequency = clock;
1299         mem_level->EnabledForThrottle = 1;
1300         mem_level->EnabledForActivity = 0;
1301         mem_level->UpHyst = 0;
1302         mem_level->DownHyst = 100;
1303         mem_level->VoltageDownHyst = 0;
1304         mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1305         mem_level->StutterEnable = false;
1306
1307         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1308
1309         data->display_timing.num_existing_displays = info.display_count;
1310
1311         if ((data->mclk_stutter_mode_threshold) &&
1312                 (clock <= data->mclk_stutter_mode_threshold) &&
1313                 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1314                                 STUTTER_ENABLE) & 0x1))
1315                 mem_level->StutterEnable = true;
1316
1317         if (!result) {
1318                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1319                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1320                 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1321                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1322         }
1323         return result;
1324 }
1325
1326 /**
1327 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1328 *
1329 * @param    hwmgr      the address of the hardware manager
1330 */
1331 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1332 {
1333         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1334         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1335         int result;
1336         /* populate MCLK dpm table to SMU7 */
1337         uint32_t array = data->dpm_table_start +
1338                         offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1339         uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1340                         SMU74_MAX_LEVELS_MEMORY;
1341         struct SMU74_Discrete_MemoryLevel *levels =
1342                         data->smc_state_table.MemoryLevel;
1343         uint32_t i;
1344
1345         for (i = 0; i < dpm_table->mclk_table.count; i++) {
1346                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1347                                 "can not populate memory level as memory clock is zero",
1348                                 return -EINVAL);
1349                 result = polaris10_populate_single_memory_level(hwmgr,
1350                                 dpm_table->mclk_table.dpm_levels[i].value,
1351                                 &levels[i]);
1352                 if (i == dpm_table->mclk_table.count - 1) {
1353                         levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1354                         levels[i].EnabledForActivity = 1;
1355                 }
1356                 if (result)
1357                         return result;
1358         }
1359
1360         /* in order to prevent MC activity from stutter mode to push DPM up.
1361          * the UVD change complements this by putting the MCLK in
1362          * a higher state by default such that we are not effected by
1363          * up threshold or and MCLK DPM latency.
1364          */
1365         levels[0].ActivityLevel = 0x1f;
1366         CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1367
1368         data->smc_state_table.MemoryDpmLevelCount =
1369                         (uint8_t)dpm_table->mclk_table.count;
1370         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1371                         phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1372
1373         /* level count will send to smc once at init smc table and never change */
1374         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1375                         (uint32_t)array_size, data->sram_end);
1376
1377         return result;
1378 }
1379
1380 /**
1381 * Populates the SMC MVDD structure using the provided memory clock.
1382 *
1383 * @param    hwmgr      the address of the hardware manager
1384 * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
1385 * @param    voltage     the SMC VOLTAGE structure to be populated
1386 */
1387 int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1388                 uint32_t mclk, SMIO_Pattern *smio_pat)
1389 {
1390         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1391         struct phm_ppt_v1_information *table_info =
1392                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1393         uint32_t i = 0;
1394
1395         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1396                 /* find mvdd value which clock is more than request */
1397                 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1398                         if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1399                                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1400                                 break;
1401                         }
1402                 }
1403                 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1404                                 "MVDD Voltage is outside the supported range.",
1405                                 return -EINVAL);
1406         } else
1407                 return -EINVAL;
1408
1409         return 0;
1410 }
1411
1412 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1413                 SMU74_Discrete_DpmTable *table)
1414 {
1415         int result = 0;
1416         uint32_t sclk_frequency;
1417         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1418         struct phm_ppt_v1_information *table_info =
1419                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1420         SMIO_Pattern vol_level;
1421         uint32_t mvdd;
1422         uint16_t us_mvdd;
1423
1424         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1425
1426         if (!data->sclk_dpm_key_disabled) {
1427                 /* Get MinVoltage and Frequency from DPM0,
1428                  * already converted to SMC_UL */
1429                 sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1430                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1431                                 table_info->vdd_dep_on_sclk,
1432                                 table->ACPILevel.SclkFrequency,
1433                                 &table->ACPILevel.MinVoltage, &mvdd);
1434                 PP_ASSERT_WITH_CODE((0 == result),
1435                                 "Cannot find ACPI VDDC voltage value "
1436                                 "in Clock Dependency Table", );
1437         } else {
1438                 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1439                 table->ACPILevel.MinVoltage =
1440                                 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1441         }
1442
1443         result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
1444         PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1445
1446         table->ACPILevel.DeepSleepDivId = 0;
1447         table->ACPILevel.CcPwrDynRm = 0;
1448         table->ACPILevel.CcPwrDynRm1 = 0;
1449
1450         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1451         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1452         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1453         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1454
1455         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1456         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1457         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1458         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1459         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1460         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1461         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1462         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1463         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1464         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1465
1466         if (!data->mclk_dpm_key_disabled) {
1467                 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1468                 table->MemoryACPILevel.MclkFrequency =
1469                                 data->dpm_table.mclk_table.dpm_levels[0].value;
1470                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1471                                 table_info->vdd_dep_on_mclk,
1472                                 table->MemoryACPILevel.MclkFrequency,
1473                                 &table->MemoryACPILevel.MinVoltage, &mvdd);
1474                 PP_ASSERT_WITH_CODE((0 == result),
1475                                 "Cannot find ACPI VDDCI voltage value "
1476                                 "in Clock Dependency Table",
1477                                 );
1478         } else {
1479                 table->MemoryACPILevel.MclkFrequency =
1480                                 data->vbios_boot_state.mclk_bootup_value;
1481                 table->MemoryACPILevel.MinVoltage =
1482                                 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1483         }
1484
1485         us_mvdd = 0;
1486         if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1487                         (data->mclk_dpm_key_disabled))
1488                 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1489         else {
1490                 if (!polaris10_populate_mvdd_value(hwmgr,
1491                                 data->dpm_table.mclk_table.dpm_levels[0].value,
1492                                 &vol_level))
1493                         us_mvdd = vol_level.Voltage;
1494         }
1495
1496         if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1497                 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1498         else
1499                 table->MemoryACPILevel.MinMvdd = 0;
1500
1501         table->MemoryACPILevel.StutterEnable = false;
1502
1503         table->MemoryACPILevel.EnabledForThrottle = 0;
1504         table->MemoryACPILevel.EnabledForActivity = 0;
1505         table->MemoryACPILevel.UpHyst = 0;
1506         table->MemoryACPILevel.DownHyst = 100;
1507         table->MemoryACPILevel.VoltageDownHyst = 0;
1508         table->MemoryACPILevel.ActivityLevel =
1509                         PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1510
1511         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1512         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1513
1514         return result;
1515 }
1516
1517 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1518                 SMU74_Discrete_DpmTable *table)
1519 {
1520         int result = -EINVAL;
1521         uint8_t count;
1522         struct pp_atomctrl_clock_dividers_vi dividers;
1523         struct phm_ppt_v1_information *table_info =
1524                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1525         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1526                         table_info->mm_dep_table;
1527         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1528
1529         table->VceLevelCount = (uint8_t)(mm_table->count);
1530         table->VceBootLevel = 0;
1531
1532         for (count = 0; count < table->VceLevelCount; count++) {
1533                 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1534                 table->VceLevel[count].MinVoltage = 0;
1535                 table->VceLevel[count].MinVoltage |=
1536                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1537                 table->VceLevel[count].MinVoltage |=
1538                                 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
1539                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1540                 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1541
1542                 /*retrieve divider value for VBIOS */
1543                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1544                                 table->VceLevel[count].Frequency, &dividers);
1545                 PP_ASSERT_WITH_CODE((0 == result),
1546                                 "can not find divide id for VCE engine clock",
1547                                 return result);
1548
1549                 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1550
1551                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1552                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1553         }
1554         return result;
1555 }
1556
1557 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1558                 SMU74_Discrete_DpmTable *table)
1559 {
1560         int result = -EINVAL;
1561         uint8_t count;
1562         struct pp_atomctrl_clock_dividers_vi dividers;
1563         struct phm_ppt_v1_information *table_info =
1564                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1565         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1566                         table_info->mm_dep_table;
1567         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1568
1569         table->SamuBootLevel = 0;
1570         table->SamuLevelCount = (uint8_t)(mm_table->count);
1571
1572         for (count = 0; count < table->SamuLevelCount; count++) {
1573                 /* not sure whether we need evclk or not */
1574                 table->SamuLevel[count].MinVoltage = 0;
1575                 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1576                 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1577                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1578                 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1579                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1580                 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1581
1582                 /* retrieve divider value for VBIOS */
1583                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1584                                 table->SamuLevel[count].Frequency, &dividers);
1585                 PP_ASSERT_WITH_CODE((0 == result),
1586                                 "can not find divide id for samu clock", return result);
1587
1588                 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1589
1590                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1591                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1592         }
1593         return result;
1594 }
1595
1596 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1597                 int32_t eng_clock, int32_t mem_clock,
1598                 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1599 {
1600         uint32_t dram_timing;
1601         uint32_t dram_timing2;
1602         uint32_t burst_time;
1603         int result;
1604
1605         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1606                         eng_clock, mem_clock);
1607         PP_ASSERT_WITH_CODE(result == 0,
1608                         "Error calling VBIOS to set DRAM_TIMING.", return result);
1609
1610         dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1611         dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1612         burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1613
1614
1615         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
1616         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1617         arb_regs->McArbBurstTime   = (uint8_t)burst_time;
1618
1619         return 0;
1620 }
1621
1622 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1623 {
1624         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1625         struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1626         uint32_t i, j;
1627         int result = 0;
1628
1629         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1630                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1631                         result = polaris10_populate_memory_timing_parameters(hwmgr,
1632                                         data->dpm_table.sclk_table.dpm_levels[i].value,
1633                                         data->dpm_table.mclk_table.dpm_levels[j].value,
1634                                         &arb_regs.entries[i][j]);
1635                         if (result == 0)
1636                                 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1637                         if (result != 0)
1638                                 return result;
1639                 }
1640         }
1641
1642         result = polaris10_copy_bytes_to_smc(
1643                         hwmgr->smumgr,
1644                         data->arb_table_start,
1645                         (uint8_t *)&arb_regs,
1646                         sizeof(SMU74_Discrete_MCArbDramTimingTable),
1647                         data->sram_end);
1648         return result;
1649 }
1650
1651 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1652                 struct SMU74_Discrete_DpmTable *table)
1653 {
1654         int result = -EINVAL;
1655         uint8_t count;
1656         struct pp_atomctrl_clock_dividers_vi dividers;
1657         struct phm_ppt_v1_information *table_info =
1658                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1659         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1660                         table_info->mm_dep_table;
1661         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1662
1663         table->UvdLevelCount = (uint8_t)(mm_table->count);
1664         table->UvdBootLevel = 0;
1665
1666         for (count = 0; count < table->UvdLevelCount; count++) {
1667                 table->UvdLevel[count].MinVoltage = 0;
1668                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1669                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1670                 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1671                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1672                 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1673                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1674                 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1675
1676                 /* retrieve divider value for VBIOS */
1677                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1678                                 table->UvdLevel[count].VclkFrequency, &dividers);
1679                 PP_ASSERT_WITH_CODE((0 == result),
1680                                 "can not find divide id for Vclk clock", return result);
1681
1682                 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1683
1684                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1685                                 table->UvdLevel[count].DclkFrequency, &dividers);
1686                 PP_ASSERT_WITH_CODE((0 == result),
1687                                 "can not find divide id for Dclk clock", return result);
1688
1689                 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1690
1691                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1692                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1693                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1694
1695         }
1696         return result;
1697 }
1698
1699 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1700                 struct SMU74_Discrete_DpmTable *table)
1701 {
1702         int result = 0;
1703         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1704
1705         table->GraphicsBootLevel = 0;
1706         table->MemoryBootLevel = 0;
1707
1708         /* find boot level from dpm table */
1709         result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1710                         data->vbios_boot_state.sclk_bootup_value,
1711                         (uint32_t *)&(table->GraphicsBootLevel));
1712
1713         result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1714                         data->vbios_boot_state.mclk_bootup_value,
1715                         (uint32_t *)&(table->MemoryBootLevel));
1716
1717         table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
1718                         VOLTAGE_SCALE;
1719         table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1720                         VOLTAGE_SCALE;
1721         table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
1722                         VOLTAGE_SCALE;
1723
1724         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1725         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1726         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1727
1728         return 0;
1729 }
1730
1731
1732 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1733 {
1734         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1735         struct phm_ppt_v1_information *table_info =
1736                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1737         uint8_t count, level;
1738
1739         count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1740
1741         for (level = 0; level < count; level++) {
1742                 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1743                                 data->vbios_boot_state.sclk_bootup_value) {
1744                         data->smc_state_table.GraphicsBootLevel = level;
1745                         break;
1746                 }
1747         }
1748
1749         count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1750         for (level = 0; level < count; level++) {
1751                 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1752                                 data->vbios_boot_state.mclk_bootup_value) {
1753                         data->smc_state_table.MemoryBootLevel = level;
1754                         break;
1755                 }
1756         }
1757
1758         return 0;
1759 }
1760
1761 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1762 {
1763         uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
1764                         volt_with_cks, value;
1765         uint16_t clock_freq_u16;
1766         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1767         uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
1768                         volt_offset = 0;
1769         struct phm_ppt_v1_information *table_info =
1770                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1771         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1772                         table_info->vdd_dep_on_sclk;
1773
1774         stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1775
1776         /* Read SMU_Eefuse to read and calculate RO and determine
1777          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1778          */
1779         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1780                         ixSMU_EFUSE_0 + (146 * 4));
1781         efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1782                         ixSMU_EFUSE_0 + (148 * 4));
1783         efuse &= 0xFF000000;
1784         efuse = efuse >> 24;
1785         efuse2 &= 0xF;
1786
1787         if (efuse2 == 1)
1788                 ro = (2300 - 1350) * efuse / 255 + 1350;
1789         else
1790                 ro = (2500 - 1000) * efuse / 255 + 1000;
1791
1792         if (ro >= 1660)
1793                 type = 0;
1794         else
1795                 type = 1;
1796
1797         /* Populate Stretch amount */
1798         data->smc_state_table.ClockStretcherAmount = stretch_amount;
1799
1800         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1801         for (i = 0; i < sclk_table->count; i++) {
1802                 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1803                                 sclk_table->entries[i].cks_enable << i;
1804                 volt_without_cks = (uint32_t)((14041 *
1805                         (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
1806                         (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
1807                 volt_with_cks = (uint32_t)((13946 *
1808                         (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
1809                         (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
1810                 if (volt_without_cks >= volt_with_cks)
1811                         volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1812                                         sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1813                 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1814         }
1815
1816         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1817                         STRETCH_ENABLE, 0x0);
1818         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1819                         masterReset, 0x1);
1820         /* PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, staticEnable, 0x1); */
1821         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1822                         masterReset, 0x0);
1823
1824         /* Populate CKS Lookup Table */
1825         if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1826                 stretch_amount2 = 0;
1827         else if (stretch_amount == 3 || stretch_amount == 4)
1828                 stretch_amount2 = 1;
1829         else {
1830                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1831                                 PHM_PlatformCaps_ClockStretcher);
1832                 PP_ASSERT_WITH_CODE(false,
1833                                 "Stretch Amount in PPTable not supported\n",
1834                                 return -EINVAL);
1835         }
1836
1837         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1838                         ixPWR_CKS_CNTL);
1839         value &= 0xFFC2FF87;
1840         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
1841                         polaris10_clock_stretcher_lookup_table[stretch_amount2][0];
1842         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
1843                         polaris10_clock_stretcher_lookup_table[stretch_amount2][1];
1844         clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
1845                         GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100);
1846         if (polaris10_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16
1847         && polaris10_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) {
1848                 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
1849                 value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
1850                 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
1851                 value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
1852                 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
1853                 value |= (polaris10_clock_stretch_amount_conversion
1854                                 [polaris10_clock_stretcher_lookup_table[stretch_amount2][3]]
1855                                  [stretch_amount]) << 3;
1856         }
1857         CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq);
1858         CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq);
1859         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
1860                         polaris10_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
1861         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
1862                         (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
1863
1864         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1865                         ixPWR_CKS_CNTL, value);
1866
1867         /* Populate DDT Lookup Table */
1868         for (i = 0; i < 4; i++) {
1869                 /* Assign the minimum and maximum VID stored
1870                  * in the last row of Clock Stretcher Voltage Table.
1871                  */
1872                 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID =
1873                                 (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][2];
1874                 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID =
1875                                 (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][3];
1876                 /* Loop through each SCLK and check the frequency
1877                  * to see if it lies within the frequency for clock stretcher.
1878                  */
1879                 for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
1880                         cks_setting = 0;
1881                         clock_freq = PP_SMC_TO_HOST_UL(
1882                                         data->smc_state_table.GraphicsLevel[j].SclkSetting.SclkFrequency);
1883                         /* Check the allowed frequency against the sclk level[j].
1884                          *  Sclk's endianness has already been converted,
1885                          *  and it's in 10Khz unit,
1886                          *  as opposed to Data table, which is in Mhz unit.
1887                          */
1888                         if (clock_freq >= (polaris10_clock_stretcher_ddt_table[type][i][0]) * 100) {
1889                                 cks_setting |= 0x2;
1890                                 if (clock_freq < (polaris10_clock_stretcher_ddt_table[type][i][1]) * 100)
1891                                         cks_setting |= 0x1;
1892                         }
1893                         data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting
1894                                                         |= cks_setting << (j * 2);
1895                 }
1896                 CONVERT_FROM_HOST_TO_SMC_US(
1897                         data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting);
1898         }
1899
1900         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1901         value &= 0xFFFFFFFE;
1902         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1903
1904         return 0;
1905 }
1906
1907 /**
1908 * Populates the SMC VRConfig field in DPM table.
1909 *
1910 * @param    hwmgr   the address of the hardware manager
1911 * @param    table   the SMC DPM table structure to be populated
1912 * @return   always 0
1913 */
1914 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1915                 struct SMU74_Discrete_DpmTable *table)
1916 {
1917         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1918         uint16_t config;
1919
1920         config = VR_MERGED_WITH_VDDC;
1921         table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1922
1923         /* Set Vddc Voltage Controller */
1924         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1925                 config = VR_SVI2_PLANE_1;
1926                 table->VRConfig |= config;
1927         } else {
1928                 PP_ASSERT_WITH_CODE(false,
1929                                 "VDDC should be on SVI2 control in merged mode!",
1930                                 );
1931         }
1932         /* Set Vddci Voltage Controller */
1933         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1934                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
1935                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1936         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1937                 config = VR_SMIO_PATTERN_1;
1938                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1939         } else {
1940                 config = VR_STATIC_VOLTAGE;
1941                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1942         }
1943         /* Set Mvdd Voltage Controller */
1944         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1945                 config = VR_SVI2_PLANE_2;
1946                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1947         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1948                 config = VR_SMIO_PATTERN_2;
1949                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1950         } else {
1951                 config = VR_STATIC_VOLTAGE;
1952                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1953         }
1954
1955         return 0;
1956 }
1957
1958 /**
1959 * Initializes the SMC table and uploads it
1960 *
1961 * @param    hwmgr  the address of the powerplay hardware manager.
1962 * @return   always 0
1963 */
1964 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1965 {
1966         int result;
1967         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1968         struct phm_ppt_v1_information *table_info =
1969                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1970         struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1971         const struct polaris10_ulv_parm *ulv = &(data->ulv);
1972         uint8_t i;
1973         struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1974         pp_atomctrl_clock_dividers_vi dividers;
1975
1976         result = polaris10_setup_default_dpm_tables(hwmgr);
1977         PP_ASSERT_WITH_CODE(0 == result,
1978                         "Failed to setup default DPM tables!", return result);
1979
1980         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
1981                 polaris10_populate_smc_voltage_tables(hwmgr, table);
1982
1983         table->SystemFlags = 0;
1984         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1985                         PHM_PlatformCaps_AutomaticDCTransition))
1986                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1987
1988         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1989                         PHM_PlatformCaps_StepVddc))
1990                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1991
1992         if (data->is_memory_gddr5)
1993                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1994
1995         if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
1996                 result = polaris10_populate_ulv_state(hwmgr, table);
1997                 PP_ASSERT_WITH_CODE(0 == result,
1998                                 "Failed to initialize ULV state!", return result);
1999                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2000                                 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
2001         }
2002
2003         result = polaris10_populate_smc_link_level(hwmgr, table);
2004         PP_ASSERT_WITH_CODE(0 == result,
2005                         "Failed to initialize Link Level!", return result);
2006
2007         result = polaris10_populate_all_graphic_levels(hwmgr);
2008         PP_ASSERT_WITH_CODE(0 == result,
2009                         "Failed to initialize Graphics Level!", return result);
2010
2011         result = polaris10_populate_all_memory_levels(hwmgr);
2012         PP_ASSERT_WITH_CODE(0 == result,
2013                         "Failed to initialize Memory Level!", return result);
2014
2015         result = polaris10_populate_smc_acpi_level(hwmgr, table);
2016         PP_ASSERT_WITH_CODE(0 == result,
2017                         "Failed to initialize ACPI Level!", return result);
2018
2019         result = polaris10_populate_smc_vce_level(hwmgr, table);
2020         PP_ASSERT_WITH_CODE(0 == result,
2021                         "Failed to initialize VCE Level!", return result);
2022
2023         result = polaris10_populate_smc_samu_level(hwmgr, table);
2024         PP_ASSERT_WITH_CODE(0 == result,
2025                         "Failed to initialize SAMU Level!", return result);
2026
2027         /* Since only the initial state is completely set up at this point
2028          * (the other states are just copies of the boot state) we only
2029          * need to populate the  ARB settings for the initial state.
2030          */
2031         result = polaris10_program_memory_timing_parameters(hwmgr);
2032         PP_ASSERT_WITH_CODE(0 == result,
2033                         "Failed to Write ARB settings for the initial state.", return result);
2034
2035         result = polaris10_populate_smc_uvd_level(hwmgr, table);
2036         PP_ASSERT_WITH_CODE(0 == result,
2037                         "Failed to initialize UVD Level!", return result);
2038
2039         result = polaris10_populate_smc_boot_level(hwmgr, table);
2040         PP_ASSERT_WITH_CODE(0 == result,
2041                         "Failed to initialize Boot Level!", return result);
2042
2043         result = polaris10_populate_smc_initailial_state(hwmgr);
2044         PP_ASSERT_WITH_CODE(0 == result,
2045                         "Failed to initialize Boot State!", return result);
2046
2047         result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
2048         PP_ASSERT_WITH_CODE(0 == result,
2049                         "Failed to populate BAPM Parameters!", return result);
2050
2051         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2052                         PHM_PlatformCaps_ClockStretcher)) {
2053                 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2054                 PP_ASSERT_WITH_CODE(0 == result,
2055                                 "Failed to populate Clock Stretcher Data Table!",
2056                                 return result);
2057         }
2058         table->CurrSclkPllRange = 0xff;
2059         table->GraphicsVoltageChangeEnable  = 1;
2060         table->GraphicsThermThrottleEnable  = 1;
2061         table->GraphicsInterval = 1;
2062         table->VoltageInterval  = 1;
2063         table->ThermalInterval  = 1;
2064         table->TemperatureLimitHigh =
2065                         table_info->cac_dtp_table->usTargetOperatingTemp *
2066                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2067         table->TemperatureLimitLow  =
2068                         (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2069                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2070         table->MemoryVoltageChangeEnable = 1;
2071         table->MemoryInterval = 1;
2072         table->VoltageResponseTime = 0;
2073         table->PhaseResponseTime = 0;
2074         table->MemoryThermThrottleEnable = 1;
2075         table->PCIeBootLinkLevel = 0;
2076         table->PCIeGenInterval = 1;
2077         table->VRConfig = 0;
2078
2079         result = polaris10_populate_vr_config(hwmgr, table);
2080         PP_ASSERT_WITH_CODE(0 == result,
2081                         "Failed to populate VRConfig setting!", return result);
2082
2083         table->ThermGpio = 17;
2084         table->SclkStepSize = 0x4000;
2085
2086         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2087                 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2088         } else {
2089                 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
2090                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2091                                 PHM_PlatformCaps_RegulatorHot);
2092         }
2093
2094         if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2095                         &gpio_pin)) {
2096                 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2097                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2098                                 PHM_PlatformCaps_AutomaticDCTransition);
2099         } else {
2100                 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
2101                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2102                                 PHM_PlatformCaps_AutomaticDCTransition);
2103         }
2104
2105         /* Thermal Output GPIO */
2106         if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2107                         &gpio_pin)) {
2108                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2109                                 PHM_PlatformCaps_ThermalOutGPIO);
2110
2111                 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2112
2113                 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2114                  * since VBIOS will program this register to set 'inactive state',
2115                  * driver can then determine 'active state' from this and
2116                  * program SMU with correct polarity
2117                  */
2118                 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2119                                         & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2120                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2121
2122                 /* if required, combine VRHot/PCC with thermal out GPIO */
2123                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2124                 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2125                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2126         } else {
2127                 table->ThermOutGpio = 17;
2128                 table->ThermOutPolarity = 1;
2129                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2130         }
2131
2132         /* Populate BIF_SCLK levels into SMC DPM table */
2133         for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2134                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
2135                 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2136
2137                 if (i == 0)
2138                         table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2139                 else
2140                         table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2141         }
2142
2143         for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2144                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2145
2146         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2147         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2148         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2149         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2150         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2151         CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2152         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2153         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2154         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2155         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2156
2157         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2158         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
2159                         data->dpm_table_start +
2160                         offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2161                         (uint8_t *)&(table->SystemFlags),
2162                         sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2163                         data->sram_end);
2164         PP_ASSERT_WITH_CODE(0 == result,
2165                         "Failed to upload dpm data to SMC memory!", return result);
2166
2167         return 0;
2168 }
2169
2170 /**
2171 * Initialize the ARB DRAM timing table's index field.
2172 *
2173 * @param    hwmgr  the address of the powerplay hardware manager.
2174 * @return   always 0
2175 */
2176 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
2177 {
2178         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2179         uint32_t tmp;
2180         int result;
2181
2182         /* This is a read-modify-write on the first byte of the ARB table.
2183          * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2184          * is the field 'current'.
2185          * This solution is ugly, but we never write the whole table only
2186          * individual fields in it.
2187          * In reality this field should not be in that structure
2188          * but in a soft register.
2189          */
2190         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
2191                         data->arb_table_start, &tmp, data->sram_end);
2192
2193         if (result)
2194                 return result;
2195
2196         tmp &= 0x00FFFFFF;
2197         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2198
2199         return polaris10_write_smc_sram_dword(hwmgr->smumgr,
2200                         data->arb_table_start, tmp, data->sram_end);
2201 }
2202
2203 static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
2204 {
2205         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2206                         PHM_PlatformCaps_RegulatorHot))
2207                 return smum_send_msg_to_smc(hwmgr->smumgr,
2208                                 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2209
2210         return 0;
2211 }
2212
2213 static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
2214 {
2215         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2216                         SCLK_PWRMGT_OFF, 0);
2217         return 0;
2218 }
2219
2220 static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
2221 {
2222         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2223         struct polaris10_ulv_parm *ulv = &(data->ulv);
2224
2225         if (ulv->ulv_supported)
2226                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2227
2228         return 0;
2229 }
2230
2231 static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2232 {
2233         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2234                         PHM_PlatformCaps_SclkDeepSleep)) {
2235                 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2236                         PP_ASSERT_WITH_CODE(false,
2237                                         "Attempt to enable Master Deep Sleep switch failed!",
2238                                         return -1);
2239         } else {
2240                 if (smum_send_msg_to_smc(hwmgr->smumgr,
2241                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2242                         PP_ASSERT_WITH_CODE(false,
2243                                         "Attempt to disable Master Deep Sleep switch failed!",
2244                                         return -1);
2245                 }
2246         }
2247
2248         return 0;
2249 }
2250
2251 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2252 {
2253         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2254         uint32_t soft_register_value = 0;
2255         uint32_t handshake_disables_offset = data->soft_regs_start
2256                                 + offsetof(SMU74_SoftRegisters, HandshakeDisables);
2257
2258         /* enable SCLK dpm */
2259         if (!data->sclk_dpm_key_disabled)
2260                 PP_ASSERT_WITH_CODE(
2261                 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2262                 "Failed to enable SCLK DPM during DPM Start Function!",
2263                 return -1);
2264
2265         /* enable MCLK dpm */
2266         if (0 == data->mclk_dpm_key_disabled) {
2267 /* Disable UVD - SMU handshake for MCLK. */
2268                 soft_register_value = cgs_read_ind_register(hwmgr->device,
2269                                         CGS_IND_REG__SMC, handshake_disables_offset);
2270                 soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2271                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2272                                 handshake_disables_offset, soft_register_value);
2273
2274                 PP_ASSERT_WITH_CODE(
2275                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2276                                                 PPSMC_MSG_MCLKDPM_Enable)),
2277                                 "Failed to enable MCLK DPM during DPM Start Function!",
2278                                 return -1);
2279
2280
2281                 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2282
2283                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2284                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2285                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2286                 udelay(10);
2287                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2288                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2289                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2290         }
2291
2292         return 0;
2293 }
2294
2295 static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
2296 {
2297         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2298
2299         /*enable general power management */
2300
2301         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2302                         GLOBAL_PWRMGT_EN, 1);
2303
2304         /* enable sclk deep sleep */
2305
2306         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2307                         DYNAMIC_PM_EN, 1);
2308
2309         /* prepare for PCIE DPM */
2310
2311         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2312                         data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2313                                         VoltageChangeTimeout), 0x1000);
2314         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2315                         SWRST_COMMAND_1, RESETLC, 0x0);
2316 /*
2317         PP_ASSERT_WITH_CODE(
2318                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2319                                         PPSMC_MSG_Voltage_Cntl_Enable)),
2320                         "Failed to enable voltage DPM during DPM Start Function!",
2321                         return -1);
2322 */
2323
2324         if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
2325                 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2326                 return -1;
2327         }
2328
2329         /* enable PCIE dpm */
2330         if (0 == data->pcie_dpm_key_disabled) {
2331                 PP_ASSERT_WITH_CODE(
2332                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2333                                                 PPSMC_MSG_PCIeDPM_Enable)),
2334                                 "Failed to enable pcie DPM during DPM Start Function!",
2335                                 return -1);
2336         }
2337
2338         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2339                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
2340                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2341                                 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2342                                 "Failed to enable AC DC GPIO Interrupt!",
2343                                 );
2344         }
2345
2346         return 0;
2347 }
2348
2349 static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
2350 {
2351         bool protection;
2352         enum DPM_EVENT_SRC src;
2353
2354         switch (sources) {
2355         default:
2356                 printk(KERN_ERR "Unknown throttling event sources.");
2357                 /* fall through */
2358         case 0:
2359                 protection = false;
2360                 /* src is unused */
2361                 break;
2362         case (1 << PHM_AutoThrottleSource_Thermal):
2363                 protection = true;
2364                 src = DPM_EVENT_SRC_DIGITAL;
2365                 break;
2366         case (1 << PHM_AutoThrottleSource_External):
2367                 protection = true;
2368                 src = DPM_EVENT_SRC_EXTERNAL;
2369                 break;
2370         case (1 << PHM_AutoThrottleSource_External) |
2371                         (1 << PHM_AutoThrottleSource_Thermal):
2372                 protection = true;
2373                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2374                 break;
2375         }
2376         /* Order matters - don't enable thermal protection for the wrong source. */
2377         if (protection) {
2378                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2379                                 DPM_EVENT_SRC, src);
2380                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2381                                 THERMAL_PROTECTION_DIS,
2382                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2383                                                 PHM_PlatformCaps_ThermalController));
2384         } else
2385                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2386                                 THERMAL_PROTECTION_DIS, 1);
2387 }
2388
2389 static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2390                 PHM_AutoThrottleSource source)
2391 {
2392         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2393
2394         if (!(data->active_auto_throttle_sources & (1 << source))) {
2395                 data->active_auto_throttle_sources |= 1 << source;
2396                 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2397         }
2398         return 0;
2399 }
2400
2401 static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2402 {
2403         return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2404 }
2405
2406 int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
2407 {
2408         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2409         data->pcie_performance_request = true;
2410
2411         return 0;
2412 }
2413
2414 int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2415 {
2416         int tmp_result, result = 0;
2417         tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2418         PP_ASSERT_WITH_CODE(result == 0,
2419                         "DPM is already running right now, no need to enable DPM!",
2420                         return 0);
2421
2422         if (polaris10_voltage_control(hwmgr)) {
2423                 tmp_result = polaris10_enable_voltage_control(hwmgr);
2424                 PP_ASSERT_WITH_CODE(tmp_result == 0,
2425                                 "Failed to enable voltage control!",
2426                                 result = tmp_result);
2427
2428                 tmp_result = polaris10_construct_voltage_tables(hwmgr);
2429                 PP_ASSERT_WITH_CODE((0 == tmp_result),
2430                                 "Failed to contruct voltage tables!",
2431                                 result = tmp_result);
2432         }
2433
2434         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2435                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2436                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2437                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2438
2439         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2440                         PHM_PlatformCaps_ThermalController))
2441                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2442                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2443
2444         tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
2445         PP_ASSERT_WITH_CODE((0 == tmp_result),
2446                         "Failed to program static screen threshold parameters!",
2447                         result = tmp_result);
2448
2449         tmp_result = polaris10_enable_display_gap(hwmgr);
2450         PP_ASSERT_WITH_CODE((0 == tmp_result),
2451                         "Failed to enable display gap!", result = tmp_result);
2452
2453         tmp_result = polaris10_program_voting_clients(hwmgr);
2454         PP_ASSERT_WITH_CODE((0 == tmp_result),
2455                         "Failed to program voting clients!", result = tmp_result);
2456
2457         tmp_result = polaris10_process_firmware_header(hwmgr);
2458         PP_ASSERT_WITH_CODE((0 == tmp_result),
2459                         "Failed to process firmware header!", result = tmp_result);
2460
2461         tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
2462         PP_ASSERT_WITH_CODE((0 == tmp_result),
2463                         "Failed to initialize switch from ArbF0 to F1!",
2464                         result = tmp_result);
2465
2466         tmp_result = polaris10_init_smc_table(hwmgr);
2467         PP_ASSERT_WITH_CODE((0 == tmp_result),
2468                         "Failed to initialize SMC table!", result = tmp_result);
2469
2470         tmp_result = polaris10_init_arb_table_index(hwmgr);
2471         PP_ASSERT_WITH_CODE((0 == tmp_result),
2472                         "Failed to initialize ARB table index!", result = tmp_result);
2473
2474         tmp_result = polaris10_populate_pm_fuses(hwmgr);
2475         PP_ASSERT_WITH_CODE((0 == tmp_result),
2476                         "Failed to populate PM fuses!", result = tmp_result);
2477
2478         tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
2479         PP_ASSERT_WITH_CODE((0 == tmp_result),
2480                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2481
2482         tmp_result = polaris10_enable_sclk_control(hwmgr);
2483         PP_ASSERT_WITH_CODE((0 == tmp_result),
2484                         "Failed to enable SCLK control!", result = tmp_result);
2485
2486         tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
2487         PP_ASSERT_WITH_CODE((0 == tmp_result),
2488                         "Failed to enable voltage control!", result = tmp_result);
2489
2490         tmp_result = polaris10_enable_ulv(hwmgr);
2491         PP_ASSERT_WITH_CODE((0 == tmp_result),
2492                         "Failed to enable ULV!", result = tmp_result);
2493
2494         tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
2495         PP_ASSERT_WITH_CODE((0 == tmp_result),
2496                         "Failed to enable deep sleep master switch!", result = tmp_result);
2497
2498         tmp_result = polaris10_start_dpm(hwmgr);
2499         PP_ASSERT_WITH_CODE((0 == tmp_result),
2500                         "Failed to start DPM!", result = tmp_result);
2501
2502         tmp_result = polaris10_enable_smc_cac(hwmgr);
2503         PP_ASSERT_WITH_CODE((0 == tmp_result),
2504                         "Failed to enable SMC CAC!", result = tmp_result);
2505
2506         tmp_result = polaris10_enable_power_containment(hwmgr);
2507         PP_ASSERT_WITH_CODE((0 == tmp_result),
2508                         "Failed to enable power containment!", result = tmp_result);
2509
2510         tmp_result = polaris10_power_control_set_level(hwmgr);
2511         PP_ASSERT_WITH_CODE((0 == tmp_result),
2512                         "Failed to power control set level!", result = tmp_result);
2513
2514         tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
2515         PP_ASSERT_WITH_CODE((0 == tmp_result),
2516                         "Failed to enable thermal auto throttle!", result = tmp_result);
2517
2518         tmp_result = polaris10_pcie_performance_request(hwmgr);
2519         PP_ASSERT_WITH_CODE((0 == tmp_result),
2520                         "pcie performance request failed!", result = tmp_result);
2521
2522         return result;
2523 }
2524
2525 int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2526 {
2527
2528         return 0;
2529 }
2530
2531 int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
2532 {
2533
2534         return 0;
2535 }
2536
2537 int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2538 {
2539         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2540
2541         if (data->soft_pp_table) {
2542                 kfree(data->soft_pp_table);
2543                 data->soft_pp_table = NULL;
2544         }
2545
2546         return phm_hwmgr_backend_fini(hwmgr);
2547 }
2548
2549 int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
2550 {
2551         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2552
2553         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2554                         PHM_PlatformCaps_SclkDeepSleep);
2555
2556         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2557                 PHM_PlatformCaps_DynamicPatchPowerState);
2558
2559         if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2560                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2561                                 PHM_PlatformCaps_EnableMVDDControl);
2562
2563         if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2564                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2565                                 PHM_PlatformCaps_ControlVDDCI);
2566
2567         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2568                          PHM_PlatformCaps_TablelessHardwareInterface);
2569
2570         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2571                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
2572
2573         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2574                         PHM_PlatformCaps_DynamicPowerManagement);
2575
2576         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2577                         PHM_PlatformCaps_UnTabledHardwareInterface);
2578
2579         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2580                         PHM_PlatformCaps_TablelessHardwareInterface);
2581
2582         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2583                                         PHM_PlatformCaps_SMC);
2584
2585         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2586                                         PHM_PlatformCaps_NonABMSupportInPPLib);
2587
2588         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2589                                         PHM_PlatformCaps_DynamicUVDState);
2590
2591         /* power tune caps Assume disabled */
2592         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2593                                                 PHM_PlatformCaps_SQRamping);
2594         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2595                                                 PHM_PlatformCaps_DBRamping);
2596         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2597                                                 PHM_PlatformCaps_TDRamping);
2598         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2599                                                 PHM_PlatformCaps_TCPRamping);
2600
2601         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2602                                         PHM_PlatformCaps_PowerContainment);
2603         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2604                                                         PHM_PlatformCaps_CAC);
2605
2606         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2607                                                 PHM_PlatformCaps_RegulatorHot);
2608
2609         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2610                                                 PHM_PlatformCaps_AutomaticDCTransition);
2611
2612         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2613                                                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2614
2615         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2616                                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
2617
2618         if (hwmgr->chip_id == CHIP_POLARIS11)
2619                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2620                                         PHM_PlatformCaps_SPLLShutdownSupport);
2621         return 0;
2622 }
2623
2624 static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
2625 {
2626         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2627
2628         polaris10_initialize_power_tune_defaults(hwmgr);
2629
2630         data->pcie_gen_performance.max = PP_PCIEGen1;
2631         data->pcie_gen_performance.min = PP_PCIEGen3;
2632         data->pcie_gen_power_saving.max = PP_PCIEGen1;
2633         data->pcie_gen_power_saving.min = PP_PCIEGen3;
2634         data->pcie_lane_performance.max = 0;
2635         data->pcie_lane_performance.min = 16;
2636         data->pcie_lane_power_saving.max = 0;
2637         data->pcie_lane_power_saving.min = 16;
2638 }
2639
2640 /**
2641 * Get Leakage VDDC based on leakage ID.
2642 *
2643 * @param    hwmgr  the address of the powerplay hardware manager.
2644 * @return   always 0
2645 */
2646 static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
2647 {
2648         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2649         uint16_t vv_id;
2650         uint16_t vddc = 0;
2651         uint16_t i, j;
2652         uint32_t sclk = 0;
2653         struct phm_ppt_v1_information *table_info =
2654                         (struct phm_ppt_v1_information *)hwmgr->pptable;
2655         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2656                         table_info->vdd_dep_on_sclk;
2657         int result;
2658
2659         for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
2660                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2661                 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2662                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
2663                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2664                                         PHM_PlatformCaps_ClockStretcher)) {
2665                                 for (j = 1; j < sclk_table->count; j++) {
2666                                         if (sclk_table->entries[j].clk == sclk &&
2667                                                         sclk_table->entries[j].cks_enable == 0) {
2668                                                 sclk += 5000;
2669                                                 break;
2670                                         }
2671                                 }
2672                         }
2673
2674
2675                         PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2676                                                         VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
2677                                                 "Error retrieving EVV voltage value!",
2678                                                 continue);
2679
2680
2681                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
2682                         PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
2683                                         "Invalid VDDC value", result = -EINVAL;);
2684
2685                         /* the voltage should not be zero nor equal to leakage ID */
2686                         if (vddc != 0 && vddc != vv_id) {
2687                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2688                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2689                                 data->vddc_leakage.count++;
2690                         }
2691                 }
2692         }
2693
2694         return 0;
2695 }
2696
2697 /**
2698  * Change virtual leakage voltage to actual value.
2699  *
2700  * @param     hwmgr  the address of the powerplay hardware manager.
2701  * @param     pointer to changing voltage
2702  * @param     pointer to leakage table
2703  */
2704 static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2705                 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
2706 {
2707         uint32_t index;
2708
2709         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2710         for (index = 0; index < leakage_table->count; index++) {
2711                 /* if this voltage matches a leakage voltage ID */
2712                 /* patch with actual leakage voltage */
2713                 if (leakage_table->leakage_id[index] == *voltage) {
2714                         *voltage = leakage_table->actual_voltage[index];
2715                         break;
2716                 }
2717         }
2718
2719         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2720                 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2721 }
2722
2723 /**
2724 * Patch voltage lookup table by EVV leakages.
2725 *
2726 * @param     hwmgr  the address of the powerplay hardware manager.
2727 * @param     pointer to voltage lookup table
2728 * @param     pointer to leakage table
2729 * @return     always 0
2730 */
2731 static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2732                 phm_ppt_v1_voltage_lookup_table *lookup_table,
2733                 struct polaris10_leakage_voltage *leakage_table)
2734 {
2735         uint32_t i;
2736
2737         for (i = 0; i < lookup_table->count; i++)
2738                 polaris10_patch_with_vdd_leakage(hwmgr,
2739                                 &lookup_table->entries[i].us_vdd, leakage_table);
2740
2741         return 0;
2742 }
2743
2744 static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2745                 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
2746                 uint16_t *vddc)
2747 {
2748         struct phm_ppt_v1_information *table_info =
2749                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2750         polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2751         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2752                         table_info->max_clock_voltage_on_dc.vddc;
2753         return 0;
2754 }
2755
2756 static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
2757                 struct pp_hwmgr *hwmgr)
2758 {
2759         uint8_t entryId;
2760         uint8_t voltageId;
2761         struct phm_ppt_v1_information *table_info =
2762                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2763
2764         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2765                         table_info->vdd_dep_on_sclk;
2766         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2767                         table_info->vdd_dep_on_mclk;
2768         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2769                         table_info->mm_dep_table;
2770
2771         for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2772                 voltageId = sclk_table->entries[entryId].vddInd;
2773                 sclk_table->entries[entryId].vddc =
2774                                 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2775         }
2776
2777         for (entryId = 0; entryId < mclk_table->count; ++entryId) {
2778                 voltageId = mclk_table->entries[entryId].vddInd;
2779                 mclk_table->entries[entryId].vddc =
2780                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2781         }
2782
2783         for (entryId = 0; entryId < mm_table->count; ++entryId) {
2784                 voltageId = mm_table->entries[entryId].vddcInd;
2785                 mm_table->entries[entryId].vddc =
2786                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2787         }
2788
2789         return 0;
2790
2791 }
2792
2793 static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
2794 {
2795         /* Need to determine if we need calculated voltage. */
2796         return 0;
2797 }
2798
2799 static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
2800 {
2801         /* Need to determine if we need calculated voltage from mm table. */
2802         return 0;
2803 }
2804
2805 static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
2806                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2807 {
2808         uint32_t table_size, i, j;
2809         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
2810         table_size = lookup_table->count;
2811
2812         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2813                 "Lookup table is empty", return -EINVAL);
2814
2815         /* Sorting voltages */
2816         for (i = 0; i < table_size - 1; i++) {
2817                 for (j = i + 1; j > 0; j--) {
2818                         if (lookup_table->entries[j].us_vdd <
2819                                         lookup_table->entries[j - 1].us_vdd) {
2820                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
2821                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
2822                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
2823                         }
2824                 }
2825         }
2826
2827         return 0;
2828 }
2829
2830 static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2831 {
2832         int result = 0;
2833         int tmp_result;
2834         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2835         struct phm_ppt_v1_information *table_info =
2836                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2837
2838         tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
2839                         table_info->vddc_lookup_table, &(data->vddc_leakage));
2840         if (tmp_result)
2841                 result = tmp_result;
2842
2843         tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2844                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2845         if (tmp_result)
2846                 result = tmp_result;
2847
2848         tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2849         if (tmp_result)
2850                 result = tmp_result;
2851
2852         tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
2853         if (tmp_result)
2854                 result = tmp_result;
2855
2856         tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
2857         if (tmp_result)
2858                 result = tmp_result;
2859
2860         tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2861         if (tmp_result)
2862                 result = tmp_result;
2863
2864         return result;
2865 }
2866
2867 static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
2868 {
2869         struct phm_ppt_v1_information *table_info =
2870                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2871
2872         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2873                                                 table_info->vdd_dep_on_sclk;
2874         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2875                                                 table_info->vdd_dep_on_mclk;
2876
2877         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2878                 "VDD dependency on SCLK table is missing.       \
2879                 This table is mandatory", return -EINVAL);
2880         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2881                 "VDD dependency on SCLK table has to have is missing.   \
2882                 This table is mandatory", return -EINVAL);
2883
2884         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2885                 "VDD dependency on MCLK table is missing.       \
2886                 This table is mandatory", return -EINVAL);
2887         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2888                 "VDD dependency on MCLK table has to have is missing.    \
2889                 This table is mandatory", return -EINVAL);
2890
2891         table_info->max_clock_voltage_on_ac.sclk =
2892                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2893         table_info->max_clock_voltage_on_ac.mclk =
2894                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2895         table_info->max_clock_voltage_on_ac.vddc =
2896                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2897         table_info->max_clock_voltage_on_ac.vddci =
2898                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2899
2900         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2901         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2902         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2903         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
2904
2905         return 0;
2906 }
2907
2908 int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2909 {
2910         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2911         struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2912         uint32_t temp_reg;
2913         int result;
2914         struct phm_ppt_v1_information *table_info =
2915                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2916
2917         data->dll_default_on = false;
2918         data->sram_end = SMC_RAM_END;
2919         data->mclk_dpm0_activity_target = 0xa;
2920         data->disable_dpm_mask = 0xFF;
2921         data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2922         data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2923         data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2924         data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2925         data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2926         data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2927         data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2928         data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2929         data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2930         data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2931
2932         data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
2933         data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
2934         data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
2935         data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
2936         data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
2937         data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
2938         data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
2939         data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
2940
2941         data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
2942
2943         data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
2944
2945         /* need to set voltage control types before EVV patching */
2946         data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2947         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2948         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2949
2950         data->enable_tdc_limit_feature = true;
2951         data->enable_pkg_pwr_tracking_feature = true;
2952         data->force_pcie_gen = PP_PCIEGenInvalid;
2953         data->mclk_stutter_mode_threshold = 40000;
2954
2955         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2956                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
2957                 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2958
2959         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2960                         PHM_PlatformCaps_EnableMVDDControl)) {
2961                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2962                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
2963                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
2964                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2965                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
2966                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2967         }
2968
2969         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2970                         PHM_PlatformCaps_ControlVDDCI)) {
2971                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2972                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
2973                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
2974                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2975                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
2976                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2977         }
2978
2979         polaris10_set_features_platform_caps(hwmgr);
2980
2981         polaris10_init_dpm_defaults(hwmgr);
2982
2983         /* Get leakage voltage based on leakage ID. */
2984         result = polaris10_get_evv_voltages(hwmgr);
2985
2986         if (result) {
2987                 printk("Get EVV Voltage Failed.  Abort Driver loading!\n");
2988                 return -1;
2989         }
2990
2991         polaris10_complete_dependency_tables(hwmgr);
2992         polaris10_set_private_data_based_on_pptable(hwmgr);
2993
2994         /* Initalize Dynamic State Adjustment Rule Settings */
2995         result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
2996
2997         if (0 == result) {
2998                 struct cgs_system_info sys_info = {0};
2999
3000                 data->is_tlu_enabled = 0;
3001
3002                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
3003                                                         POLARIS10_MAX_HARDWARE_POWERLEVELS;
3004                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3005                 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
3006
3007
3008                 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
3009                         temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3010                         switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3011                         case 0:
3012                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3013                                 break;
3014                         case 1:
3015                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3016                                 break;
3017                         case 2:
3018                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3019                                 break;
3020                         case 3:
3021                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3022                                 break;
3023                         case 4:
3024                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3025                                 break;
3026                         default:
3027                                 PP_ASSERT_WITH_CODE(0,
3028                                 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3029                                 );
3030                                 break;
3031                         }
3032                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3033                 }
3034
3035                 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3036                         hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3037                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3038                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3039
3040                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3041                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3042
3043                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3044
3045                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3046
3047                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3048                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3049
3050                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3051
3052                         table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3053                                                                         (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3054
3055                         table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3056                         table_info->cac_dtp_table->usOperatingTempStep = 1;
3057                         table_info->cac_dtp_table->usOperatingTempHyst = 1;
3058
3059                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3060                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3061
3062                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3063                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3064
3065                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3066                                        table_info->cac_dtp_table->usOperatingTempMinLimit;
3067
3068                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3069                                        table_info->cac_dtp_table->usOperatingTempMaxLimit;
3070
3071                         hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3072                                        table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3073
3074                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3075                                        table_info->cac_dtp_table->usOperatingTempStep;
3076
3077                         hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3078                                        table_info->cac_dtp_table->usTargetOperatingTemp;
3079                 }
3080
3081                 sys_info.size = sizeof(struct cgs_system_info);
3082                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3083                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3084                 if (result)
3085                         data->pcie_gen_cap = 0x30007;
3086                 else
3087                         data->pcie_gen_cap = (uint32_t)sys_info.value;
3088                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3089                         data->pcie_spc_cap = 20;
3090                 sys_info.size = sizeof(struct cgs_system_info);
3091                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3092                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3093                 if (result)
3094                         data->pcie_lane_cap = 0x2f0000;
3095                 else
3096                         data->pcie_lane_cap = (uint32_t)sys_info.value;
3097
3098                 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3099 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3100                 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3101                 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
3102         } else {
3103                 /* Ignore return value in here, we are cleaning up a mess. */
3104                 polaris10_hwmgr_backend_fini(hwmgr);
3105         }
3106
3107         return 0;
3108 }
3109
3110 static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3111 {
3112         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3113         uint32_t level, tmp;
3114
3115         if (!data->pcie_dpm_key_disabled) {
3116                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3117                         level = 0;
3118                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3119                         while (tmp >>= 1)
3120                                 level++;
3121
3122                         if (level)
3123                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3124                                                 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3125                 }
3126         }
3127
3128         if (!data->sclk_dpm_key_disabled) {
3129                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3130                         level = 0;
3131                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3132                         while (tmp >>= 1)
3133                                 level++;
3134
3135                         if (level)
3136                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3137                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3138                                                 (1 << level));
3139                 }
3140         }
3141
3142         if (!data->mclk_dpm_key_disabled) {
3143                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3144                         level = 0;
3145                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3146                         while (tmp >>= 1)
3147                                 level++;
3148
3149                         if (level)
3150                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3151                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3152                                                 (1 << level));
3153                 }
3154         }
3155
3156         return 0;
3157 }
3158
3159 static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3160 {
3161         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3162
3163         phm_apply_dal_min_voltage_request(hwmgr);
3164
3165         if (!data->sclk_dpm_key_disabled) {
3166                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3167                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3168                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
3169                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3170         }
3171
3172         if (!data->mclk_dpm_key_disabled) {
3173                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3174                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3175                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
3176                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3177         }
3178
3179         return 0;
3180 }
3181
3182 static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3183 {
3184         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3185
3186         if (!polaris10_is_dpm_running(hwmgr))
3187                 return -EINVAL;
3188
3189         if (!data->pcie_dpm_key_disabled) {
3190                 smum_send_msg_to_smc(hwmgr->smumgr,
3191                                 PPSMC_MSG_PCIeDPM_UnForceLevel);
3192         }
3193
3194         return polaris10_upload_dpm_level_enable_mask(hwmgr);
3195 }
3196
3197 static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3198 {
3199         struct polaris10_hwmgr *data =
3200                         (struct polaris10_hwmgr *)(hwmgr->backend);
3201         uint32_t level;
3202
3203         if (!data->sclk_dpm_key_disabled)
3204                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3205                         level = phm_get_lowest_enabled_level(hwmgr,
3206                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3207                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3208                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
3209                                                             (1 << level));
3210
3211         }
3212
3213         if (!data->mclk_dpm_key_disabled) {
3214                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3215                         level = phm_get_lowest_enabled_level(hwmgr,
3216                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3217                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3218                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
3219                                                             (1 << level));
3220                 }
3221         }
3222
3223         if (!data->pcie_dpm_key_disabled) {
3224                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3225                         level = phm_get_lowest_enabled_level(hwmgr,
3226                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3227                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3228                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
3229                                                             (level));
3230                 }
3231         }
3232
3233         return 0;
3234
3235 }
3236 static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
3237                                 enum amd_dpm_forced_level level)
3238 {
3239         int ret = 0;
3240
3241         switch (level) {
3242         case AMD_DPM_FORCED_LEVEL_HIGH:
3243                 ret = polaris10_force_dpm_highest(hwmgr);
3244                 if (ret)
3245                         return ret;
3246                 break;
3247         case AMD_DPM_FORCED_LEVEL_LOW:
3248                 ret = polaris10_force_dpm_lowest(hwmgr);
3249                 if (ret)
3250                         return ret;
3251                 break;
3252         case AMD_DPM_FORCED_LEVEL_AUTO:
3253                 ret = polaris10_unforce_dpm_levels(hwmgr);
3254                 if (ret)
3255                         return ret;
3256                 break;
3257         default:
3258                 break;
3259         }
3260
3261         hwmgr->dpm_level = level;
3262
3263         return ret;
3264 }
3265
3266 static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
3267 {
3268         return sizeof(struct polaris10_power_state);
3269 }
3270
3271
3272 static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3273                                 struct pp_power_state *request_ps,
3274                         const struct pp_power_state *current_ps)
3275 {
3276
3277         struct polaris10_power_state *polaris10_ps =
3278                                 cast_phw_polaris10_power_state(&request_ps->hardware);
3279         uint32_t sclk;
3280         uint32_t mclk;
3281         struct PP_Clocks minimum_clocks = {0};
3282         bool disable_mclk_switching;
3283         bool disable_mclk_switching_for_frame_lock;
3284         struct cgs_display_info info = {0};
3285         const struct phm_clock_and_voltage_limits *max_limits;
3286         uint32_t i;
3287         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3288         struct phm_ppt_v1_information *table_info =
3289                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3290         int32_t count;
3291         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3292
3293         data->battery_state = (PP_StateUILabel_Battery ==
3294                         request_ps->classification.ui_label);
3295
3296         PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
3297                                  "VI should always have 2 performance levels",
3298                                 );
3299
3300         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3301                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3302                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3303
3304         /* Cap clock DPM tables at DC MAX if it is in DC. */
3305         if (PP_PowerSource_DC == hwmgr->power_source) {
3306                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3307                         if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3308                                 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3309                         if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3310                                 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
3311                 }
3312         }
3313
3314         polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3315         polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3316
3317         cgs_get_active_displays_info(hwmgr->device, &info);
3318
3319         /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3320
3321         /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3322
3323         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3324                         PHM_PlatformCaps_StablePState)) {
3325                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3326                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3327
3328                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3329                                 count >= 0; count--) {
3330                         if (stable_pstate_sclk >=
3331                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3332                                 stable_pstate_sclk =
3333                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3334                                 break;
3335                         }
3336                 }
3337
3338                 if (count < 0)
3339                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3340
3341                 stable_pstate_mclk = max_limits->mclk;
3342
3343                 minimum_clocks.engineClock = stable_pstate_sclk;
3344                 minimum_clocks.memoryClock = stable_pstate_mclk;
3345         }
3346
3347         if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3348                 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3349
3350         if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3351                 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3352
3353         polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3354
3355         if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3356                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3357                                 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3358                                 "Overdrive sclk exceeds limit",
3359                                 hwmgr->gfx_arbiter.sclk_over_drive =
3360                                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3361
3362                 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3363                         polaris10_ps->performance_levels[1].engine_clock =
3364                                         hwmgr->gfx_arbiter.sclk_over_drive;
3365         }
3366
3367         if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3368                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3369                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3370                                 "Overdrive mclk exceeds limit",
3371                                 hwmgr->gfx_arbiter.mclk_over_drive =
3372                                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3373
3374                 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3375                         polaris10_ps->performance_levels[1].memory_clock =
3376                                         hwmgr->gfx_arbiter.mclk_over_drive;
3377         }
3378
3379         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3380                                     hwmgr->platform_descriptor.platformCaps,
3381                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3382
3383         disable_mclk_switching = (1 < info.display_count) ||
3384                                     disable_mclk_switching_for_frame_lock;
3385
3386         sclk = polaris10_ps->performance_levels[0].engine_clock;
3387         mclk = polaris10_ps->performance_levels[0].memory_clock;
3388
3389         if (disable_mclk_switching)
3390                 mclk = polaris10_ps->performance_levels
3391                 [polaris10_ps->performance_level_count - 1].memory_clock;
3392
3393         if (sclk < minimum_clocks.engineClock)
3394                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3395                                 max_limits->sclk : minimum_clocks.engineClock;
3396
3397         if (mclk < minimum_clocks.memoryClock)
3398                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3399                                 max_limits->mclk : minimum_clocks.memoryClock;
3400
3401         polaris10_ps->performance_levels[0].engine_clock = sclk;
3402         polaris10_ps->performance_levels[0].memory_clock = mclk;
3403
3404         polaris10_ps->performance_levels[1].engine_clock =
3405                 (polaris10_ps->performance_levels[1].engine_clock >=
3406                                 polaris10_ps->performance_levels[0].engine_clock) ?
3407                                                 polaris10_ps->performance_levels[1].engine_clock :
3408                                                 polaris10_ps->performance_levels[0].engine_clock;
3409
3410         if (disable_mclk_switching) {
3411                 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3412                         mclk = polaris10_ps->performance_levels[1].memory_clock;
3413
3414                 polaris10_ps->performance_levels[0].memory_clock = mclk;
3415                 polaris10_ps->performance_levels[1].memory_clock = mclk;
3416         } else {
3417                 if (polaris10_ps->performance_levels[1].memory_clock <
3418                                 polaris10_ps->performance_levels[0].memory_clock)
3419                         polaris10_ps->performance_levels[1].memory_clock =
3420                                         polaris10_ps->performance_levels[0].memory_clock;
3421         }
3422
3423         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3424                         PHM_PlatformCaps_StablePState)) {
3425                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3426                         polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3427                         polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3428                         polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3429                         polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3430                 }
3431         }
3432         return 0;
3433 }
3434
3435
3436 static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3437 {
3438         struct pp_power_state  *ps;
3439         struct polaris10_power_state  *polaris10_ps;
3440
3441         if (hwmgr == NULL)
3442                 return -EINVAL;
3443
3444         ps = hwmgr->request_ps;
3445
3446         if (ps == NULL)
3447                 return -EINVAL;
3448
3449         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3450
3451         if (low)
3452                 return polaris10_ps->performance_levels[0].memory_clock;
3453         else
3454                 return polaris10_ps->performance_levels
3455                                 [polaris10_ps->performance_level_count-1].memory_clock;
3456 }
3457
3458 static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3459 {
3460         struct pp_power_state  *ps;
3461         struct polaris10_power_state  *polaris10_ps;
3462
3463         if (hwmgr == NULL)
3464                 return -EINVAL;
3465
3466         ps = hwmgr->request_ps;
3467
3468         if (ps == NULL)
3469                 return -EINVAL;
3470
3471         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3472
3473         if (low)
3474                 return polaris10_ps->performance_levels[0].engine_clock;
3475         else
3476                 return polaris10_ps->performance_levels
3477                                 [polaris10_ps->performance_level_count-1].engine_clock;
3478 }
3479
3480 static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3481                                         struct pp_hw_power_state *hw_ps)
3482 {
3483         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3484         struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
3485         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3486         uint16_t size;
3487         uint8_t frev, crev;
3488         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3489
3490         /* First retrieve the Boot clocks and VDDC from the firmware info table.
3491          * We assume here that fw_info is unchanged if this call fails.
3492          */
3493         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3494                         hwmgr->device, index,
3495                         &size, &frev, &crev);
3496         if (!fw_info)
3497                 /* During a test, there is no firmware info table. */
3498                 return 0;
3499
3500         /* Patch the state. */
3501         data->vbios_boot_state.sclk_bootup_value =
3502                         le32_to_cpu(fw_info->ulDefaultEngineClock);
3503         data->vbios_boot_state.mclk_bootup_value =
3504                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
3505         data->vbios_boot_state.mvdd_bootup_value =
3506                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3507         data->vbios_boot_state.vddc_bootup_value =
3508                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3509         data->vbios_boot_state.vddci_bootup_value =
3510                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3511         data->vbios_boot_state.pcie_gen_bootup_value =
3512                         phm_get_current_pcie_speed(hwmgr);
3513
3514         data->vbios_boot_state.pcie_lane_bootup_value =
3515                         (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3516
3517         /* set boot power state */
3518         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3519         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3520         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3521         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3522
3523         return 0;
3524 }
3525
3526 static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3527                 void *state, struct pp_power_state *power_state,
3528                 void *pp_table, uint32_t classification_flag)
3529 {
3530         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3531         struct polaris10_power_state  *polaris10_power_state =
3532                         (struct polaris10_power_state *)(&(power_state->hardware));
3533         struct polaris10_performance_level *performance_level;
3534         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3535         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3536                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3537         PPTable_Generic_SubTable_Header *sclk_dep_table =
3538                         (PPTable_Generic_SubTable_Header *)
3539                         (((unsigned long)powerplay_table) +
3540                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3541
3542         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3543                         (ATOM_Tonga_MCLK_Dependency_Table *)
3544                         (((unsigned long)powerplay_table) +
3545                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3546
3547         /* The following fields are not initialized here: id orderedList allStatesList */
3548         power_state->classification.ui_label =
3549                         (le16_to_cpu(state_entry->usClassification) &
3550                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3551                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3552         power_state->classification.flags = classification_flag;
3553         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3554
3555         power_state->classification.temporary_state = false;
3556         power_state->classification.to_be_deleted = false;
3557
3558         power_state->validation.disallowOnDC =
3559                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3560                                         ATOM_Tonga_DISALLOW_ON_DC));
3561
3562         power_state->pcie.lanes = 0;
3563
3564         power_state->display.disableFrameModulation = false;
3565         power_state->display.limitRefreshrate = false;
3566         power_state->display.enableVariBright =
3567                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3568                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3569
3570         power_state->validation.supportedPowerLevels = 0;
3571         power_state->uvd_clocks.VCLK = 0;
3572         power_state->uvd_clocks.DCLK = 0;
3573         power_state->temperatures.min = 0;
3574         power_state->temperatures.max = 0;
3575
3576         performance_level = &(polaris10_power_state->performance_levels
3577                         [polaris10_power_state->performance_level_count++]);
3578
3579         PP_ASSERT_WITH_CODE(
3580                         (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
3581                         "Performance levels exceeds SMC limit!",
3582                         return -1);
3583
3584         PP_ASSERT_WITH_CODE(
3585                         (polaris10_power_state->performance_level_count <=
3586                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3587                         "Performance levels exceeds Driver limit!",
3588                         return -1);
3589
3590         /* Performance levels are arranged from low to high. */
3591         performance_level->memory_clock = mclk_dep_table->entries
3592                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3593         if (sclk_dep_table->ucRevId == 0)
3594                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3595                         [state_entry->ucEngineClockIndexLow].ulSclk;
3596         else if (sclk_dep_table->ucRevId == 1)
3597                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3598                         [state_entry->ucEngineClockIndexLow].ulSclk;
3599         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3600                         state_entry->ucPCIEGenLow);
3601         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3602                         state_entry->ucPCIELaneHigh);
3603
3604         performance_level = &(polaris10_power_state->performance_levels
3605                         [polaris10_power_state->performance_level_count++]);
3606         performance_level->memory_clock = mclk_dep_table->entries
3607                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3608
3609         if (sclk_dep_table->ucRevId == 0)
3610                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3611                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3612         else if (sclk_dep_table->ucRevId == 1)
3613                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3614                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3615
3616         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3617                         state_entry->ucPCIEGenHigh);
3618         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3619                         state_entry->ucPCIELaneHigh);
3620
3621         return 0;
3622 }
3623
3624 static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3625                 unsigned long entry_index, struct pp_power_state *state)
3626 {
3627         int result;
3628         struct polaris10_power_state *ps;
3629         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3630         struct phm_ppt_v1_information *table_info =
3631                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3632         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3633                         table_info->vdd_dep_on_mclk;
3634
3635         state->hardware.magic = PHM_VIslands_Magic;
3636
3637         ps = (struct polaris10_power_state *)(&state->hardware);
3638
3639         result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3640                         polaris10_get_pp_table_entry_callback_func);
3641
3642         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3643          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3644          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3645          */
3646         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3647                 if (dep_mclk_table->entries[0].clk !=
3648                                 data->vbios_boot_state.mclk_bootup_value)
3649                         printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3650                                         "does not match VBIOS boot MCLK level");
3651                 if (dep_mclk_table->entries[0].vddci !=
3652                                 data->vbios_boot_state.vddci_bootup_value)
3653                         printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3654                                         "does not match VBIOS boot VDDCI level");
3655         }
3656
3657         /* set DC compatible flag if this state supports DC */
3658         if (!state->validation.disallowOnDC)
3659                 ps->dc_compatible = true;
3660
3661         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3662                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3663
3664         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3665         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3666
3667         if (!result) {
3668                 uint32_t i;
3669
3670                 switch (state->classification.ui_label) {
3671                 case PP_StateUILabel_Performance:
3672                         data->use_pcie_performance_levels = true;
3673                         for (i = 0; i < ps->performance_level_count; i++) {
3674                                 if (data->pcie_gen_performance.max <
3675                                                 ps->performance_levels[i].pcie_gen)
3676                                         data->pcie_gen_performance.max =
3677                                                         ps->performance_levels[i].pcie_gen;
3678
3679                                 if (data->pcie_gen_performance.min >
3680                                                 ps->performance_levels[i].pcie_gen)
3681                                         data->pcie_gen_performance.min =
3682                                                         ps->performance_levels[i].pcie_gen;
3683
3684                                 if (data->pcie_lane_performance.max <
3685                                                 ps->performance_levels[i].pcie_lane)
3686                                         data->pcie_lane_performance.max =
3687                                                         ps->performance_levels[i].pcie_lane;
3688                                 if (data->pcie_lane_performance.min >
3689                                                 ps->performance_levels[i].pcie_lane)
3690                                         data->pcie_lane_performance.min =
3691                                                         ps->performance_levels[i].pcie_lane;
3692                         }
3693                         break;
3694                 case PP_StateUILabel_Battery:
3695                         data->use_pcie_power_saving_levels = true;
3696
3697                         for (i = 0; i < ps->performance_level_count; i++) {
3698                                 if (data->pcie_gen_power_saving.max <
3699                                                 ps->performance_levels[i].pcie_gen)
3700                                         data->pcie_gen_power_saving.max =
3701                                                         ps->performance_levels[i].pcie_gen;
3702
3703                                 if (data->pcie_gen_power_saving.min >
3704                                                 ps->performance_levels[i].pcie_gen)
3705                                         data->pcie_gen_power_saving.min =
3706                                                         ps->performance_levels[i].pcie_gen;
3707
3708                                 if (data->pcie_lane_power_saving.max <
3709                                                 ps->performance_levels[i].pcie_lane)
3710                                         data->pcie_lane_power_saving.max =
3711                                                         ps->performance_levels[i].pcie_lane;
3712
3713                                 if (data->pcie_lane_power_saving.min >
3714                                                 ps->performance_levels[i].pcie_lane)
3715                                         data->pcie_lane_power_saving.min =
3716                                                         ps->performance_levels[i].pcie_lane;
3717                         }
3718                         break;
3719                 default:
3720                         break;
3721                 }
3722         }
3723         return 0;
3724 }
3725
3726 static void
3727 polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
3728 {
3729         uint32_t sclk, mclk, activity_percent;
3730         uint32_t offset;
3731         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3732
3733         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3734
3735         sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3736
3737         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3738
3739         mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3740         seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
3741                         mclk / 100, sclk / 100);
3742
3743         offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
3744         activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3745         activity_percent += 0x80;
3746         activity_percent >>= 8;
3747
3748         seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3749
3750         seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
3751
3752         seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
3753 }
3754
3755 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3756 {
3757         const struct phm_set_power_state_input *states =
3758                         (const struct phm_set_power_state_input *)input;
3759         const struct polaris10_power_state *polaris10_ps =
3760                         cast_const_phw_polaris10_power_state(states->pnew_state);
3761         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3762         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3763         uint32_t sclk = polaris10_ps->performance_levels
3764                         [polaris10_ps->performance_level_count - 1].engine_clock;
3765         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3766         uint32_t mclk = polaris10_ps->performance_levels
3767                         [polaris10_ps->performance_level_count - 1].memory_clock;
3768         struct PP_Clocks min_clocks = {0};
3769         uint32_t i;
3770         struct cgs_display_info info = {0};
3771
3772         data->need_update_smu7_dpm_table = 0;
3773
3774         for (i = 0; i < sclk_table->count; i++) {
3775                 if (sclk == sclk_table->dpm_levels[i].value)
3776                         break;
3777         }
3778
3779         if (i >= sclk_table->count)
3780                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3781         else {
3782         /* TODO: Check SCLK in DAL's minimum clocks
3783          * in case DeepSleep divider update is required.
3784          */
3785                 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3786                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
3787                                 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
3788                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3789         }
3790
3791         for (i = 0; i < mclk_table->count; i++) {
3792                 if (mclk == mclk_table->dpm_levels[i].value)
3793                         break;
3794         }
3795
3796         if (i >= mclk_table->count)
3797                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3798
3799         cgs_get_active_displays_info(hwmgr->device, &info);
3800
3801         if (data->display_timing.num_existing_displays != info.display_count)
3802                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3803
3804         return 0;
3805 }
3806
3807 static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3808                 const struct polaris10_power_state *polaris10_ps)
3809 {
3810         uint32_t i;
3811         uint32_t sclk, max_sclk = 0;
3812         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3813         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3814
3815         for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3816                 sclk = polaris10_ps->performance_levels[i].engine_clock;
3817                 if (max_sclk < sclk)
3818                         max_sclk = sclk;
3819         }
3820
3821         for (i = 0; i < dpm_table->sclk_table.count; i++) {
3822                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3823                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3824                                         dpm_table->pcie_speed_table.dpm_levels
3825                                         [dpm_table->pcie_speed_table.count - 1].value :
3826                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
3827         }
3828
3829         return 0;
3830 }
3831
3832 static int polaris10_request_link_speed_change_before_state_change(
3833                 struct pp_hwmgr *hwmgr, const void *input)
3834 {
3835         const struct phm_set_power_state_input *states =
3836                         (const struct phm_set_power_state_input *)input;
3837         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3838         const struct polaris10_power_state *polaris10_nps =
3839                         cast_const_phw_polaris10_power_state(states->pnew_state);
3840         const struct polaris10_power_state *polaris10_cps =
3841                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
3842
3843         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
3844         uint16_t current_link_speed;
3845
3846         if (data->force_pcie_gen == PP_PCIEGenInvalid)
3847                 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
3848         else
3849                 current_link_speed = data->force_pcie_gen;
3850
3851         data->force_pcie_gen = PP_PCIEGenInvalid;
3852         data->pspp_notify_required = false;
3853
3854         if (target_link_speed > current_link_speed) {
3855                 switch (target_link_speed) {
3856                 case PP_PCIEGen3:
3857                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
3858                                 break;
3859                         data->force_pcie_gen = PP_PCIEGen2;
3860                         if (current_link_speed == PP_PCIEGen2)
3861                                 break;
3862                 case PP_PCIEGen2:
3863                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
3864                                 break;
3865                 default:
3866                         data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
3867                         break;
3868                 }
3869         } else {
3870                 if (target_link_speed < current_link_speed)
3871                         data->pspp_notify_required = true;
3872         }
3873
3874         return 0;
3875 }
3876
3877 static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3878 {
3879         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3880
3881         if (0 == data->need_update_smu7_dpm_table)
3882                 return 0;
3883
3884         if ((0 == data->sclk_dpm_key_disabled) &&
3885                 (data->need_update_smu7_dpm_table &
3886                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3887                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3888                                 "Trying to freeze SCLK DPM when DPM is disabled",
3889                                 );
3890                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3891                                 PPSMC_MSG_SCLKDPM_FreezeLevel),
3892                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3893                                 return -1);
3894         }
3895
3896         if ((0 == data->mclk_dpm_key_disabled) &&
3897                 (data->need_update_smu7_dpm_table &
3898                  DPMTABLE_OD_UPDATE_MCLK)) {
3899                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3900                                 "Trying to freeze MCLK DPM when DPM is disabled",
3901                                 );
3902                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3903                                 PPSMC_MSG_MCLKDPM_FreezeLevel),
3904                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3905                                 return -1);
3906         }
3907
3908         return 0;
3909 }
3910
3911 static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
3912                 struct pp_hwmgr *hwmgr, const void *input)
3913 {
3914         int result = 0;
3915         const struct phm_set_power_state_input *states =
3916                         (const struct phm_set_power_state_input *)input;
3917         const struct polaris10_power_state *polaris10_ps =
3918                         cast_const_phw_polaris10_power_state(states->pnew_state);
3919         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3920         uint32_t sclk = polaris10_ps->performance_levels
3921                         [polaris10_ps->performance_level_count - 1].engine_clock;
3922         uint32_t mclk = polaris10_ps->performance_levels
3923                         [polaris10_ps->performance_level_count - 1].memory_clock;
3924         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3925
3926         struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
3927         uint32_t dpm_count, clock_percent;
3928         uint32_t i;
3929
3930         if (0 == data->need_update_smu7_dpm_table)
3931                 return 0;
3932
3933         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3934                 dpm_table->sclk_table.dpm_levels
3935                 [dpm_table->sclk_table.count - 1].value = sclk;
3936
3937                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3938                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3939                 /* Need to do calculation based on the golden DPM table
3940                  * as the Heatmap GPU Clock axis is also based on the default values
3941                  */
3942                         PP_ASSERT_WITH_CODE(
3943                                 (golden_dpm_table->sclk_table.dpm_levels
3944                                                 [golden_dpm_table->sclk_table.count - 1].value != 0),
3945                                 "Divide by 0!",
3946                                 return -1);
3947                         dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
3948
3949                         for (i = dpm_count; i > 1; i--) {
3950                                 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
3951                                         clock_percent =
3952                                               ((sclk
3953                                                 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
3954                                                 ) * 100)
3955                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3956
3957                                         dpm_table->sclk_table.dpm_levels[i].value =
3958                                                         golden_dpm_table->sclk_table.dpm_levels[i].value +
3959                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
3960                                                                 clock_percent)/100;
3961
3962                                 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
3963                                         clock_percent =
3964                                                 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
3965                                                 - sclk) * 100)
3966                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3967
3968                                         dpm_table->sclk_table.dpm_levels[i].value =
3969                                                         golden_dpm_table->sclk_table.dpm_levels[i].value -
3970                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
3971                                                                         clock_percent) / 100;
3972                                 } else
3973                                         dpm_table->sclk_table.dpm_levels[i].value =
3974                                                         golden_dpm_table->sclk_table.dpm_levels[i].value;
3975                         }
3976                 }
3977         }
3978
3979         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3980                 dpm_table->mclk_table.dpm_levels
3981                         [dpm_table->mclk_table.count - 1].value = mclk;
3982
3983                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3984                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3985
3986                         PP_ASSERT_WITH_CODE(
3987                                         (golden_dpm_table->mclk_table.dpm_levels
3988                                                 [golden_dpm_table->mclk_table.count-1].value != 0),
3989                                         "Divide by 0!",
3990                                         return -1);
3991                         dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
3992                         for (i = dpm_count; i > 1; i--) {
3993                                 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
3994                                         clock_percent = ((mclk -
3995                                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
3996                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
3997
3998                                         dpm_table->mclk_table.dpm_levels[i].value =
3999                                                         golden_dpm_table->mclk_table.dpm_levels[i].value +
4000                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4001                                                         clock_percent) / 100;
4002
4003                                 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
4004                                         clock_percent = (
4005                                          (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
4006                                         * 100)
4007                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4008
4009                                         dpm_table->mclk_table.dpm_levels[i].value =
4010                                                         golden_dpm_table->mclk_table.dpm_levels[i].value -
4011                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4012                                                                         clock_percent) / 100;
4013                                 } else
4014                                         dpm_table->mclk_table.dpm_levels[i].value =
4015                                                         golden_dpm_table->mclk_table.dpm_levels[i].value;
4016                         }
4017                 }
4018         }
4019
4020         if (data->need_update_smu7_dpm_table &
4021                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4022                 result = polaris10_populate_all_graphic_levels(hwmgr);
4023                 PP_ASSERT_WITH_CODE((0 == result),
4024                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4025                                 return result);
4026         }
4027
4028         if (data->need_update_smu7_dpm_table &
4029                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4030                 /*populate MCLK dpm table to SMU7 */
4031                 result = polaris10_populate_all_memory_levels(hwmgr);
4032                 PP_ASSERT_WITH_CODE((0 == result),
4033                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4034                                 return result);
4035         }
4036
4037         return result;
4038 }
4039
4040 static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4041                           struct polaris10_single_dpm_table *dpm_table,
4042                         uint32_t low_limit, uint32_t high_limit)
4043 {
4044         uint32_t i;
4045
4046         for (i = 0; i < dpm_table->count; i++) {
4047                 if ((dpm_table->dpm_levels[i].value < low_limit)
4048                 || (dpm_table->dpm_levels[i].value > high_limit))
4049                         dpm_table->dpm_levels[i].enabled = false;
4050                 else
4051                         dpm_table->dpm_levels[i].enabled = true;
4052         }
4053
4054         return 0;
4055 }
4056
4057 static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4058                 const struct polaris10_power_state *polaris10_ps)
4059 {
4060         int result = 0;
4061         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4062         uint32_t high_limit_count;
4063
4064         PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
4065                         "power state did not have any performance level",
4066                         return -1);
4067
4068         high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
4069
4070         polaris10_trim_single_dpm_states(hwmgr,
4071                         &(data->dpm_table.sclk_table),
4072                         polaris10_ps->performance_levels[0].engine_clock,
4073                         polaris10_ps->performance_levels[high_limit_count].engine_clock);
4074
4075         polaris10_trim_single_dpm_states(hwmgr,
4076                         &(data->dpm_table.mclk_table),
4077                         polaris10_ps->performance_levels[0].memory_clock,
4078                         polaris10_ps->performance_levels[high_limit_count].memory_clock);
4079
4080         return result;
4081 }
4082
4083 static int polaris10_generate_dpm_level_enable_mask(
4084                 struct pp_hwmgr *hwmgr, const void *input)
4085 {
4086         int result;
4087         const struct phm_set_power_state_input *states =
4088                         (const struct phm_set_power_state_input *)input;
4089         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4090         const struct polaris10_power_state *polaris10_ps =
4091                         cast_const_phw_polaris10_power_state(states->pnew_state);
4092
4093         result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
4094         if (result)
4095                 return result;
4096
4097         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4098                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4099         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4100                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4101         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4102                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4103
4104         return 0;
4105 }
4106
4107 int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4108 {
4109         return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4110                         PPSMC_MSG_UVDDPM_Enable :
4111                         PPSMC_MSG_UVDDPM_Disable);
4112 }
4113
4114 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4115 {
4116         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4117                         PPSMC_MSG_VCEDPM_Enable :
4118                         PPSMC_MSG_VCEDPM_Disable);
4119 }
4120
4121 int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4122 {
4123         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4124                         PPSMC_MSG_SAMUDPM_Enable :
4125                         PPSMC_MSG_SAMUDPM_Disable);
4126 }
4127
4128 int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4129 {
4130         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4131         uint32_t mm_boot_level_offset, mm_boot_level_value;
4132         struct phm_ppt_v1_information *table_info =
4133                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4134
4135         if (!bgate) {
4136                 data->smc_state_table.UvdBootLevel = 0;
4137                 if (table_info->mm_dep_table->count > 0)
4138                         data->smc_state_table.UvdBootLevel =
4139                                         (uint8_t) (table_info->mm_dep_table->count - 1);
4140                 mm_boot_level_offset = data->dpm_table_start +
4141                                 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4142                 mm_boot_level_offset /= 4;
4143                 mm_boot_level_offset *= 4;
4144                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4145                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4146                 mm_boot_level_value &= 0x00FFFFFF;
4147                 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4148                 cgs_write_ind_register(hwmgr->device,
4149                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4150
4151                 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4152                                 PHM_PlatformCaps_UVDDPM) ||
4153                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4154                                 PHM_PlatformCaps_StablePState))
4155                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4156                                         PPSMC_MSG_UVDDPM_SetEnabledMask,
4157                                         (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4158         }
4159
4160         return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
4161 }
4162
4163 static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4164 {
4165         const struct phm_set_power_state_input *states =
4166                         (const struct phm_set_power_state_input *)input;
4167         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4168         const struct polaris10_power_state *polaris10_nps =
4169                         cast_const_phw_polaris10_power_state(states->pnew_state);
4170         const struct polaris10_power_state *polaris10_cps =
4171                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
4172
4173         uint32_t mm_boot_level_offset, mm_boot_level_value;
4174         struct phm_ppt_v1_information *table_info =
4175                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4176
4177         if (polaris10_nps->vce_clks.evclk > 0 &&
4178         (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
4179
4180                 data->smc_state_table.VceBootLevel =
4181                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4182
4183                 mm_boot_level_offset = data->dpm_table_start +
4184                                 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4185                 mm_boot_level_offset /= 4;
4186                 mm_boot_level_offset *= 4;
4187                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4188                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4189                 mm_boot_level_value &= 0xFF00FFFF;
4190                 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4191                 cgs_write_ind_register(hwmgr->device,
4192                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4193
4194                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4195                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4196                                         PPSMC_MSG_VCEDPM_SetEnabledMask,
4197                                         (uint32_t)1 << data->smc_state_table.VceBootLevel);
4198
4199                         polaris10_enable_disable_vce_dpm(hwmgr, true);
4200                 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4201                                 polaris10_cps != NULL &&
4202                                 polaris10_cps->vce_clks.evclk > 0)
4203                         polaris10_enable_disable_vce_dpm(hwmgr, false);
4204         }
4205
4206         return 0;
4207 }
4208
4209 int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4210 {
4211         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4212         uint32_t mm_boot_level_offset, mm_boot_level_value;
4213
4214         if (!bgate) {
4215                 data->smc_state_table.SamuBootLevel = 0;
4216                 mm_boot_level_offset = data->dpm_table_start +
4217                                 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4218                 mm_boot_level_offset /= 4;
4219                 mm_boot_level_offset *= 4;
4220                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4221                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4222                 mm_boot_level_value &= 0xFFFFFF00;
4223                 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4224                 cgs_write_ind_register(hwmgr->device,
4225                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4226
4227                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4228                                 PHM_PlatformCaps_StablePState))
4229                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4230                                         PPSMC_MSG_SAMUDPM_SetEnabledMask,
4231                                         (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4232         }
4233
4234         return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
4235 }
4236
4237 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4238 {
4239         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4240
4241         int result = 0;
4242         uint32_t low_sclk_interrupt_threshold = 0;
4243
4244         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4245                         PHM_PlatformCaps_SclkThrottleLowNotification)
4246                 && (hwmgr->gfx_arbiter.sclk_threshold !=
4247                                 data->low_sclk_interrupt_threshold)) {
4248                 data->low_sclk_interrupt_threshold =
4249                                 hwmgr->gfx_arbiter.sclk_threshold;
4250                 low_sclk_interrupt_threshold =
4251                                 data->low_sclk_interrupt_threshold;
4252
4253                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4254
4255                 result = polaris10_copy_bytes_to_smc(
4256                                 hwmgr->smumgr,
4257                                 data->dpm_table_start +
4258                                 offsetof(SMU74_Discrete_DpmTable,
4259                                         LowSclkInterruptThreshold),
4260                                 (uint8_t *)&low_sclk_interrupt_threshold,
4261                                 sizeof(uint32_t),
4262                                 data->sram_end);
4263         }
4264
4265         return result;
4266 }
4267
4268 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4269 {
4270         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4271
4272         if (data->need_update_smu7_dpm_table &
4273                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4274                 return polaris10_program_memory_timing_parameters(hwmgr);
4275
4276         return 0;
4277 }
4278
4279 static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4280 {
4281         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4282
4283         if (0 == data->need_update_smu7_dpm_table)
4284                 return 0;
4285
4286         if ((0 == data->sclk_dpm_key_disabled) &&
4287                 (data->need_update_smu7_dpm_table &
4288                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4289
4290                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4291                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4292                                 );
4293                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4294                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4295                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4296                         return -1);
4297         }
4298
4299         if ((0 == data->mclk_dpm_key_disabled) &&
4300                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4301
4302                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4303                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4304                                 );
4305                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4306                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4307                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4308                     return -1);
4309         }
4310
4311         data->need_update_smu7_dpm_table = 0;
4312
4313         return 0;
4314 }
4315
4316 static int polaris10_notify_link_speed_change_after_state_change(
4317                 struct pp_hwmgr *hwmgr, const void *input)
4318 {
4319         const struct phm_set_power_state_input *states =
4320                         (const struct phm_set_power_state_input *)input;
4321         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4322         const struct polaris10_power_state *polaris10_ps =
4323                         cast_const_phw_polaris10_power_state(states->pnew_state);
4324         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
4325         uint8_t  request;
4326
4327         if (data->pspp_notify_required) {
4328                 if (target_link_speed == PP_PCIEGen3)
4329                         request = PCIE_PERF_REQ_GEN3;
4330                 else if (target_link_speed == PP_PCIEGen2)
4331                         request = PCIE_PERF_REQ_GEN2;
4332                 else
4333                         request = PCIE_PERF_REQ_GEN1;
4334
4335                 if (request == PCIE_PERF_REQ_GEN1 &&
4336                                 phm_get_current_pcie_speed(hwmgr) > 0)
4337                         return 0;
4338
4339                 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4340                         if (PP_PCIEGen2 == target_link_speed)
4341                                 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4342                         else
4343                                 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4344                 }
4345         }
4346
4347         return 0;
4348 }
4349
4350 static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4351 {
4352         int tmp_result, result = 0;
4353         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4354
4355         tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4356         PP_ASSERT_WITH_CODE((0 == tmp_result),
4357                         "Failed to find DPM states clocks in DPM table!",
4358                         result = tmp_result);
4359
4360         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4361                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4362                 tmp_result =
4363                         polaris10_request_link_speed_change_before_state_change(hwmgr, input);
4364                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4365                                 "Failed to request link speed change before state change!",
4366                                 result = tmp_result);
4367         }
4368
4369         tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
4370         PP_ASSERT_WITH_CODE((0 == tmp_result),
4371                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4372
4373         tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4374         PP_ASSERT_WITH_CODE((0 == tmp_result),
4375                         "Failed to populate and upload SCLK MCLK DPM levels!",
4376                         result = tmp_result);
4377
4378         tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
4379         PP_ASSERT_WITH_CODE((0 == tmp_result),
4380                         "Failed to generate DPM level enabled mask!",
4381                         result = tmp_result);
4382
4383         tmp_result = polaris10_update_vce_dpm(hwmgr, input);
4384         PP_ASSERT_WITH_CODE((0 == tmp_result),
4385                         "Failed to update VCE DPM!",
4386                         result = tmp_result);
4387
4388         tmp_result = polaris10_update_sclk_threshold(hwmgr);
4389         PP_ASSERT_WITH_CODE((0 == tmp_result),
4390                         "Failed to update SCLK threshold!",
4391                         result = tmp_result);
4392
4393         tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
4394         PP_ASSERT_WITH_CODE((0 == tmp_result),
4395                         "Failed to program memory timing parameters!",
4396                         result = tmp_result);
4397
4398         tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4399         PP_ASSERT_WITH_CODE((0 == tmp_result),
4400                         "Failed to unfreeze SCLK MCLK DPM!",
4401                         result = tmp_result);
4402
4403         tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
4404         PP_ASSERT_WITH_CODE((0 == tmp_result),
4405                         "Failed to upload DPM level enabled mask!",
4406                         result = tmp_result);
4407
4408         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4409                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4410                 tmp_result =
4411                         polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
4412                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4413                                 "Failed to notify link speed change after state change!",
4414                                 result = tmp_result);
4415         }
4416         data->apply_optimized_settings = false;
4417         return result;
4418 }
4419
4420 static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4421 {
4422         hwmgr->thermal_controller.
4423         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4424
4425         if (phm_is_hw_access_blocked(hwmgr))
4426                 return 0;
4427
4428         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4429                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4430 }
4431
4432 int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4433 {
4434         PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4435
4436         return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
4437 }
4438
4439 int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4440 {
4441         uint32_t num_active_displays = 0;
4442         struct cgs_display_info info = {0};
4443         info.mode_info = NULL;
4444
4445         cgs_get_active_displays_info(hwmgr->device, &info);
4446
4447         num_active_displays = info.display_count;
4448
4449         if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4450                 polaris10_notify_smc_display_change(hwmgr, false);
4451         else
4452                 polaris10_notify_smc_display_change(hwmgr, true);
4453
4454         return 0;
4455 }
4456
4457 /**
4458 * Programs the display gap
4459 *
4460 * @param    hwmgr  the address of the powerplay hardware manager.
4461 * @return   always OK
4462 */
4463 int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
4464 {
4465         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4466         uint32_t num_active_displays = 0;
4467         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4468         uint32_t display_gap2;
4469         uint32_t pre_vbi_time_in_us;
4470         uint32_t frame_time_in_us;
4471         uint32_t ref_clock;
4472         uint32_t refresh_rate = 0;
4473         struct cgs_display_info info = {0};
4474         struct cgs_mode_info mode_info;
4475
4476         info.mode_info = &mode_info;
4477
4478         cgs_get_active_displays_info(hwmgr->device, &info);
4479         num_active_displays = info.display_count;
4480
4481         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4482         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4483
4484         ref_clock = mode_info.ref_clock;
4485         refresh_rate = mode_info.refresh_rate;
4486
4487         if (0 == refresh_rate)
4488                 refresh_rate = 60;
4489
4490         frame_time_in_us = 1000000 / refresh_rate;
4491
4492         pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4493         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4494
4495         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4496
4497         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4498
4499         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4500
4501         polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0);
4502
4503         return 0;
4504 }
4505
4506
4507 int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4508 {
4509         return polaris10_program_display_gap(hwmgr);
4510 }
4511
4512 /**
4513 *  Set maximum target operating fan output RPM
4514 *
4515 * @param    hwmgr:  the address of the powerplay hardware manager.
4516 * @param    usMaxFanRpm:  max operating fan RPM value.
4517 * @return   The response that came from the SMC.
4518 */
4519 static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4520 {
4521         hwmgr->thermal_controller.
4522         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4523
4524         if (phm_is_hw_access_blocked(hwmgr))
4525                 return 0;
4526
4527         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4528                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4529 }
4530
4531 int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
4532                                         const void *thermal_interrupt_info)
4533 {
4534         return 0;
4535 }
4536
4537 bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4538 {
4539         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4540         bool is_update_required = false;
4541         struct cgs_display_info info = {0, 0, NULL};
4542
4543         cgs_get_active_displays_info(hwmgr->device, &info);
4544
4545         if (data->display_timing.num_existing_displays != info.display_count)
4546                 is_update_required = true;
4547 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4548         if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4549                 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
4550                 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4551                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4552                                 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4553                         is_update_required = true;
4554 */
4555         return is_update_required;
4556 }
4557
4558 static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4559                                                            const struct polaris10_performance_level *pl2)
4560 {
4561         return ((pl1->memory_clock == pl2->memory_clock) &&
4562                   (pl1->engine_clock == pl2->engine_clock) &&
4563                   (pl1->pcie_gen == pl2->pcie_gen) &&
4564                   (pl1->pcie_lane == pl2->pcie_lane));
4565 }
4566
4567 int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
4568 {
4569         const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4570         const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
4571         int i;
4572
4573         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4574                 return -EINVAL;
4575
4576         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4577         if (psa->performance_level_count != psb->performance_level_count) {
4578                 *equal = false;
4579                 return 0;
4580         }
4581
4582         for (i = 0; i < psa->performance_level_count; i++) {
4583                 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4584                         /* If we have found even one performance level pair that is different the states are different. */
4585                         *equal = false;
4586                         return 0;
4587                 }
4588         }
4589
4590         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4591         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4592         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4593         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4594
4595         return 0;
4596 }
4597
4598 int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
4599 {
4600         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4601
4602         uint32_t vbios_version;
4603
4604         /*  Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4605
4606         phm_get_mc_microcode_version(hwmgr);
4607         vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4608         /*  Full version of MC ucode has already been loaded. */
4609         if (vbios_version == 0) {
4610                 data->need_long_memory_training = false;
4611                 return 0;
4612         }
4613
4614         data->need_long_memory_training = true;
4615
4616 /*
4617  *      PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4618         pfd = &tonga_mcmeFirmware;
4619         if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
4620                 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
4621                                         pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4622                                         pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4623 */
4624         return 0;
4625 }
4626
4627 /**
4628  * Read clock related registers.
4629  *
4630  * @param    hwmgr  the address of the powerplay hardware manager.
4631  * @return   always 0
4632  */
4633 static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
4634 {
4635         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4636
4637         data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4638                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4639                                                 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4640
4641         data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4642                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4643                                                 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4644
4645         data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4646                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4647                                                 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4648
4649         return 0;
4650 }
4651
4652 /**
4653  * Find out if memory is GDDR5.
4654  *
4655  * @param    hwmgr  the address of the powerplay hardware manager.
4656  * @return   always 0
4657  */
4658 static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
4659 {
4660         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4661         uint32_t temp;
4662
4663         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4664
4665         data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4666                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4667                          MC_SEQ_MISC0_GDDR5_SHIFT));
4668
4669         return 0;
4670 }
4671
4672 /**
4673  * Enables Dynamic Power Management by SMC
4674  *
4675  * @param    hwmgr  the address of the powerplay hardware manager.
4676  * @return   always 0
4677  */
4678 static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4679 {
4680         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4681                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
4682
4683         return 0;
4684 }
4685
4686 /**
4687  * Initialize PowerGating States for different engines
4688  *
4689  * @param    hwmgr  the address of the powerplay hardware manager.
4690  * @return   always 0
4691  */
4692 static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
4693 {
4694         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4695
4696         data->uvd_power_gated = false;
4697         data->vce_power_gated = false;
4698         data->samu_power_gated = false;
4699
4700         return 0;
4701 }
4702
4703 static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4704 {
4705         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4706         data->low_sclk_interrupt_threshold = 0;
4707
4708         return 0;
4709 }
4710
4711 int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
4712 {
4713         int tmp_result, result = 0;
4714
4715         polaris10_upload_mc_firmware(hwmgr);
4716
4717         tmp_result = polaris10_read_clock_registers(hwmgr);
4718         PP_ASSERT_WITH_CODE((0 == tmp_result),
4719                         "Failed to read clock registers!", result = tmp_result);
4720
4721         tmp_result = polaris10_get_memory_type(hwmgr);
4722         PP_ASSERT_WITH_CODE((0 == tmp_result),
4723                         "Failed to get memory type!", result = tmp_result);
4724
4725         tmp_result = polaris10_enable_acpi_power_management(hwmgr);
4726         PP_ASSERT_WITH_CODE((0 == tmp_result),
4727                         "Failed to enable ACPI power management!", result = tmp_result);
4728
4729         tmp_result = polaris10_init_power_gate_state(hwmgr);
4730         PP_ASSERT_WITH_CODE((0 == tmp_result),
4731                         "Failed to init power gate state!", result = tmp_result);
4732
4733         tmp_result = phm_get_mc_microcode_version(hwmgr);
4734         PP_ASSERT_WITH_CODE((0 == tmp_result),
4735                         "Failed to get MC microcode version!", result = tmp_result);
4736
4737         tmp_result = polaris10_init_sclk_threshold(hwmgr);
4738         PP_ASSERT_WITH_CODE((0 == tmp_result),
4739                         "Failed to init sclk threshold!", result = tmp_result);
4740
4741         return result;
4742 }
4743
4744 static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
4745 {
4746         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4747
4748         if (!data->soft_pp_table) {
4749                 data->soft_pp_table = kmemdup(hwmgr->soft_pp_table,
4750                                               hwmgr->soft_pp_table_size,
4751                                               GFP_KERNEL);
4752                 if (!data->soft_pp_table)
4753                         return -ENOMEM;
4754         }
4755
4756         *table = (char *)&data->soft_pp_table;
4757
4758         return hwmgr->soft_pp_table_size;
4759 }
4760
4761 static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
4762 {
4763         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4764
4765         if (!data->soft_pp_table) {
4766                 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
4767                 if (!data->soft_pp_table)
4768                         return -ENOMEM;
4769         }
4770
4771         memcpy(data->soft_pp_table, buf, size);
4772
4773         hwmgr->soft_pp_table = data->soft_pp_table;
4774
4775         /* TODO: re-init powerplay to implement modified pptable */
4776
4777         return 0;
4778 }
4779
4780 static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
4781                 enum pp_clock_type type, uint32_t mask)
4782 {
4783         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4784
4785         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
4786                 return -EINVAL;
4787
4788         switch (type) {
4789         case PP_SCLK:
4790                 if (!data->sclk_dpm_key_disabled)
4791                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4792                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
4793                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
4794                 break;
4795         case PP_MCLK:
4796                 if (!data->mclk_dpm_key_disabled)
4797                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4798                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
4799                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
4800                 break;
4801         case PP_PCIE:
4802         {
4803                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4804                 uint32_t level = 0;
4805
4806                 while (tmp >>= 1)
4807                         level++;
4808
4809                 if (!data->pcie_dpm_key_disabled)
4810                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4811                                         PPSMC_MSG_PCIeDPM_ForceLevel,
4812                                         level);
4813                 break;
4814         }
4815         default:
4816                 break;
4817         }
4818
4819         return 0;
4820 }
4821
4822 static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
4823 {
4824         uint32_t speedCntl = 0;
4825
4826         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
4827         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
4828                         ixPCIE_LC_SPEED_CNTL);
4829         return((uint16_t)PHM_GET_FIELD(speedCntl,
4830                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4831 }
4832
4833 static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
4834                 enum pp_clock_type type, char *buf)
4835 {
4836         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4837         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4838         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4839         struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4840         int i, now, size = 0;
4841         uint32_t clock, pcie_speed;
4842
4843         switch (type) {
4844         case PP_SCLK:
4845                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4846                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4847
4848                 for (i = 0; i < sclk_table->count; i++) {
4849                         if (clock > sclk_table->dpm_levels[i].value)
4850                                 continue;
4851                         break;
4852                 }
4853                 now = i;
4854
4855                 for (i = 0; i < sclk_table->count; i++)
4856                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4857                                         i, sclk_table->dpm_levels[i].value / 100,
4858                                         (i == now) ? "*" : "");
4859                 break;
4860         case PP_MCLK:
4861                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4862                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4863
4864                 for (i = 0; i < mclk_table->count; i++) {
4865                         if (clock > mclk_table->dpm_levels[i].value)
4866                                 continue;
4867                         break;
4868                 }
4869                 now = i;
4870
4871                 for (i = 0; i < mclk_table->count; i++)
4872                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4873                                         i, mclk_table->dpm_levels[i].value / 100,
4874                                         (i == now) ? "*" : "");
4875                 break;
4876         case PP_PCIE:
4877                 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
4878                 for (i = 0; i < pcie_table->count; i++) {
4879                         if (pcie_speed != pcie_table->dpm_levels[i].value)
4880                                 continue;
4881                         break;
4882                 }
4883                 now = i;
4884
4885                 for (i = 0; i < pcie_table->count; i++)
4886                         size += sprintf(buf + size, "%d: %s %s\n", i,
4887                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
4888                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
4889                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
4890                                         (i == now) ? "*" : "");
4891                 break;
4892         default:
4893                 break;
4894         }
4895         return size;
4896 }
4897
4898 static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4899 {
4900         if (mode) {
4901                 /* stop auto-manage */
4902                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4903                                 PHM_PlatformCaps_MicrocodeFanControl))
4904                         polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
4905                 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
4906         } else
4907                 /* restart auto-manage */
4908                 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
4909
4910         return 0;
4911 }
4912
4913 static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4914 {
4915         if (hwmgr->fan_ctrl_is_in_default_mode)
4916                 return hwmgr->fan_ctrl_default_mode;
4917         else
4918                 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4919                                 CG_FDO_CTRL2, FDO_PWM_MODE);
4920 }
4921
4922 static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
4923         .backend_init = &polaris10_hwmgr_backend_init,
4924         .backend_fini = &polaris10_hwmgr_backend_fini,
4925         .asic_setup = &polaris10_setup_asic_task,
4926         .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
4927         .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
4928         .force_dpm_level = &polaris10_force_dpm_level,
4929         .power_state_set = polaris10_set_power_state_tasks,
4930         .get_power_state_size = polaris10_get_power_state_size,
4931         .get_mclk = polaris10_dpm_get_mclk,
4932         .get_sclk = polaris10_dpm_get_sclk,
4933         .patch_boot_state = polaris10_dpm_patch_boot_state,
4934         .get_pp_table_entry = polaris10_get_pp_table_entry,
4935         .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
4936         .print_current_perforce_level = polaris10_print_current_perforce_level,
4937         .powerdown_uvd = polaris10_phm_powerdown_uvd,
4938         .powergate_uvd = polaris10_phm_powergate_uvd,
4939         .powergate_vce = polaris10_phm_powergate_vce,
4940         .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
4941         .update_clock_gatings = polaris10_phm_update_clock_gatings,
4942         .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
4943         .display_config_changed = polaris10_display_configuration_changed_task,
4944         .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
4945         .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
4946         .get_temperature = polaris10_thermal_get_temperature,
4947         .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
4948         .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
4949         .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
4950         .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
4951         .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
4952         .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
4953         .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
4954         .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
4955         .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
4956         .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
4957         .check_states_equal = polaris10_check_states_equal,
4958         .set_fan_control_mode = polaris10_set_fan_control_mode,
4959         .get_fan_control_mode = polaris10_get_fan_control_mode,
4960         .get_pp_table = polaris10_get_pp_table,
4961         .set_pp_table = polaris10_set_pp_table,
4962         .force_clock_level = polaris10_force_clock_level,
4963         .print_clock_levels = polaris10_print_clock_levels,
4964         .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
4965 };
4966
4967 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
4968 {
4969         struct polaris10_hwmgr  *data;
4970
4971         data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL);
4972         if (data == NULL)
4973                 return -ENOMEM;
4974
4975         hwmgr->backend = data;
4976         hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
4977         hwmgr->pptable_func = &tonga_pptable_funcs;
4978         pp_polaris10_thermal_initialize(hwmgr);
4979
4980         return 0;
4981 }