drivers/gpu/drm/armada/armada_crtc.c

   1 /*
   2  * Copyright (C) 2012 Russell King
   3  *  Rewritten from the dovefb driver, and Armada510 manuals.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <drm/drmP.h>
  14 #include <drm/drm_crtc_helper.h>
  15 #include <drm/drm_plane_helper.h>
  16 #include "armada_crtc.h"
  17 #include "armada_drm.h"
  18 #include "armada_fb.h"
  19 #include "armada_gem.h"
  20 #include "armada_hw.h"
  21
  22 struct armada_frame_work {
  23         struct armada_plane_work work;
  24         struct drm_pending_vblank_event *event;
  25         struct armada_regs regs[4];
  26         struct drm_framebuffer *old_fb;
  27 };
  28
  29 enum csc_mode {
  30         CSC_AUTO = 0,
  31         CSC_YUV_CCIR601 = 1,
  32         CSC_YUV_CCIR709 = 2,
  33         CSC_RGB_COMPUTER = 1,
  34         CSC_RGB_STUDIO = 2,
  35 };
  36
  37 static const uint32_t armada_primary_formats[] = {
  38         DRM_FORMAT_UYVY,
  39         DRM_FORMAT_YUYV,
  40         DRM_FORMAT_VYUY,
  41         DRM_FORMAT_YVYU,
  42         DRM_FORMAT_ARGB8888,
  43         DRM_FORMAT_ABGR8888,
  44         DRM_FORMAT_XRGB8888,
  45         DRM_FORMAT_XBGR8888,
  46         DRM_FORMAT_RGB888,
  47         DRM_FORMAT_BGR888,
  48         DRM_FORMAT_ARGB1555,
  49         DRM_FORMAT_ABGR1555,
  50         DRM_FORMAT_RGB565,
  51         DRM_FORMAT_BGR565,
  52 };
  53
  54 /*
  55  * A note about interlacing.  Let's consider HDMI 1920x1080i.
  56  * The timing parameters we have from X are:
  57  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  58  *  1920 2448 2492 2640  1080 1084 1094 1125
  59  * Which get translated to:
  60  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  61  *  1920 2448 2492 2640   540  542  547  562
  62  *
  63  * This is how it is defined by CEA-861-D - line and pixel numbers are
  64  * referenced to the rising edge of VSYNC and HSYNC.  Total clocks per
  65  * line: 2640.  The odd frame, the first active line is at line 21, and
  66  * the even frame, the first active line is 584.
  67  *
  68  * LN:    560     561     562     563             567     568    569
  69  * DE:    ~~~|____________________________//__________________________
  70  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  71  * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
  72  *  22 blanking lines.  VSYNC at 1320 (referenced to the HSYNC rising edge).
  73  *
  74  * LN:    1123   1124    1125      1               5       6      7
  75  * DE:    ~~~|____________________________//__________________________
  76  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  77  * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
  78  *  23 blanking lines
  79  *
  80  * The Armada LCD Controller line and pixel numbers are, like X timings,
  81  * referenced to the top left of the active frame.
  82  *
  83  * So, translating these to our LCD controller:
  84  *  Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
  85  *  Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
  86  * Note: Vsync front porch remains constant!
  87  *
  88  * if (odd_frame) {
  89  *   vtotal = mode->crtc_vtotal + 1;
  90  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
  91  *   vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
  92  * } else {
  93  *   vtotal = mode->crtc_vtotal;
  94  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
  95  *   vhorizpos = mode->crtc_hsync_start;
  96  * }
  97  * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
  98  *
  99  * So, we need to reprogram these registers on each vsync event:
 100  *  LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
 101  *
 102  * Note: we do not use the frame done interrupts because these appear
 103  * to happen too early, and lead to jitter on the display (presumably
 104  * they occur at the end of the last active line, before the vsync back
 105  * porch, which we're reprogramming.)
 106  */
 107
 108 void
 109 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
 110 {
 111         while (regs->offset != ~0) {
 112                 void __iomem *reg = dcrtc->base + regs->offset;
 113                 uint32_t val;
 114
 115                 val = regs->mask;
 116                 if (val != 0)
 117                         val &= readl_relaxed(reg);
 118                 writel_relaxed(val | regs->val, reg);
 119                 ++regs;
 120         }
 121 }
 122
 123 #define dpms_blanked(dpms)      ((dpms) != DRM_MODE_DPMS_ON)
 124
 125 static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
 126 {
 127         uint32_t dumb_ctrl;
 128
 129         dumb_ctrl = dcrtc->cfg_dumb_ctrl;
 130
 131         if (!dpms_blanked(dcrtc->dpms))
 132                 dumb_ctrl |= CFG_DUMB_ENA;
 133
 134         /*
 135          * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
 136          * be using SPI or GPIO.  If we set this to DUMB_BLANK, we will
 137          * force LCD_D[23:0] to output blank color, overriding the GPIO or
 138          * SPI usage.  So leave it as-is unless in DUMB24_RGB888_0 mode.
 139          */
 140         if (dpms_blanked(dcrtc->dpms) &&
 141             (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
 142                 dumb_ctrl &= ~DUMB_MASK;
 143                 dumb_ctrl |= DUMB_BLANK;
 144         }
 145
 146         /*
 147          * The documentation doesn't indicate what the normal state of
 148          * the sync signals are.  Sebastian Hesselbart kindly probed
 149          * these signals on his board to determine their state.
 150          *
 151          * The non-inverted state of the sync signals is active high.
 152          * Setting these bits makes the appropriate signal active low.
 153          */
 154         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
 155                 dumb_ctrl |= CFG_INV_CSYNC;
 156         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
 157                 dumb_ctrl |= CFG_INV_HSYNC;
 158         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
 159                 dumb_ctrl |= CFG_INV_VSYNC;
 160
 161         if (dcrtc->dumb_ctrl != dumb_ctrl) {
 162                 dcrtc->dumb_ctrl = dumb_ctrl;
 163                 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
 164         }
 165 }
 166
 167 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
 168         int x, int y, struct armada_regs *regs, bool interlaced)
 169 {
 170         struct armada_gem_object *obj = drm_fb_obj(fb);
 171         unsigned pitch = fb->pitches[0];
 172         unsigned offset = y * pitch + x * fb->bits_per_pixel / 8;
 173         uint32_t addr_odd, addr_even;
 174         unsigned i = 0;
 175
 176         DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
 177                 pitch, x, y, fb->bits_per_pixel);
 178
 179         addr_odd = addr_even = obj->dev_addr + offset;
 180
 181         if (interlaced) {
 182                 addr_even += pitch;
 183                 pitch *= 2;
 184         }
 185
 186         /* write offset, base, and pitch */
 187         armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
 188         armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
 189         armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
 190
 191         return i;
 192 }
 193
 194 static void armada_drm_plane_work_run(struct armada_crtc *dcrtc,
 195         struct armada_plane *plane)
 196 {
 197         struct armada_plane_work *work = xchg(&plane->work, NULL);
 198
 199         /* Handle any pending frame work. */
 200         if (work) {
 201                 work->fn(dcrtc, plane, work);
 202                 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
 203         }
 204 }
 205
 206 int armada_drm_plane_work_queue(struct armada_crtc *dcrtc,
 207         struct armada_plane *plane, struct armada_plane_work *work)
 208 {
 209         int ret;
 210
 211         ret = drm_vblank_get(dcrtc->crtc.dev, dcrtc->num);
 212         if (ret) {
 213                 DRM_ERROR("failed to acquire vblank counter\n");
 214                 return ret;
 215         }
 216
 217         ret = cmpxchg(&plane->work, NULL, work) ? -EBUSY : 0;
 218         if (ret)
 219                 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
 220
 221         return ret;
 222 }
 223
 224 int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout)
 225 {
 226         return wait_event_timeout(plane->frame_wait, !plane->work, timeout);
 227 }
 228
 229 void armada_drm_vbl_event_add(struct armada_crtc *dcrtc,
 230         struct armada_vbl_event *evt)
 231 {
 232         unsigned long flags;
 233         bool not_on_list;
 234
 235         WARN_ON(drm_vblank_get(dcrtc->crtc.dev, dcrtc->num));
 236
 237         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 238         not_on_list = list_empty(&evt->node);
 239         if (not_on_list)
 240                 list_add_tail(&evt->node, &dcrtc->vbl_list);
 241         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 242
 243         if (!not_on_list)
 244                 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
 245 }
 246
 247 void armada_drm_vbl_event_remove(struct armada_crtc *dcrtc,
 248         struct armada_vbl_event *evt)
 249 {
 250         spin_lock_irq(&dcrtc->irq_lock);
 251         if (!list_empty(&evt->node)) {
 252                 list_del_init(&evt->node);
 253                 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
 254         }
 255         spin_unlock_irq(&dcrtc->irq_lock);
 256 }
 257
 258 static void armada_drm_vbl_event_run(struct armada_crtc *dcrtc)
 259 {
 260         struct armada_vbl_event *e, *n;
 261
 262         list_for_each_entry_safe(e, n, &dcrtc->vbl_list, node) {
 263                 list_del_init(&e->node);
 264                 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
 265                 e->fn(dcrtc, e->data);
 266         }
 267 }
 268
 269 static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc,
 270         struct armada_frame_work *work)
 271 {
 272         struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary);
 273
 274         return armada_drm_plane_work_queue(dcrtc, plane, &work->work);
 275 }
 276
 277 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc,
 278         struct armada_plane *plane, struct armada_plane_work *work)
 279 {
 280         struct armada_frame_work *fwork = container_of(work, struct armada_frame_work, work);
 281         struct drm_device *dev = dcrtc->crtc.dev;
 282         unsigned long flags;
 283
 284         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 285         armada_drm_crtc_update_regs(dcrtc, fwork->regs);
 286         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 287
 288         if (fwork->event) {
 289                 spin_lock_irqsave(&dev->event_lock, flags);
 290                 drm_send_vblank_event(dev, dcrtc->num, fwork->event);
 291                 spin_unlock_irqrestore(&dev->event_lock, flags);
 292         }
 293
 294         /* Finally, queue the process-half of the cleanup. */
 295         __armada_drm_queue_unref_work(dcrtc->crtc.dev, fwork->old_fb);
 296         kfree(fwork);
 297 }
 298
 299 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
 300         struct drm_framebuffer *fb, bool force)
 301 {
 302         struct armada_frame_work *work;
 303
 304         if (!fb)
 305                 return;
 306
 307         if (force) {
 308                 /* Display is disabled, so just drop the old fb */
 309                 drm_framebuffer_unreference(fb);
 310                 return;
 311         }
 312
 313         work = kmalloc(sizeof(*work), GFP_KERNEL);
 314         if (work) {
 315                 int i = 0;
 316                 work->work.fn = armada_drm_crtc_complete_frame_work;
 317                 work->event = NULL;
 318                 work->old_fb = fb;
 319                 armada_reg_queue_end(work->regs, i);
 320
 321                 if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0)
 322                         return;
 323
 324                 kfree(work);
 325         }
 326
 327         /*
 328          * Oops - just drop the reference immediately and hope for
 329          * the best.  The worst that will happen is the buffer gets
 330          * reused before it has finished being displayed.
 331          */
 332         drm_framebuffer_unreference(fb);
 333 }
 334
 335 static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
 336 {
 337         struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary);
 338
 339         /*
 340          * Tell the DRM core that vblank IRQs aren't going to happen for
 341          * a while.  This cleans up any pending vblank events for us.
 342          */
 343         drm_crtc_vblank_off(&dcrtc->crtc);
 344         armada_drm_plane_work_run(dcrtc, plane);
 345 }
 346
 347 void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b,
 348         int idx)
 349 {
 350 }
 351
 352 void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 353         int idx)
 354 {
 355 }
 356
 357 /* The mode_config.mutex will be held for this call */
 358 static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
 359 {
 360         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 361
 362         if (dcrtc->dpms != dpms) {
 363                 dcrtc->dpms = dpms;
 364                 if (!IS_ERR(dcrtc->clk) && !dpms_blanked(dpms))
 365                         WARN_ON(clk_prepare_enable(dcrtc->clk));
 366                 armada_drm_crtc_update(dcrtc);
 367                 if (!IS_ERR(dcrtc->clk) && dpms_blanked(dpms))
 368                         clk_disable_unprepare(dcrtc->clk);
 369                 if (dpms_blanked(dpms))
 370                         armada_drm_vblank_off(dcrtc);
 371                 else
 372                         drm_crtc_vblank_on(&dcrtc->crtc);
 373         }
 374 }
 375
 376 /*
 377  * Prepare for a mode set.  Turn off overlay to ensure that we don't end
 378  * up with the overlay size being bigger than the active screen size.
 379  * We rely upon X refreshing this state after the mode set has completed.
 380  *
 381  * The mode_config.mutex will be held for this call
 382  */
 383 static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
 384 {
 385         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 386         struct drm_plane *plane;
 387
 388         /*
 389          * If we have an overlay plane associated with this CRTC, disable
 390          * it before the modeset to avoid its coordinates being outside
 391          * the new mode parameters.
 392          */
 393         plane = dcrtc->plane;
 394         if (plane)
 395                 drm_plane_force_disable(plane);
 396 }
 397
 398 /* The mode_config.mutex will be held for this call */
 399 static void armada_drm_crtc_commit(struct drm_crtc *crtc)
 400 {
 401         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 402
 403         if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
 404                 dcrtc->dpms = DRM_MODE_DPMS_ON;
 405                 armada_drm_crtc_update(dcrtc);
 406         }
 407 }
 408
 409 /* The mode_config.mutex will be held for this call */
 410 static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
 411         const struct drm_display_mode *mode, struct drm_display_mode *adj)
 412 {
 413         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 414         int ret;
 415
 416         /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
 417         if (!dcrtc->variant->has_spu_adv_reg &&
 418             adj->flags & DRM_MODE_FLAG_INTERLACE)
 419                 return false;
 420
 421         /* Check whether the display mode is possible */
 422         ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
 423         if (ret)
 424                 return false;
 425
 426         return true;
 427 }
 428
 429 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
 430 {
 431         void __iomem *base = dcrtc->base;
 432
 433         if (stat & DMA_FF_UNDERFLOW)
 434                 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
 435         if (stat & GRA_FF_UNDERFLOW)
 436                 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
 437
 438         if (stat & VSYNC_IRQ)
 439                 drm_handle_vblank(dcrtc->crtc.dev, dcrtc->num);
 440
 441         spin_lock(&dcrtc->irq_lock);
 442         armada_drm_vbl_event_run(dcrtc);
 443
 444         if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
 445                 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
 446                 uint32_t val;
 447
 448                 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
 449                 writel_relaxed(dcrtc->v[i].spu_v_h_total,
 450                                base + LCD_SPUT_V_H_TOTAL);
 451
 452                 val = readl_relaxed(base + LCD_SPU_ADV_REG);
 453                 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
 454                 val |= dcrtc->v[i].spu_adv_reg;
 455                 writel_relaxed(val, base + LCD_SPU_ADV_REG);
 456         }
 457
 458         if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
 459                 writel_relaxed(dcrtc->cursor_hw_pos,
 460                                base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 461                 writel_relaxed(dcrtc->cursor_hw_sz,
 462                                base + LCD_SPU_HWC_HPXL_VLN);
 463                 armada_updatel(CFG_HWC_ENA,
 464                                CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
 465                                base + LCD_SPU_DMA_CTRL0);
 466                 dcrtc->cursor_update = false;
 467                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 468         }
 469
 470         spin_unlock(&dcrtc->irq_lock);
 471
 472         if (stat & GRA_FRAME_IRQ) {
 473                 struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary);
 474                 armada_drm_plane_work_run(dcrtc, plane);
 475                 wake_up(&plane->frame_wait);
 476         }
 477 }
 478
 479 static irqreturn_t armada_drm_irq(int irq, void *arg)
 480 {
 481         struct armada_crtc *dcrtc = arg;
 482         u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
 483
 484         /*
 485          * This is rediculous - rather than writing bits to clear, we
 486          * have to set the actual status register value.  This is racy.
 487          */
 488         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 489
 490         /* Mask out those interrupts we haven't enabled */
 491         v = stat & dcrtc->irq_ena;
 492
 493         if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
 494                 armada_drm_crtc_irq(dcrtc, stat);
 495                 return IRQ_HANDLED;
 496         }
 497         return IRQ_NONE;
 498 }
 499
 500 /* These are locked by dev->vbl_lock */
 501 void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
 502 {
 503         if (dcrtc->irq_ena & mask) {
 504                 dcrtc->irq_ena &= ~mask;
 505                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 506         }
 507 }
 508
 509 void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
 510 {
 511         if ((dcrtc->irq_ena & mask) != mask) {
 512                 dcrtc->irq_ena |= mask;
 513                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 514                 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
 515                         writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 516         }
 517 }
 518
 519 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
 520 {
 521         struct drm_display_mode *adj = &dcrtc->crtc.mode;
 522         uint32_t val = 0;
 523
 524         if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
 525                 val |= CFG_CSC_YUV_CCIR709;
 526         if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
 527                 val |= CFG_CSC_RGB_STUDIO;
 528
 529         /*
 530          * In auto mode, set the colorimetry, based upon the HDMI spec.
 531          * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
 532          * ITU601.  It may be more appropriate to set this depending on
 533          * the source - but what if the graphic frame is YUV and the
 534          * video frame is RGB?
 535          */
 536         if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
 537              !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
 538             (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
 539                 if (dcrtc->csc_yuv_mode == CSC_AUTO)
 540                         val |= CFG_CSC_YUV_CCIR709;
 541         }
 542
 543         /*
 544          * We assume we're connected to a TV-like device, so the YUV->RGB
 545          * conversion should produce a limited range.  We should set this
 546          * depending on the connectors attached to this CRTC, and what
 547          * kind of device they report being connected.
 548          */
 549         if (dcrtc->csc_rgb_mode == CSC_AUTO)
 550                 val |= CFG_CSC_RGB_STUDIO;
 551
 552         return val;
 553 }
 554
 555 /* The mode_config.mutex will be held for this call */
 556 static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
 557         struct drm_display_mode *mode, struct drm_display_mode *adj,
 558         int x, int y, struct drm_framebuffer *old_fb)
 559 {
 560         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 561         struct armada_regs regs[17];
 562         uint32_t lm, rm, tm, bm, val, sclk;
 563         unsigned long flags;
 564         unsigned i;
 565         bool interlaced;
 566
 567         drm_framebuffer_reference(crtc->primary->fb);
 568
 569         interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
 570
 571         i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb,
 572                                     x, y, regs, interlaced);
 573
 574         rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
 575         lm = adj->crtc_htotal - adj->crtc_hsync_end;
 576         bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
 577         tm = adj->crtc_vtotal - adj->crtc_vsync_end;
 578
 579         DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
 580                 adj->crtc_hdisplay,
 581                 adj->crtc_hsync_start,
 582                 adj->crtc_hsync_end,
 583                 adj->crtc_htotal, lm, rm);
 584         DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
 585                 adj->crtc_vdisplay,
 586                 adj->crtc_vsync_start,
 587                 adj->crtc_vsync_end,
 588                 adj->crtc_vtotal, tm, bm);
 589
 590         /* Wait for pending flips to complete */
 591         armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
 592                                    MAX_SCHEDULE_TIMEOUT);
 593
 594         drm_crtc_vblank_off(crtc);
 595
 596         val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
 597         if (val != dcrtc->dumb_ctrl) {
 598                 dcrtc->dumb_ctrl = val;
 599                 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
 600         }
 601
 602         /*
 603          * If we are blanked, we would have disabled the clock.  Re-enable
 604          * it so that compute_clock() does the right thing.
 605          */
 606         if (!IS_ERR(dcrtc->clk) && dpms_blanked(dcrtc->dpms))
 607                 WARN_ON(clk_prepare_enable(dcrtc->clk));
 608
 609         /* Now compute the divider for real */
 610         dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
 611
 612         /* Ensure graphic fifo is enabled */
 613         armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
 614         armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
 615
 616         if (interlaced ^ dcrtc->interlaced) {
 617                 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
 618                         drm_vblank_get(dcrtc->crtc.dev, dcrtc->num);
 619                 else
 620                         drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
 621                 dcrtc->interlaced = interlaced;
 622         }
 623
 624         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 625
 626         /* Even interlaced/progressive frame */
 627         dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
 628                                     adj->crtc_htotal;
 629         dcrtc->v[1].spu_v_porch = tm << 16 | bm;
 630         val = adj->crtc_hsync_start;
 631         dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 632                 dcrtc->variant->spu_adv_reg;
 633
 634         if (interlaced) {
 635                 /* Odd interlaced frame */
 636                 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
 637                                                 (1 << 16);
 638                 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
 639                 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
 640                 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 641                         dcrtc->variant->spu_adv_reg;
 642         } else {
 643                 dcrtc->v[0] = dcrtc->v[1];
 644         }
 645
 646         val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
 647
 648         armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
 649         armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN);
 650         armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN);
 651         armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
 652         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
 653         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
 654                            LCD_SPUT_V_H_TOTAL);
 655
 656         if (dcrtc->variant->has_spu_adv_reg) {
 657                 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
 658                                      ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
 659                                      ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
 660         }
 661
 662         val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
 663         val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
 664         val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
 665
 666         if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
 667                 val |= CFG_PALETTE_ENA;
 668
 669         if (interlaced)
 670                 val |= CFG_GRA_FTOGGLE;
 671
 672         armada_reg_queue_mod(regs, i, val, CFG_GRAFORMAT |
 673                              CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
 674                                          CFG_SWAPYU | CFG_YUV2RGB) |
 675                              CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
 676                              LCD_SPU_DMA_CTRL0);
 677
 678         val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
 679         armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
 680
 681         val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
 682         armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
 683         armada_reg_queue_end(regs, i);
 684
 685         armada_drm_crtc_update_regs(dcrtc, regs);
 686         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 687
 688         armada_drm_crtc_update(dcrtc);
 689
 690         drm_crtc_vblank_on(crtc);
 691         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 692
 693         return 0;
 694 }
 695
 696 /* The mode_config.mutex will be held for this call */
 697 static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 698         struct drm_framebuffer *old_fb)
 699 {
 700         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 701         struct armada_regs regs[4];
 702         unsigned i;
 703
 704         i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs,
 705                                     dcrtc->interlaced);
 706         armada_reg_queue_end(regs, i);
 707
 708         /* Wait for pending flips to complete */
 709         armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
 710                                    MAX_SCHEDULE_TIMEOUT);
 711
 712         /* Take a reference to the new fb as we're using it */
 713         drm_framebuffer_reference(crtc->primary->fb);
 714
 715         /* Update the base in the CRTC */
 716         armada_drm_crtc_update_regs(dcrtc, regs);
 717
 718         /* Drop our previously held reference */
 719         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 720
 721         return 0;
 722 }
 723
 724 void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc,
 725         struct drm_plane *plane)
 726 {
 727         u32 sram_para1, dma_ctrl0_mask;
 728
 729         /*
 730          * Drop our reference on any framebuffer attached to this plane.
 731          * We don't need to NULL this out as drm_plane_force_disable(),
 732          * and __setplane_internal() will do so for an overlay plane, and
 733          * __drm_helper_disable_unused_functions() will do so for the
 734          * primary plane.
 735          */
 736         if (plane->fb)
 737                 drm_framebuffer_unreference(plane->fb);
 738
 739         /* Power down the Y/U/V FIFOs */
 740         sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66;
 741
 742         /* Power down most RAMs and FIFOs if this is the primary plane */
 743         if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
 744                 sram_para1 |= CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
 745                               CFG_PDWN32x32 | CFG_PDWN64x66;
 746                 dma_ctrl0_mask = CFG_GRA_ENA;
 747         } else {
 748                 dma_ctrl0_mask = CFG_DMA_ENA;
 749         }
 750
 751         spin_lock_irq(&dcrtc->irq_lock);
 752         armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0);
 753         spin_unlock_irq(&dcrtc->irq_lock);
 754
 755         armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1);
 756 }
 757
 758 /* The mode_config.mutex will be held for this call */
 759 static void armada_drm_crtc_disable(struct drm_crtc *crtc)
 760 {
 761         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 762
 763         armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 764         armada_drm_crtc_plane_disable(dcrtc, crtc->primary);
 765 }
 766
 767 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
 768         .dpms           = armada_drm_crtc_dpms,
 769         .prepare        = armada_drm_crtc_prepare,
 770         .commit         = armada_drm_crtc_commit,
 771         .mode_fixup     = armada_drm_crtc_mode_fixup,
 772         .mode_set       = armada_drm_crtc_mode_set,
 773         .mode_set_base  = armada_drm_crtc_mode_set_base,
 774         .disable        = armada_drm_crtc_disable,
 775 };
 776
 777 static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
 778         unsigned stride, unsigned width, unsigned height)
 779 {
 780         uint32_t addr;
 781         unsigned y;
 782
 783         addr = SRAM_HWC32_RAM1;
 784         for (y = 0; y < height; y++) {
 785                 uint32_t *p = &pix[y * stride];
 786                 unsigned x;
 787
 788                 for (x = 0; x < width; x++, p++) {
 789                         uint32_t val = *p;
 790
 791                         val = (val & 0xff00ff00) |
 792                               (val & 0x000000ff) << 16 |
 793                               (val & 0x00ff0000) >> 16;
 794
 795                         writel_relaxed(val,
 796                                        base + LCD_SPU_SRAM_WRDAT);
 797                         writel_relaxed(addr | SRAM_WRITE,
 798                                        base + LCD_SPU_SRAM_CTRL);
 799                         readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 800                         addr += 1;
 801                         if ((addr & 0x00ff) == 0)
 802                                 addr += 0xf00;
 803                         if ((addr & 0x30ff) == 0)
 804                                 addr = SRAM_HWC32_RAM2;
 805                 }
 806         }
 807 }
 808
 809 static void armada_drm_crtc_cursor_tran(void __iomem *base)
 810 {
 811         unsigned addr;
 812
 813         for (addr = 0; addr < 256; addr++) {
 814                 /* write the default value */
 815                 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
 816                 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
 817                                base + LCD_SPU_SRAM_CTRL);
 818         }
 819 }
 820
 821 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
 822 {
 823         uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
 824         uint32_t yoff, yscr, h = dcrtc->cursor_h;
 825         uint32_t para1;
 826
 827         /*
 828          * Calculate the visible width and height of the cursor,
 829          * screen position, and the position in the cursor bitmap.
 830          */
 831         if (dcrtc->cursor_x < 0) {
 832                 xoff = -dcrtc->cursor_x;
 833                 xscr = 0;
 834                 w -= min(xoff, w);
 835         } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
 836                 xoff = 0;
 837                 xscr = dcrtc->cursor_x;
 838                 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
 839         } else {
 840                 xoff = 0;
 841                 xscr = dcrtc->cursor_x;
 842         }
 843
 844         if (dcrtc->cursor_y < 0) {
 845                 yoff = -dcrtc->cursor_y;
 846                 yscr = 0;
 847                 h -= min(yoff, h);
 848         } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
 849                 yoff = 0;
 850                 yscr = dcrtc->cursor_y;
 851                 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
 852         } else {
 853                 yoff = 0;
 854                 yscr = dcrtc->cursor_y;
 855         }
 856
 857         /* On interlaced modes, the vertical cursor size must be halved */
 858         s = dcrtc->cursor_w;
 859         if (dcrtc->interlaced) {
 860                 s *= 2;
 861                 yscr /= 2;
 862                 h /= 2;
 863         }
 864
 865         if (!dcrtc->cursor_obj || !h || !w) {
 866                 spin_lock_irq(&dcrtc->irq_lock);
 867                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 868                 dcrtc->cursor_update = false;
 869                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 870                 spin_unlock_irq(&dcrtc->irq_lock);
 871                 return 0;
 872         }
 873
 874         para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
 875         armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
 876                        dcrtc->base + LCD_SPU_SRAM_PARA1);
 877
 878         /*
 879          * Initialize the transparency if the SRAM was powered down.
 880          * We must also reload the cursor data as well.
 881          */
 882         if (!(para1 & CFG_CSB_256x32)) {
 883                 armada_drm_crtc_cursor_tran(dcrtc->base);
 884                 reload = true;
 885         }
 886
 887         if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
 888                 spin_lock_irq(&dcrtc->irq_lock);
 889                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 890                 dcrtc->cursor_update = false;
 891                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 892                 spin_unlock_irq(&dcrtc->irq_lock);
 893                 reload = true;
 894         }
 895         if (reload) {
 896                 struct armada_gem_object *obj = dcrtc->cursor_obj;
 897                 uint32_t *pix;
 898                 /* Set the top-left corner of the cursor image */
 899                 pix = obj->addr;
 900                 pix += yoff * s + xoff;
 901                 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
 902         }
 903
 904         /* Reload the cursor position, size and enable in the IRQ handler */
 905         spin_lock_irq(&dcrtc->irq_lock);
 906         dcrtc->cursor_hw_pos = yscr << 16 | xscr;
 907         dcrtc->cursor_hw_sz = h << 16 | w;
 908         dcrtc->cursor_update = true;
 909         armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 910         spin_unlock_irq(&dcrtc->irq_lock);
 911
 912         return 0;
 913 }
 914
 915 static void cursor_update(void *data)
 916 {
 917         armada_drm_crtc_cursor_update(data, true);
 918 }
 919
 920 static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
 921         struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
 922 {
 923         struct drm_device *dev = crtc->dev;
 924         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 925         struct armada_gem_object *obj = NULL;
 926         int ret;
 927
 928         /* If no cursor support, replicate drm's return value */
 929         if (!dcrtc->variant->has_spu_adv_reg)
 930                 return -ENXIO;
 931
 932         if (handle && w > 0 && h > 0) {
 933                 /* maximum size is 64x32 or 32x64 */
 934                 if (w > 64 || h > 64 || (w > 32 && h > 32))
 935                         return -ENOMEM;
 936
 937                 obj = armada_gem_object_lookup(dev, file, handle);
 938                 if (!obj)
 939                         return -ENOENT;
 940
 941                 /* Must be a kernel-mapped object */
 942                 if (!obj->addr) {
 943                         drm_gem_object_unreference_unlocked(&obj->obj);
 944                         return -EINVAL;
 945                 }
 946
 947                 if (obj->obj.size < w * h * 4) {
 948                         DRM_ERROR("buffer is too small\n");
 949                         drm_gem_object_unreference_unlocked(&obj->obj);
 950                         return -ENOMEM;
 951                 }
 952         }
 953
 954         mutex_lock(&dev->struct_mutex);
 955         if (dcrtc->cursor_obj) {
 956                 dcrtc->cursor_obj->update = NULL;
 957                 dcrtc->cursor_obj->update_data = NULL;
 958                 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
 959         }
 960         dcrtc->cursor_obj = obj;
 961         dcrtc->cursor_w = w;
 962         dcrtc->cursor_h = h;
 963         ret = armada_drm_crtc_cursor_update(dcrtc, true);
 964         if (obj) {
 965                 obj->update_data = dcrtc;
 966                 obj->update = cursor_update;
 967         }
 968         mutex_unlock(&dev->struct_mutex);
 969
 970         return ret;
 971 }
 972
 973 static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 974 {
 975         struct drm_device *dev = crtc->dev;
 976         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 977         int ret;
 978
 979         /* If no cursor support, replicate drm's return value */
 980         if (!dcrtc->variant->has_spu_adv_reg)
 981                 return -EFAULT;
 982
 983         mutex_lock(&dev->struct_mutex);
 984         dcrtc->cursor_x = x;
 985         dcrtc->cursor_y = y;
 986         ret = armada_drm_crtc_cursor_update(dcrtc, false);
 987         mutex_unlock(&dev->struct_mutex);
 988
 989         return ret;
 990 }
 991
 992 static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
 993 {
 994         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 995         struct armada_private *priv = crtc->dev->dev_private;
 996
 997         if (dcrtc->cursor_obj)
 998                 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
 999
1000         priv->dcrtc[dcrtc->num] = NULL;
1001         drm_crtc_cleanup(&dcrtc->crtc);
1002
1003         if (!IS_ERR(dcrtc->clk))
1004                 clk_disable_unprepare(dcrtc->clk);
1005
1006         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
1007
1008         of_node_put(dcrtc->crtc.port);
1009
1010         kfree(dcrtc);
1011 }
1012
1013 /*
1014  * The mode_config lock is held here, to prevent races between this
1015  * and a mode_set.
1016  */
1017 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
1018         struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
1019 {
1020         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1021         struct armada_frame_work *work;
1022         unsigned i;
1023         int ret;
1024
1025         /* We don't support changing the pixel format */
1026         if (fb->pixel_format != crtc->primary->fb->pixel_format)
1027                 return -EINVAL;
1028
1029         work = kmalloc(sizeof(*work), GFP_KERNEL);
1030         if (!work)
1031                 return -ENOMEM;
1032
1033         work->work.fn = armada_drm_crtc_complete_frame_work;
1034         work->event = event;
1035         work->old_fb = dcrtc->crtc.primary->fb;
1036
1037         i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
1038                                     dcrtc->interlaced);
1039         armada_reg_queue_end(work->regs, i);
1040
1041         /*
1042          * Ensure that we hold a reference on the new framebuffer.
1043          * This has to match the behaviour in mode_set.
1044          */
1045         drm_framebuffer_reference(fb);
1046
1047         ret = armada_drm_crtc_queue_frame_work(dcrtc, work);
1048         if (ret) {
1049                 /* Undo our reference above */
1050                 drm_framebuffer_unreference(fb);
1051                 kfree(work);
1052                 return ret;
1053         }
1054
1055         /*
1056          * Don't take a reference on the new framebuffer;
1057          * drm_mode_page_flip_ioctl() has already grabbed a reference and
1058          * will _not_ drop that reference on successful return from this
1059          * function.  Simply mark this new framebuffer as the current one.
1060          */
1061         dcrtc->crtc.primary->fb = fb;
1062
1063         /*
1064          * Finally, if the display is blanked, we won't receive an
1065          * interrupt, so complete it now.
1066          */
1067         if (dpms_blanked(dcrtc->dpms))
1068                 armada_drm_plane_work_run(dcrtc, drm_to_armada_plane(dcrtc->crtc.primary));
1069
1070         return 0;
1071 }
1072
1073 static int
1074 armada_drm_crtc_set_property(struct drm_crtc *crtc,
1075         struct drm_property *property, uint64_t val)
1076 {
1077         struct armada_private *priv = crtc->dev->dev_private;
1078         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1079         bool update_csc = false;
1080
1081         if (property == priv->csc_yuv_prop) {
1082                 dcrtc->csc_yuv_mode = val;
1083                 update_csc = true;
1084         } else if (property == priv->csc_rgb_prop) {
1085                 dcrtc->csc_rgb_mode = val;
1086                 update_csc = true;
1087         }
1088
1089         if (update_csc) {
1090                 uint32_t val;
1091
1092                 val = dcrtc->spu_iopad_ctrl |
1093                       armada_drm_crtc_calculate_csc(dcrtc);
1094                 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1095         }
1096
1097         return 0;
1098 }
1099
1100 static struct drm_crtc_funcs armada_crtc_funcs = {
1101         .cursor_set     = armada_drm_crtc_cursor_set,
1102         .cursor_move    = armada_drm_crtc_cursor_move,
1103         .destroy        = armada_drm_crtc_destroy,
1104         .set_config     = drm_crtc_helper_set_config,
1105         .page_flip      = armada_drm_crtc_page_flip,
1106         .set_property   = armada_drm_crtc_set_property,
1107 };
1108
1109 static const struct drm_plane_funcs armada_primary_plane_funcs = {
1110         .update_plane   = drm_primary_helper_update,
1111         .disable_plane  = drm_primary_helper_disable,
1112         .destroy        = drm_primary_helper_destroy,
1113 };
1114
1115 int armada_drm_plane_init(struct armada_plane *plane)
1116 {
1117         init_waitqueue_head(&plane->frame_wait);
1118
1119         return 0;
1120 }
1121
1122 static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
1123         { CSC_AUTO,        "Auto" },
1124         { CSC_YUV_CCIR601, "CCIR601" },
1125         { CSC_YUV_CCIR709, "CCIR709" },
1126 };
1127
1128 static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
1129         { CSC_AUTO,         "Auto" },
1130         { CSC_RGB_COMPUTER, "Computer system" },
1131         { CSC_RGB_STUDIO,   "Studio" },
1132 };
1133
1134 static int armada_drm_crtc_create_properties(struct drm_device *dev)
1135 {
1136         struct armada_private *priv = dev->dev_private;
1137
1138         if (priv->csc_yuv_prop)
1139                 return 0;
1140
1141         priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1142                                 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1143                                 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1144         priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1145                                 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1146                                 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1147
1148         if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1149                 return -ENOMEM;
1150
1151         return 0;
1152 }
1153
1154 static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
1155         struct resource *res, int irq, const struct armada_variant *variant,
1156         struct device_node *port)
1157 {
1158         struct armada_private *priv = drm->dev_private;
1159         struct armada_crtc *dcrtc;
1160         struct armada_plane *primary;
1161         void __iomem *base;
1162         int ret;
1163
1164         ret = armada_drm_crtc_create_properties(drm);
1165         if (ret)
1166                 return ret;
1167
1168         base = devm_ioremap_resource(dev, res);
1169         if (IS_ERR(base))
1170                 return PTR_ERR(base);
1171
1172         dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1173         if (!dcrtc) {
1174                 DRM_ERROR("failed to allocate Armada crtc\n");
1175                 return -ENOMEM;
1176         }
1177
1178         if (dev != drm->dev)
1179                 dev_set_drvdata(dev, dcrtc);
1180
1181         dcrtc->variant = variant;
1182         dcrtc->base = base;
1183         dcrtc->num = drm->mode_config.num_crtc;
1184         dcrtc->clk = ERR_PTR(-EINVAL);
1185         dcrtc->csc_yuv_mode = CSC_AUTO;
1186         dcrtc->csc_rgb_mode = CSC_AUTO;
1187         dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1188         dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1189         spin_lock_init(&dcrtc->irq_lock);
1190         dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1191         INIT_LIST_HEAD(&dcrtc->vbl_list);
1192
1193         /* Initialize some registers which we don't otherwise set */
1194         writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1195         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1196         writel_relaxed(dcrtc->spu_iopad_ctrl,
1197                        dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1198         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1199         writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1200                        CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1201                        CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1202         writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
1203         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN);
1204         writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
1205         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
1206
1207         ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1208                                dcrtc);
1209         if (ret < 0) {
1210                 kfree(dcrtc);
1211                 return ret;
1212         }
1213
1214         if (dcrtc->variant->init) {
1215                 ret = dcrtc->variant->init(dcrtc, dev);
1216                 if (ret) {
1217                         kfree(dcrtc);
1218                         return ret;
1219                 }
1220         }
1221
1222         /* Ensure AXI pipeline is enabled */
1223         armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1224
1225         priv->dcrtc[dcrtc->num] = dcrtc;
1226
1227         dcrtc->crtc.port = port;
1228
1229         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
1230         if (!primary)
1231                 return -ENOMEM;
1232
1233         ret = armada_drm_plane_init(primary);
1234         if (ret) {
1235                 kfree(primary);
1236                 return ret;
1237         }
1238
1239         ret = drm_universal_plane_init(drm, &primary->base, 0,
1240                                        &armada_primary_plane_funcs,
1241                                        armada_primary_formats,
1242                                        ARRAY_SIZE(armada_primary_formats),
1243                                        DRM_PLANE_TYPE_PRIMARY);
1244         if (ret) {
1245                 kfree(primary);
1246                 return ret;
1247         }
1248
1249         ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL,
1250                                         &armada_crtc_funcs);
1251         if (ret)
1252                 goto err_crtc_init;
1253
1254         drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1255
1256         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1257                                    dcrtc->csc_yuv_mode);
1258         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1259                                    dcrtc->csc_rgb_mode);
1260
1261         return armada_overlay_plane_create(drm, 1 << dcrtc->num);
1262
1263 err_crtc_init:
1264         primary->base.funcs->destroy(&primary->base);
1265         return ret;
1266 }
1267
1268 static int
1269 armada_lcd_bind(struct device *dev, struct device *master, void *data)
1270 {
1271         struct platform_device *pdev = to_platform_device(dev);
1272         struct drm_device *drm = data;
1273         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1274         int irq = platform_get_irq(pdev, 0);
1275         const struct armada_variant *variant;
1276         struct device_node *port = NULL;
1277
1278         if (irq < 0)
1279                 return irq;
1280
1281         if (!dev->of_node) {
1282                 const struct platform_device_id *id;
1283
1284                 id = platform_get_device_id(pdev);
1285                 if (!id)
1286                         return -ENXIO;
1287
1288                 variant = (const struct armada_variant *)id->driver_data;
1289         } else {
1290                 const struct of_device_id *match;
1291                 struct device_node *np, *parent = dev->of_node;
1292
1293                 match = of_match_device(dev->driver->of_match_table, dev);
1294                 if (!match)
1295                         return -ENXIO;
1296
1297                 np = of_get_child_by_name(parent, "ports");
1298                 if (np)
1299                         parent = np;
1300                 port = of_get_child_by_name(parent, "port");
1301                 of_node_put(np);
1302                 if (!port) {
1303                         dev_err(dev, "no port node found in %s\n",
1304                                 parent->full_name);
1305                         return -ENXIO;
1306                 }
1307
1308                 variant = match->data;
1309         }
1310
1311         return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
1312 }
1313
1314 static void
1315 armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1316 {
1317         struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1318
1319         armada_drm_crtc_destroy(&dcrtc->crtc);
1320 }
1321
1322 static const struct component_ops armada_lcd_ops = {
1323         .bind = armada_lcd_bind,
1324         .unbind = armada_lcd_unbind,
1325 };
1326
1327 static int armada_lcd_probe(struct platform_device *pdev)
1328 {
1329         return component_add(&pdev->dev, &armada_lcd_ops);
1330 }
1331
1332 static int armada_lcd_remove(struct platform_device *pdev)
1333 {
1334         component_del(&pdev->dev, &armada_lcd_ops);
1335         return 0;
1336 }
1337
1338 static struct of_device_id armada_lcd_of_match[] = {
1339         {
1340                 .compatible     = "marvell,dove-lcd",
1341                 .data           = &armada510_ops,
1342         },
1343         {}
1344 };
1345 MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1346
1347 static const struct platform_device_id armada_lcd_platform_ids[] = {
1348         {
1349                 .name           = "armada-lcd",
1350                 .driver_data    = (unsigned long)&armada510_ops,
1351         }, {
1352                 .name           = "armada-510-lcd",
1353                 .driver_data    = (unsigned long)&armada510_ops,
1354         },
1355         { },
1356 };
1357 MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1358
1359 struct platform_driver armada_lcd_platform_driver = {
1360         .probe  = armada_lcd_probe,
1361         .remove = armada_lcd_remove,
1362         .driver = {
1363                 .name   = "armada-lcd",
1364                 .owner  =  THIS_MODULE,
1365                 .of_match_table = armada_lcd_of_match,
1366         },
1367         .id_table = armada_lcd_platform_ids,
1368 };