2 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * Designware High-Definition Multimedia Interface (HDMI) driver
11 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
13 #include <linux/module.h>
14 #include <linux/irq.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/hdmi.h>
19 #include <linux/mutex.h>
20 #include <linux/of_device.h>
21 #include <linux/spinlock.h>
23 #include <drm/drm_of.h>
25 #include <drm/drm_atomic_helper.h>
26 #include <drm/drm_crtc_helper.h>
27 #include <drm/drm_edid.h>
28 #include <drm/drm_encoder_slave.h>
29 #include <drm/bridge/dw_hdmi.h>
32 #include "dw-hdmi-audio.h"
34 #define HDMI_EDID_LEN 512
38 #define YCBCR422_16BITS 2
39 #define YCBCR422_8BITS 3
56 static const u16 csc_coeff_default[3][4] = {
57 { 0x2000, 0x0000, 0x0000, 0x0000 },
58 { 0x0000, 0x2000, 0x0000, 0x0000 },
59 { 0x0000, 0x0000, 0x2000, 0x0000 }
62 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
63 { 0x2000, 0x6926, 0x74fd, 0x010e },
64 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
65 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
68 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
69 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
70 { 0x2000, 0x3264, 0x0000, 0x7e6d },
71 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
74 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
75 { 0x2591, 0x1322, 0x074b, 0x0000 },
76 { 0x6535, 0x2000, 0x7acc, 0x0200 },
77 { 0x6acd, 0x7534, 0x2000, 0x0200 }
80 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
81 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
82 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
83 { 0x6756, 0x78ab, 0x2000, 0x0200 }
87 bool mdataenablepolarity;
89 unsigned int mpixelclock;
90 unsigned int mpixelrepetitioninput;
91 unsigned int mpixelrepetitionoutput;
94 struct hdmi_data_info {
95 unsigned int enc_in_format;
96 unsigned int enc_out_format;
97 unsigned int enc_color_depth;
98 unsigned int colorimetry;
99 unsigned int pix_repet_factor;
100 unsigned int hdcp_enable;
101 struct hdmi_vmode video_mode;
105 struct drm_connector connector;
106 struct drm_encoder *encoder;
107 struct drm_bridge *bridge;
109 struct platform_device *audio;
110 enum dw_hdmi_devtype dev_type;
112 struct clk *isfr_clk;
113 struct clk *iahb_clk;
115 struct hdmi_data_info hdmi_data;
116 const struct dw_hdmi_plat_data *plat_data;
120 u8 edid[HDMI_EDID_LEN];
124 struct drm_display_mode previous_mode;
126 struct i2c_adapter *ddc;
131 struct mutex mutex; /* for state below and previous_mode */
132 enum drm_connector_force force; /* mutex-protected force state */
133 bool disabled; /* DRM has disabled our bridge */
134 bool bridge_is_on; /* indicates the bridge is on */
135 bool rxsense; /* rxsense state */
136 u8 phy_mask; /* desired phy int mask settings */
138 spinlock_t audio_lock;
139 struct mutex audio_mutex;
140 unsigned int sample_rate;
141 unsigned int audio_cts;
142 unsigned int audio_n;
145 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
146 u8 (*read)(struct dw_hdmi *hdmi, int offset);
149 #define HDMI_IH_PHY_STAT0_RX_SENSE \
150 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
151 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
153 #define HDMI_PHY_RX_SENSE \
154 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
155 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
157 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
159 writel(val, hdmi->regs + (offset << 2));
162 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
164 return readl(hdmi->regs + (offset << 2));
167 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
169 writeb(val, hdmi->regs + offset);
172 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
174 return readb(hdmi->regs + offset);
177 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
179 hdmi->write(hdmi, val, offset);
182 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
184 return hdmi->read(hdmi, offset);
187 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
189 u8 val = hdmi_readb(hdmi, reg) & ~mask;
192 hdmi_writeb(hdmi, val, reg);
195 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
198 hdmi_modb(hdmi, data << shift, mask, reg);
201 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
204 /* Must be set/cleared first */
205 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
207 /* nshift factor = 0 */
208 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
210 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
211 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
212 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
213 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
215 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
216 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
217 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
220 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
222 unsigned int n = (128 * freq) / 1000;
223 unsigned int mult = 1;
225 while (freq > 48000) {
232 if (pixel_clk == 25175000)
234 else if (pixel_clk == 27027000)
236 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
244 if (pixel_clk == 25175000)
246 else if (pixel_clk == 74176000)
248 else if (pixel_clk == 148352000)
256 if (pixel_clk == 25175000)
258 else if (pixel_clk == 27027000)
260 else if (pixel_clk == 74176000)
262 else if (pixel_clk == 148352000)
276 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
277 unsigned long pixel_clk, unsigned int sample_rate)
279 unsigned long ftdms = pixel_clk;
283 n = hdmi_compute_n(sample_rate, pixel_clk);
286 * Compute the CTS value from the N value. Note that CTS and N
287 * can be up to 20 bits in total, so we need 64-bit math. Also
288 * note that our TDMS clock is not fully accurate; it is accurate
289 * to kHz. This can introduce an unnecessary remainder in the
290 * calculation below, so we don't try to warn about that.
292 tmp = (u64)ftdms * n;
293 do_div(tmp, 128 * sample_rate);
296 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
297 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
300 spin_lock_irq(&hdmi->audio_lock);
302 hdmi->audio_cts = cts;
303 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
304 spin_unlock_irq(&hdmi->audio_lock);
307 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
309 mutex_lock(&hdmi->audio_mutex);
310 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
311 mutex_unlock(&hdmi->audio_mutex);
314 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
316 mutex_lock(&hdmi->audio_mutex);
317 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
319 mutex_unlock(&hdmi->audio_mutex);
322 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
324 mutex_lock(&hdmi->audio_mutex);
325 hdmi->sample_rate = rate;
326 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
328 mutex_unlock(&hdmi->audio_mutex);
330 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
332 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
336 spin_lock_irqsave(&hdmi->audio_lock, flags);
337 hdmi->audio_enable = true;
338 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
339 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
341 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
343 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
347 spin_lock_irqsave(&hdmi->audio_lock, flags);
348 hdmi->audio_enable = false;
349 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
350 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
352 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
355 * this submodule is responsible for the video data synchronization.
356 * for example, for RGB 4:4:4 input, the data map is defined as
357 * pin{47~40} <==> R[7:0]
358 * pin{31~24} <==> G[7:0]
359 * pin{15~8} <==> B[7:0]
361 static void hdmi_video_sample(struct dw_hdmi *hdmi)
363 int color_format = 0;
366 if (hdmi->hdmi_data.enc_in_format == RGB) {
367 if (hdmi->hdmi_data.enc_color_depth == 8)
369 else if (hdmi->hdmi_data.enc_color_depth == 10)
371 else if (hdmi->hdmi_data.enc_color_depth == 12)
373 else if (hdmi->hdmi_data.enc_color_depth == 16)
377 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
378 if (hdmi->hdmi_data.enc_color_depth == 8)
380 else if (hdmi->hdmi_data.enc_color_depth == 10)
382 else if (hdmi->hdmi_data.enc_color_depth == 12)
384 else if (hdmi->hdmi_data.enc_color_depth == 16)
388 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
389 if (hdmi->hdmi_data.enc_color_depth == 8)
391 else if (hdmi->hdmi_data.enc_color_depth == 10)
393 else if (hdmi->hdmi_data.enc_color_depth == 12)
399 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
400 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
401 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
402 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
404 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
405 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
406 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
407 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
408 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
409 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
410 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
411 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
412 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
413 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
414 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
417 static int is_color_space_conversion(struct dw_hdmi *hdmi)
419 return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
422 static int is_color_space_decimation(struct dw_hdmi *hdmi)
424 if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
426 if (hdmi->hdmi_data.enc_in_format == RGB ||
427 hdmi->hdmi_data.enc_in_format == YCBCR444)
432 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
434 if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
436 if (hdmi->hdmi_data.enc_out_format == RGB ||
437 hdmi->hdmi_data.enc_out_format == YCBCR444)
442 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
444 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
448 if (is_color_space_conversion(hdmi)) {
449 if (hdmi->hdmi_data.enc_out_format == RGB) {
450 if (hdmi->hdmi_data.colorimetry ==
451 HDMI_COLORIMETRY_ITU_601)
452 csc_coeff = &csc_coeff_rgb_out_eitu601;
454 csc_coeff = &csc_coeff_rgb_out_eitu709;
455 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
456 if (hdmi->hdmi_data.colorimetry ==
457 HDMI_COLORIMETRY_ITU_601)
458 csc_coeff = &csc_coeff_rgb_in_eitu601;
460 csc_coeff = &csc_coeff_rgb_in_eitu709;
465 /* The CSC registers are sequential, alternating MSB then LSB */
466 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
467 u16 coeff_a = (*csc_coeff)[0][i];
468 u16 coeff_b = (*csc_coeff)[1][i];
469 u16 coeff_c = (*csc_coeff)[2][i];
471 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
472 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
473 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
474 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
475 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
476 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
479 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
483 static void hdmi_video_csc(struct dw_hdmi *hdmi)
486 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
489 /* YCC422 interpolation to 444 mode */
490 if (is_color_space_interpolation(hdmi))
491 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
492 else if (is_color_space_decimation(hdmi))
493 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
495 if (hdmi->hdmi_data.enc_color_depth == 8)
496 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
497 else if (hdmi->hdmi_data.enc_color_depth == 10)
498 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
499 else if (hdmi->hdmi_data.enc_color_depth == 12)
500 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
501 else if (hdmi->hdmi_data.enc_color_depth == 16)
502 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
506 /* Configure the CSC registers */
507 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
508 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
511 dw_hdmi_update_csc_coeffs(hdmi);
515 * HDMI video packetizer is used to packetize the data.
516 * for example, if input is YCC422 mode or repeater is used,
517 * data should be repacked this module can be bypassed.
519 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
521 unsigned int color_depth = 0;
522 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
523 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
524 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
527 if (hdmi_data->enc_out_format == RGB ||
528 hdmi_data->enc_out_format == YCBCR444) {
529 if (!hdmi_data->enc_color_depth) {
530 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
531 } else if (hdmi_data->enc_color_depth == 8) {
533 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
534 } else if (hdmi_data->enc_color_depth == 10) {
536 } else if (hdmi_data->enc_color_depth == 12) {
538 } else if (hdmi_data->enc_color_depth == 16) {
543 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
544 if (!hdmi_data->enc_color_depth ||
545 hdmi_data->enc_color_depth == 8)
546 remap_size = HDMI_VP_REMAP_YCC422_16bit;
547 else if (hdmi_data->enc_color_depth == 10)
548 remap_size = HDMI_VP_REMAP_YCC422_20bit;
549 else if (hdmi_data->enc_color_depth == 12)
550 remap_size = HDMI_VP_REMAP_YCC422_24bit;
553 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
558 /* set the packetizer registers */
559 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
560 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
561 ((hdmi_data->pix_repet_factor <<
562 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
563 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
564 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
566 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
567 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
569 /* Data from pixel repeater block */
570 if (hdmi_data->pix_repet_factor > 1) {
571 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
572 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
573 } else { /* data from packetizer block */
574 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
575 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
578 hdmi_modb(hdmi, vp_conf,
579 HDMI_VP_CONF_PR_EN_MASK |
580 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
582 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
583 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
585 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
587 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
588 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
589 HDMI_VP_CONF_PP_EN_ENABLE |
590 HDMI_VP_CONF_YCC422_EN_DISABLE;
591 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
592 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
593 HDMI_VP_CONF_PP_EN_DISABLE |
594 HDMI_VP_CONF_YCC422_EN_ENABLE;
595 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
596 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
597 HDMI_VP_CONF_PP_EN_DISABLE |
598 HDMI_VP_CONF_YCC422_EN_DISABLE;
603 hdmi_modb(hdmi, vp_conf,
604 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
605 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
607 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
608 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
609 HDMI_VP_STUFF_PP_STUFFING_MASK |
610 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
612 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
616 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
619 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
620 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
623 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
626 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
627 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
630 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
633 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
634 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
637 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
640 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
643 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
646 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
649 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
653 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
658 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
663 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
666 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
667 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
668 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
669 HDMI_PHY_I2CM_DATAO_1_ADDR);
670 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
671 HDMI_PHY_I2CM_DATAO_0_ADDR);
672 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
673 HDMI_PHY_I2CM_OPERATION_ADDR);
674 hdmi_phy_wait_i2c_done(hdmi, 1000);
677 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
680 __hdmi_phy_i2c_write(hdmi, data, addr);
684 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
686 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
687 HDMI_PHY_CONF0_PDZ_OFFSET,
688 HDMI_PHY_CONF0_PDZ_MASK);
691 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
693 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
694 HDMI_PHY_CONF0_ENTMDS_OFFSET,
695 HDMI_PHY_CONF0_ENTMDS_MASK);
698 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
700 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
701 HDMI_PHY_CONF0_SPARECTRL_OFFSET,
702 HDMI_PHY_CONF0_SPARECTRL_MASK);
705 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
707 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
708 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
709 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
712 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
714 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
715 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
716 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
719 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
721 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
722 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
723 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
726 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
728 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
729 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
730 HDMI_PHY_CONF0_SELDIPIF_MASK);
733 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
734 unsigned char res, int cscon)
738 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
739 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
740 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
741 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
747 case 0: /* color resolution 0 is 8 bit colour depth */
749 res_idx = DW_HDMI_RES_8;
752 res_idx = DW_HDMI_RES_10;
755 res_idx = DW_HDMI_RES_12;
761 /* PLL/MPLL Cfg - always match on final entry */
762 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
763 if (hdmi->hdmi_data.video_mode.mpixelclock <=
764 mpll_config->mpixelclock)
767 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
768 if (hdmi->hdmi_data.video_mode.mpixelclock <=
769 curr_ctrl->mpixelclock)
772 for (; phy_config->mpixelclock != ~0UL; phy_config++)
773 if (hdmi->hdmi_data.video_mode.mpixelclock <=
774 phy_config->mpixelclock)
777 if (mpll_config->mpixelclock == ~0UL ||
778 curr_ctrl->mpixelclock == ~0UL ||
779 phy_config->mpixelclock == ~0UL) {
780 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
781 hdmi->hdmi_data.video_mode.mpixelclock);
785 /* Enable csc path */
787 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
789 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
791 hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
793 /* gen2 tx power off */
794 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
797 dw_hdmi_phy_gen2_pddq(hdmi, 1);
800 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
801 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
803 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
805 hdmi_phy_test_clear(hdmi, 1);
806 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
807 HDMI_PHY_I2CM_SLAVE_ADDR);
808 hdmi_phy_test_clear(hdmi, 0);
810 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
811 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
814 hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
816 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
817 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
819 hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19); /* TXTERM */
820 hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
821 hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
823 /* REMOVE CLK TERM */
824 hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
826 dw_hdmi_phy_enable_powerdown(hdmi, false);
828 /* toggle TMDS enable */
829 dw_hdmi_phy_enable_tmds(hdmi, 0);
830 dw_hdmi_phy_enable_tmds(hdmi, 1);
832 /* gen2 tx power on */
833 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
834 dw_hdmi_phy_gen2_pddq(hdmi, 0);
836 if (hdmi->dev_type == RK3288_HDMI)
837 dw_hdmi_phy_enable_spare(hdmi, 1);
839 /*Wait for PHY PLL lock */
842 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
847 dev_err(hdmi->dev, "PHY PLL not locked\n");
858 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
863 /*check csc whether needed activated in HDMI mode */
864 cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
866 /* HDMI Phy spec says to do the phy initialization sequence twice */
867 for (i = 0; i < 2; i++) {
868 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
869 dw_hdmi_phy_sel_interface_control(hdmi, 0);
870 dw_hdmi_phy_enable_tmds(hdmi, 0);
871 dw_hdmi_phy_enable_powerdown(hdmi, true);
874 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
879 hdmi->phy_enabled = true;
883 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
887 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
888 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
890 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
892 /* disable rx detect */
893 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
894 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
896 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
898 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
899 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
902 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
904 struct hdmi_avi_infoframe frame;
907 /* Initialise info frame from DRM mode */
908 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
910 if (hdmi->hdmi_data.enc_out_format == YCBCR444)
911 frame.colorspace = HDMI_COLORSPACE_YUV444;
912 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
913 frame.colorspace = HDMI_COLORSPACE_YUV422;
915 frame.colorspace = HDMI_COLORSPACE_RGB;
917 /* Set up colorimetry */
918 if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
919 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
920 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
921 frame.extended_colorimetry =
922 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
923 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
924 frame.extended_colorimetry =
925 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
926 } else if (hdmi->hdmi_data.enc_out_format != RGB) {
927 frame.colorimetry = hdmi->hdmi_data.colorimetry;
928 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
929 } else { /* Carries no data */
930 frame.colorimetry = HDMI_COLORIMETRY_NONE;
931 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
934 frame.scan_mode = HDMI_SCAN_MODE_NONE;
937 * The Designware IP uses a different byte format from standard
938 * AVI info frames, though generally the bits are in the correct
943 * AVI data byte 1 differences: Colorspace in bits 4,5 rather than 5,6,
944 * active aspect present in bit 6 rather than 4.
946 val = (frame.colorspace & 3) << 4 | (frame.scan_mode & 0x3);
947 if (frame.active_aspect & 15)
948 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
949 if (frame.top_bar || frame.bottom_bar)
950 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
951 if (frame.left_bar || frame.right_bar)
952 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
953 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
955 /* AVI data byte 2 differences: none */
956 val = ((frame.colorimetry & 0x3) << 6) |
957 ((frame.picture_aspect & 0x3) << 4) |
958 (frame.active_aspect & 0xf);
959 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
961 /* AVI data byte 3 differences: none */
962 val = ((frame.extended_colorimetry & 0x7) << 4) |
963 ((frame.quantization_range & 0x3) << 2) |
966 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
967 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
969 /* AVI data byte 4 differences: none */
970 val = frame.video_code & 0x7f;
971 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
973 /* AVI Data Byte 5- set up input and output pixel repetition */
974 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
975 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
976 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
977 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
978 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
979 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
980 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
983 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
984 * ycc range in bits 2,3 rather than 6,7
986 val = ((frame.ycc_quantization_range & 0x3) << 2) |
987 (frame.content_type & 0x3);
988 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
990 /* AVI Data Bytes 6-13 */
991 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
992 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
993 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
994 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
995 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
996 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
997 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
998 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1001 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1002 const struct drm_display_mode *mode)
1005 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1006 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1007 unsigned int vdisplay;
1009 vmode->mpixelclock = mode->clock * 1000;
1011 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1013 /* Set up HDMI_FC_INVIDCONF */
1014 inv_val = (hdmi->hdmi_data.hdcp_enable ?
1015 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1016 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1018 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1019 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1020 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1022 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1023 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1024 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1026 inv_val |= (vmode->mdataenablepolarity ?
1027 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1028 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1030 if (hdmi->vic == 39)
1031 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1033 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1034 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1035 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1037 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1038 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1039 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1041 inv_val |= hdmi->sink_is_hdmi ?
1042 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1043 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1045 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1047 vdisplay = mode->vdisplay;
1048 vblank = mode->vtotal - mode->vdisplay;
1049 v_de_vs = mode->vsync_start - mode->vdisplay;
1050 vsync_len = mode->vsync_end - mode->vsync_start;
1053 * When we're setting an interlaced mode, we need
1054 * to adjust the vertical timing to suit.
1056 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1063 /* Set up horizontal active pixel width */
1064 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1065 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1067 /* Set up vertical active lines */
1068 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1069 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1071 /* Set up horizontal blanking pixel region width */
1072 hblank = mode->htotal - mode->hdisplay;
1073 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1074 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1076 /* Set up vertical blanking pixel region width */
1077 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1079 /* Set up HSYNC active edge delay width (in pixel clks) */
1080 h_de_hs = mode->hsync_start - mode->hdisplay;
1081 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1082 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1084 /* Set up VSYNC active edge delay (in lines) */
1085 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1087 /* Set up HSYNC active pulse width (in pixel clks) */
1088 hsync_len = mode->hsync_end - mode->hsync_start;
1089 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1090 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1092 /* Set up VSYNC active edge delay (in lines) */
1093 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1096 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1098 if (!hdmi->phy_enabled)
1101 dw_hdmi_phy_enable_tmds(hdmi, 0);
1102 dw_hdmi_phy_enable_powerdown(hdmi, true);
1104 hdmi->phy_enabled = false;
1107 /* HDMI Initialization Step B.4 */
1108 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1112 /* control period minimum duration */
1113 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1114 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1115 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1117 /* Set to fill TMDS data channels */
1118 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1119 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1120 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1122 /* Enable pixel clock and tmds data path */
1124 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1125 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1127 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1128 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1130 /* Enable csc path */
1131 if (is_color_space_conversion(hdmi)) {
1132 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1133 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1137 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1139 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1142 /* Workaround to clear the overflow condition */
1143 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1148 /* TMDS software reset */
1149 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1151 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1152 if (hdmi->dev_type == IMX6DL_HDMI) {
1153 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1157 for (count = 0; count < 4; count++)
1158 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1161 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1163 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1164 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1167 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1169 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1170 HDMI_IH_MUTE_FC_STAT2);
1173 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1177 hdmi_disable_overflow_interrupts(hdmi);
1179 hdmi->vic = drm_match_cea_mode(mode);
1182 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1184 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1187 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1188 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1189 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1190 (hdmi->vic == 17) || (hdmi->vic == 18))
1191 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1193 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1195 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1196 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1198 /* TODO: Get input format from IPU (via FB driver interface) */
1199 hdmi->hdmi_data.enc_in_format = RGB;
1201 hdmi->hdmi_data.enc_out_format = RGB;
1203 hdmi->hdmi_data.enc_color_depth = 8;
1204 hdmi->hdmi_data.pix_repet_factor = 0;
1205 hdmi->hdmi_data.hdcp_enable = 0;
1206 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1208 /* HDMI Initialization Step B.1 */
1209 hdmi_av_composer(hdmi, mode);
1211 /* HDMI Initializateion Step B.2 */
1212 ret = dw_hdmi_phy_init(hdmi);
1216 /* HDMI Initialization Step B.3 */
1217 dw_hdmi_enable_video_path(hdmi);
1219 if (hdmi->sink_has_audio) {
1220 dev_dbg(hdmi->dev, "sink has audio support\n");
1222 /* HDMI Initialization Step E - Configure audio */
1223 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1224 hdmi_enable_audio_clk(hdmi);
1227 /* not for DVI mode */
1228 if (hdmi->sink_is_hdmi) {
1229 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1231 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1232 hdmi_config_AVI(hdmi, mode);
1234 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1237 hdmi_video_packetize(hdmi);
1238 hdmi_video_csc(hdmi);
1239 hdmi_video_sample(hdmi);
1240 hdmi_tx_hdcp_config(hdmi);
1242 dw_hdmi_clear_overflow(hdmi);
1243 if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1244 hdmi_enable_overflow_interrupts(hdmi);
1249 /* Wait until we are registered to enable interrupts */
1250 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1252 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1253 HDMI_PHY_I2CM_INT_ADDR);
1255 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1256 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1257 HDMI_PHY_I2CM_CTLINT_ADDR);
1259 /* enable cable hot plug irq */
1260 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1262 /* Clear Hotplug interrupts */
1263 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1269 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1274 * Boot up defaults are:
1275 * HDMI_IH_MUTE = 0x03 (disabled)
1276 * HDMI_IH_MUTE_* = 0x00 (enabled)
1278 * Disable top level interrupt bits in HDMI block
1280 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1281 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1282 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1284 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1286 /* by default mask all interrupts */
1287 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1288 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1289 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1290 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1291 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1292 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1293 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1294 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1295 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1296 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1297 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1298 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1299 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1300 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1301 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1303 /* Disable interrupts in the IH_MUTE_* registers */
1304 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1305 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1306 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1307 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1308 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1309 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1310 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1311 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1312 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1313 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1315 /* Enable top level interrupt bits in HDMI block */
1316 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1317 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1318 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1321 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1323 hdmi->bridge_is_on = true;
1324 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1327 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1329 dw_hdmi_phy_disable(hdmi);
1330 hdmi->bridge_is_on = false;
1333 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1335 int force = hdmi->force;
1337 if (hdmi->disabled) {
1338 force = DRM_FORCE_OFF;
1339 } else if (force == DRM_FORCE_UNSPECIFIED) {
1341 force = DRM_FORCE_ON;
1343 force = DRM_FORCE_OFF;
1346 if (force == DRM_FORCE_OFF) {
1347 if (hdmi->bridge_is_on)
1348 dw_hdmi_poweroff(hdmi);
1350 if (!hdmi->bridge_is_on)
1351 dw_hdmi_poweron(hdmi);
1356 * Adjust the detection of RXSENSE according to whether we have a forced
1357 * connection mode enabled, or whether we have been disabled. There is
1358 * no point processing RXSENSE interrupts if we have a forced connection
1359 * state, or DRM has us disabled.
1361 * We also disable rxsense interrupts when we think we're disconnected
1362 * to avoid floating TDMS signals giving false rxsense interrupts.
1364 * Note: we still need to listen for HPD interrupts even when DRM has us
1365 * disabled so that we can detect a connect event.
1367 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1369 u8 old_mask = hdmi->phy_mask;
1371 if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1372 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1374 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1376 if (old_mask != hdmi->phy_mask)
1377 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1380 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1381 struct drm_display_mode *orig_mode,
1382 struct drm_display_mode *mode)
1384 struct dw_hdmi *hdmi = bridge->driver_private;
1386 mutex_lock(&hdmi->mutex);
1388 /* Store the display mode for plugin/DKMS poweron events */
1389 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1391 mutex_unlock(&hdmi->mutex);
1394 static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1395 const struct drm_display_mode *mode,
1396 struct drm_display_mode *adjusted_mode)
1401 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1403 struct dw_hdmi *hdmi = bridge->driver_private;
1405 mutex_lock(&hdmi->mutex);
1406 hdmi->disabled = true;
1407 dw_hdmi_update_power(hdmi);
1408 dw_hdmi_update_phy_mask(hdmi);
1409 mutex_unlock(&hdmi->mutex);
1412 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1414 struct dw_hdmi *hdmi = bridge->driver_private;
1416 mutex_lock(&hdmi->mutex);
1417 hdmi->disabled = false;
1418 dw_hdmi_update_power(hdmi);
1419 dw_hdmi_update_phy_mask(hdmi);
1420 mutex_unlock(&hdmi->mutex);
1423 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1428 static enum drm_connector_status
1429 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1431 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1434 mutex_lock(&hdmi->mutex);
1435 hdmi->force = DRM_FORCE_UNSPECIFIED;
1436 dw_hdmi_update_power(hdmi);
1437 dw_hdmi_update_phy_mask(hdmi);
1438 mutex_unlock(&hdmi->mutex);
1440 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1441 connector_status_connected : connector_status_disconnected;
1444 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1446 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1454 edid = drm_get_edid(connector, hdmi->ddc);
1456 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1457 edid->width_cm, edid->height_cm);
1459 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1460 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1461 drm_mode_connector_update_edid_property(connector, edid);
1462 ret = drm_add_edid_modes(connector, edid);
1464 drm_edid_to_eld(connector, edid);
1467 dev_dbg(hdmi->dev, "failed to get edid\n");
1473 static enum drm_mode_status
1474 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1475 struct drm_display_mode *mode)
1477 struct dw_hdmi *hdmi = container_of(connector,
1478 struct dw_hdmi, connector);
1479 enum drm_mode_status mode_status = MODE_OK;
1481 /* We don't support double-clocked modes */
1482 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1485 if (hdmi->plat_data->mode_valid)
1486 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1491 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1494 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1497 return hdmi->encoder;
1500 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1502 drm_connector_unregister(connector);
1503 drm_connector_cleanup(connector);
1506 static void dw_hdmi_connector_force(struct drm_connector *connector)
1508 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1511 mutex_lock(&hdmi->mutex);
1512 hdmi->force = connector->force;
1513 dw_hdmi_update_power(hdmi);
1514 dw_hdmi_update_phy_mask(hdmi);
1515 mutex_unlock(&hdmi->mutex);
1518 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1519 .dpms = drm_helper_connector_dpms,
1520 .fill_modes = drm_helper_probe_single_connector_modes,
1521 .detect = dw_hdmi_connector_detect,
1522 .destroy = dw_hdmi_connector_destroy,
1523 .force = dw_hdmi_connector_force,
1526 static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
1527 .dpms = drm_atomic_helper_connector_dpms,
1528 .fill_modes = drm_helper_probe_single_connector_modes,
1529 .detect = dw_hdmi_connector_detect,
1530 .destroy = dw_hdmi_connector_destroy,
1531 .force = dw_hdmi_connector_force,
1532 .reset = drm_atomic_helper_connector_reset,
1533 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1534 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1537 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1538 .get_modes = dw_hdmi_connector_get_modes,
1539 .mode_valid = dw_hdmi_connector_mode_valid,
1540 .best_encoder = dw_hdmi_connector_best_encoder,
1543 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1544 .enable = dw_hdmi_bridge_enable,
1545 .disable = dw_hdmi_bridge_disable,
1546 .pre_enable = dw_hdmi_bridge_nop,
1547 .post_disable = dw_hdmi_bridge_nop,
1548 .mode_set = dw_hdmi_bridge_mode_set,
1549 .mode_fixup = dw_hdmi_bridge_mode_fixup,
1552 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1554 struct dw_hdmi *hdmi = dev_id;
1557 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1559 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1561 return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1564 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1566 struct dw_hdmi *hdmi = dev_id;
1567 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
1569 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1570 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1571 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1574 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1575 phy_pol_mask |= HDMI_PHY_HPD;
1576 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
1577 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
1578 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
1579 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
1580 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
1581 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
1582 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
1583 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
1586 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
1589 * RX sense tells us whether the TDMS transmitters are detecting
1590 * load - in other words, there's something listening on the
1591 * other end of the link. Use this to decide whether we should
1592 * power on the phy as HPD may be toggled by the sink to merely
1593 * ask the source to re-read the EDID.
1596 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
1597 mutex_lock(&hdmi->mutex);
1598 if (!hdmi->disabled && !hdmi->force) {
1600 * If the RX sense status indicates we're disconnected,
1601 * clear the software rxsense status.
1603 if (!(phy_stat & HDMI_PHY_RX_SENSE))
1604 hdmi->rxsense = false;
1607 * Only set the software rxsense status when both
1608 * rxsense and hpd indicates we're connected.
1609 * This avoids what seems to be bad behaviour in
1610 * at least iMX6S versions of the phy.
1612 if (phy_stat & HDMI_PHY_HPD)
1613 hdmi->rxsense = true;
1615 dw_hdmi_update_power(hdmi);
1616 dw_hdmi_update_phy_mask(hdmi);
1618 mutex_unlock(&hdmi->mutex);
1621 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1622 dev_dbg(hdmi->dev, "EVENT=%s\n",
1623 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
1624 drm_helper_hpd_irq_event(hdmi->bridge->dev);
1627 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1628 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1629 HDMI_IH_MUTE_PHY_STAT0);
1634 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1636 struct drm_encoder *encoder = hdmi->encoder;
1637 struct drm_bridge *bridge;
1640 bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1642 DRM_ERROR("Failed to allocate drm bridge\n");
1646 hdmi->bridge = bridge;
1647 bridge->driver_private = hdmi;
1648 bridge->funcs = &dw_hdmi_bridge_funcs;
1649 ret = drm_bridge_attach(drm, bridge);
1651 DRM_ERROR("Failed to initialize bridge with drm\n");
1655 encoder->bridge = bridge;
1656 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1658 drm_connector_helper_add(&hdmi->connector,
1659 &dw_hdmi_connector_helper_funcs);
1661 if (drm_core_check_feature(drm, DRIVER_ATOMIC))
1662 drm_connector_init(drm, &hdmi->connector,
1663 &dw_hdmi_atomic_connector_funcs,
1664 DRM_MODE_CONNECTOR_HDMIA);
1666 drm_connector_init(drm, &hdmi->connector,
1667 &dw_hdmi_connector_funcs,
1668 DRM_MODE_CONNECTOR_HDMIA);
1670 hdmi->connector.encoder = encoder;
1672 drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1677 int dw_hdmi_bind(struct device *dev, struct device *master,
1678 void *data, struct drm_encoder *encoder,
1679 struct resource *iores, int irq,
1680 const struct dw_hdmi_plat_data *plat_data)
1682 struct drm_device *drm = data;
1683 struct device_node *np = dev->of_node;
1684 struct platform_device_info pdevinfo;
1685 struct device_node *ddc_node;
1686 struct dw_hdmi_audio_data audio;
1687 struct dw_hdmi *hdmi;
1691 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1695 hdmi->connector.interlace_allowed = 1;
1697 hdmi->plat_data = plat_data;
1699 hdmi->dev_type = plat_data->dev_type;
1700 hdmi->sample_rate = 48000;
1701 hdmi->encoder = encoder;
1702 hdmi->disabled = true;
1703 hdmi->rxsense = true;
1704 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
1706 mutex_init(&hdmi->mutex);
1707 mutex_init(&hdmi->audio_mutex);
1708 spin_lock_init(&hdmi->audio_lock);
1710 of_property_read_u32(np, "reg-io-width", &val);
1714 hdmi->write = dw_hdmi_writel;
1715 hdmi->read = dw_hdmi_readl;
1718 hdmi->write = dw_hdmi_writeb;
1719 hdmi->read = dw_hdmi_readb;
1722 dev_err(dev, "reg-io-width must be 1 or 4\n");
1726 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1728 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1729 of_node_put(ddc_node);
1731 dev_dbg(hdmi->dev, "failed to read ddc node\n");
1732 return -EPROBE_DEFER;
1736 dev_dbg(hdmi->dev, "no ddc property found\n");
1739 hdmi->regs = devm_ioremap_resource(dev, iores);
1740 if (IS_ERR(hdmi->regs))
1741 return PTR_ERR(hdmi->regs);
1743 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1744 if (IS_ERR(hdmi->isfr_clk)) {
1745 ret = PTR_ERR(hdmi->isfr_clk);
1746 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1750 ret = clk_prepare_enable(hdmi->isfr_clk);
1752 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1756 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1757 if (IS_ERR(hdmi->iahb_clk)) {
1758 ret = PTR_ERR(hdmi->iahb_clk);
1759 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1763 ret = clk_prepare_enable(hdmi->iahb_clk);
1765 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1769 /* Product and revision IDs */
1771 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1772 hdmi_readb(hdmi, HDMI_DESIGN_ID),
1773 hdmi_readb(hdmi, HDMI_REVISION_ID),
1774 hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1775 hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1777 initialize_hdmi_ih_mutes(hdmi);
1779 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1780 dw_hdmi_irq, IRQF_SHARED,
1781 dev_name(dev), hdmi);
1786 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1787 * N and cts values before enabling phy
1789 hdmi_init_clk_regenerator(hdmi);
1792 * Configure registers related to HDMI interrupt
1793 * generation before registering IRQ.
1795 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1797 /* Clear Hotplug interrupts */
1798 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1801 ret = dw_hdmi_fb_registered(hdmi);
1805 ret = dw_hdmi_register(drm, hdmi);
1809 /* Unmute interrupts */
1810 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1811 HDMI_IH_MUTE_PHY_STAT0);
1813 memset(&pdevinfo, 0, sizeof(pdevinfo));
1814 pdevinfo.parent = dev;
1815 pdevinfo.id = PLATFORM_DEVID_AUTO;
1817 if (hdmi_readb(hdmi, HDMI_CONFIG1_ID) & HDMI_CONFIG1_AHB) {
1818 audio.phys = iores->start;
1819 audio.base = hdmi->regs;
1822 audio.eld = hdmi->connector.eld;
1824 pdevinfo.name = "dw-hdmi-ahb-audio";
1825 pdevinfo.data = &audio;
1826 pdevinfo.size_data = sizeof(audio);
1827 pdevinfo.dma_mask = DMA_BIT_MASK(32);
1828 hdmi->audio = platform_device_register_full(&pdevinfo);
1831 dev_set_drvdata(dev, hdmi);
1836 clk_disable_unprepare(hdmi->iahb_clk);
1838 clk_disable_unprepare(hdmi->isfr_clk);
1842 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
1844 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
1846 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
1848 if (hdmi->audio && !IS_ERR(hdmi->audio))
1849 platform_device_unregister(hdmi->audio);
1851 /* Disable all interrupts */
1852 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1854 hdmi->connector.funcs->destroy(&hdmi->connector);
1855 hdmi->encoder->funcs->destroy(hdmi->encoder);
1857 clk_disable_unprepare(hdmi->iahb_clk);
1858 clk_disable_unprepare(hdmi->isfr_clk);
1859 i2c_put_adapter(hdmi->ddc);
1861 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
1863 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1864 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1865 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
1866 MODULE_DESCRIPTION("DW HDMI transmitter driver");
1867 MODULE_LICENSE("GPL");
1868 MODULE_ALIAS("platform:dw-hdmi");