2 * Samsung SoC MIPI DSI Master driver.
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd
6 * Contacts: Tomasz Figa <t.figa@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <drm/drm_crtc_helper.h>
15 #include <drm/drm_mipi_dsi.h>
16 #include <drm/drm_panel.h>
17 #include <drm/drm_atomic_helper.h>
19 #include <linux/clk.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/irq.h>
22 #include <linux/of_device.h>
23 #include <linux/of_gpio.h>
24 #include <linux/phy/phy.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/component.h>
28 #include <video/mipi_display.h>
29 #include <video/videomode.h>
31 #include "exynos_drm_crtc.h"
32 #include "exynos_drm_drv.h"
34 /* returns true iff both arguments logically differs */
35 #define NEQV(a, b) (!(a) ^ !(b))
37 #define DSIM_STATUS_REG 0x0 /* Status register */
38 #define DSIM_SWRST_REG 0x4 /* Software reset register */
39 #define DSIM_CLKCTRL_REG 0x8 /* Clock control register */
40 #define DSIM_TIMEOUT_REG 0xc /* Time out register */
41 #define DSIM_CONFIG_REG 0x10 /* Configuration register */
42 #define DSIM_ESCMODE_REG 0x14 /* Escape mode register */
44 /* Main display image resolution register */
45 #define DSIM_MDRESOL_REG 0x18
46 #define DSIM_MVPORCH_REG 0x1c /* Main display Vporch register */
47 #define DSIM_MHPORCH_REG 0x20 /* Main display Hporch register */
48 #define DSIM_MSYNC_REG 0x24 /* Main display sync area register */
50 /* Sub display image resolution register */
51 #define DSIM_SDRESOL_REG 0x28
52 #define DSIM_INTSRC_REG 0x2c /* Interrupt source register */
53 #define DSIM_INTMSK_REG 0x30 /* Interrupt mask register */
54 #define DSIM_PKTHDR_REG 0x34 /* Packet Header FIFO register */
55 #define DSIM_PAYLOAD_REG 0x38 /* Payload FIFO register */
56 #define DSIM_RXFIFO_REG 0x3c /* Read FIFO register */
57 #define DSIM_FIFOTHLD_REG 0x40 /* FIFO threshold level register */
58 #define DSIM_FIFOCTRL_REG 0x44 /* FIFO status and control register */
60 /* FIFO memory AC characteristic register */
61 #define DSIM_PLLCTRL_REG 0x4c /* PLL control register */
62 #define DSIM_PHYACCHR_REG 0x54 /* D-PHY AC characteristic register */
63 #define DSIM_PHYACCHR1_REG 0x58 /* D-PHY AC characteristic register1 */
64 #define DSIM_PHYCTRL_REG 0x5c
65 #define DSIM_PHYTIMING_REG 0x64
66 #define DSIM_PHYTIMING1_REG 0x68
67 #define DSIM_PHYTIMING2_REG 0x6c
70 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
71 #define DSIM_STOP_STATE_CLK (1 << 8)
72 #define DSIM_TX_READY_HS_CLK (1 << 10)
73 #define DSIM_PLL_STABLE (1 << 31)
76 #define DSIM_FUNCRST (1 << 16)
77 #define DSIM_SWRST (1 << 0)
80 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0)
81 #define DSIM_BTA_TIMEOUT(x) ((x) << 16)
84 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
85 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
86 #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19)
87 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
88 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
89 #define DSIM_BYTE_CLKEN (1 << 24)
90 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
91 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
92 #define DSIM_PLL_BYPASS (1 << 27)
93 #define DSIM_ESC_CLKEN (1 << 28)
94 #define DSIM_TX_REQUEST_HSCLK (1 << 31)
97 #define DSIM_LANE_EN_CLK (1 << 0)
98 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1)
99 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5)
100 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8)
101 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12)
102 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12)
103 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12)
104 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12)
105 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12)
106 #define DSIM_SUB_VC (((x) & 0x3) << 16)
107 #define DSIM_MAIN_VC (((x) & 0x3) << 18)
108 #define DSIM_HSA_MODE (1 << 20)
109 #define DSIM_HBP_MODE (1 << 21)
110 #define DSIM_HFP_MODE (1 << 22)
111 #define DSIM_HSE_MODE (1 << 23)
112 #define DSIM_AUTO_MODE (1 << 24)
113 #define DSIM_VIDEO_MODE (1 << 25)
114 #define DSIM_BURST_MODE (1 << 26)
115 #define DSIM_SYNC_INFORM (1 << 27)
116 #define DSIM_EOT_DISABLE (1 << 28)
117 #define DSIM_MFLUSH_VS (1 << 29)
118 /* This flag is valid only for exynos3250/3472/4415/5260/5430 */
119 #define DSIM_CLKLANE_STOP (1 << 30)
122 #define DSIM_TX_TRIGGER_RST (1 << 4)
123 #define DSIM_TX_LPDT_LP (1 << 6)
124 #define DSIM_CMD_LPDT_LP (1 << 7)
125 #define DSIM_FORCE_BTA (1 << 16)
126 #define DSIM_FORCE_STOP_STATE (1 << 20)
127 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21)
128 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21)
131 #define DSIM_MAIN_STAND_BY (1 << 31)
132 #define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16)
133 #define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0)
136 #define DSIM_CMD_ALLOW(x) ((x) << 28)
137 #define DSIM_STABLE_VFP(x) ((x) << 16)
138 #define DSIM_MAIN_VBP(x) ((x) << 0)
139 #define DSIM_CMD_ALLOW_MASK (0xf << 28)
140 #define DSIM_STABLE_VFP_MASK (0x7ff << 16)
141 #define DSIM_MAIN_VBP_MASK (0x7ff << 0)
144 #define DSIM_MAIN_HFP(x) ((x) << 16)
145 #define DSIM_MAIN_HBP(x) ((x) << 0)
146 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
147 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
150 #define DSIM_MAIN_VSA(x) ((x) << 22)
151 #define DSIM_MAIN_HSA(x) ((x) << 0)
152 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
153 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
156 #define DSIM_SUB_STANDY(x) ((x) << 31)
157 #define DSIM_SUB_VRESOL(x) ((x) << 16)
158 #define DSIM_SUB_HRESOL(x) ((x) << 0)
159 #define DSIM_SUB_STANDY_MASK ((0x1) << 31)
160 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
161 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
164 #define DSIM_INT_PLL_STABLE (1 << 31)
165 #define DSIM_INT_SW_RST_RELEASE (1 << 30)
166 #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29)
167 #define DSIM_INT_BTA (1 << 25)
168 #define DSIM_INT_FRAME_DONE (1 << 24)
169 #define DSIM_INT_RX_TIMEOUT (1 << 21)
170 #define DSIM_INT_BTA_TIMEOUT (1 << 20)
171 #define DSIM_INT_RX_DONE (1 << 18)
172 #define DSIM_INT_RX_TE (1 << 17)
173 #define DSIM_INT_RX_ACK (1 << 16)
174 #define DSIM_INT_RX_ECC_ERR (1 << 15)
175 #define DSIM_INT_RX_CRC_ERR (1 << 14)
178 #define DSIM_RX_DATA_FULL (1 << 25)
179 #define DSIM_RX_DATA_EMPTY (1 << 24)
180 #define DSIM_SFR_HEADER_FULL (1 << 23)
181 #define DSIM_SFR_HEADER_EMPTY (1 << 22)
182 #define DSIM_SFR_PAYLOAD_FULL (1 << 21)
183 #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20)
184 #define DSIM_I80_HEADER_FULL (1 << 19)
185 #define DSIM_I80_HEADER_EMPTY (1 << 18)
186 #define DSIM_I80_PAYLOAD_FULL (1 << 17)
187 #define DSIM_I80_PAYLOAD_EMPTY (1 << 16)
188 #define DSIM_SD_HEADER_FULL (1 << 15)
189 #define DSIM_SD_HEADER_EMPTY (1 << 14)
190 #define DSIM_SD_PAYLOAD_FULL (1 << 13)
191 #define DSIM_SD_PAYLOAD_EMPTY (1 << 12)
192 #define DSIM_MD_HEADER_FULL (1 << 11)
193 #define DSIM_MD_HEADER_EMPTY (1 << 10)
194 #define DSIM_MD_PAYLOAD_FULL (1 << 9)
195 #define DSIM_MD_PAYLOAD_EMPTY (1 << 8)
196 #define DSIM_RX_FIFO (1 << 4)
197 #define DSIM_SFR_FIFO (1 << 3)
198 #define DSIM_I80_FIFO (1 << 2)
199 #define DSIM_SD_FIFO (1 << 1)
200 #define DSIM_MD_FIFO (1 << 0)
203 #define DSIM_AFC_EN (1 << 14)
204 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
207 #define DSIM_FREQ_BAND(x) ((x) << 24)
208 #define DSIM_PLL_EN (1 << 23)
209 #define DSIM_PLL_P(x) ((x) << 13)
210 #define DSIM_PLL_M(x) ((x) << 4)
211 #define DSIM_PLL_S(x) ((x) << 1)
214 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0)
217 #define DSIM_PHYTIMING_LPX(x) ((x) << 8)
218 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
220 /* DSIM_PHYTIMING1 */
221 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
222 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16)
223 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8)
224 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
226 /* DSIM_PHYTIMING2 */
227 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
228 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
229 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0)
231 #define DSI_MAX_BUS_WIDTH 4
232 #define DSI_NUM_VIRTUAL_CHANNELS 4
233 #define DSI_TX_FIFO_SIZE 2048
234 #define DSI_RX_FIFO_SIZE 256
235 #define DSI_XFER_TIMEOUT_MS 100
236 #define DSI_RX_FIFO_EMPTY 0x30800002
238 enum exynos_dsi_transfer_type {
243 struct exynos_dsi_transfer {
244 struct list_head list;
245 struct completion completed;
251 const u8 *tx_payload;
260 #define DSIM_STATE_ENABLED BIT(0)
261 #define DSIM_STATE_INITIALIZED BIT(1)
262 #define DSIM_STATE_CMD_LPM BIT(2)
264 struct exynos_dsi_driver_data {
265 unsigned int plltmr_reg;
267 unsigned int has_freqband:1;
268 unsigned int has_clklane_stop:1;
272 struct exynos_drm_display display;
273 struct mipi_dsi_host dsi_host;
274 struct drm_connector connector;
275 struct device_node *panel_node;
276 struct drm_panel *panel;
279 void __iomem *reg_base;
283 struct regulator_bulk_data supplies[2];
296 struct drm_property *brightness;
297 struct completion completed;
299 spinlock_t transfer_lock; /* protects transfer_list */
300 struct list_head transfer_list;
302 struct exynos_dsi_driver_data *driver_data;
305 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
306 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
308 static inline struct exynos_dsi *display_to_dsi(struct exynos_drm_display *d)
310 return container_of(d, struct exynos_dsi, display);
313 static struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
316 .has_clklane_stop = 1,
319 static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
322 .has_clklane_stop = 1,
325 static struct exynos_dsi_driver_data exynos4415_dsi_driver_data = {
327 .has_clklane_stop = 1,
330 static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
334 static struct of_device_id exynos_dsi_of_match[] = {
335 { .compatible = "samsung,exynos3250-mipi-dsi",
336 .data = &exynos3_dsi_driver_data },
337 { .compatible = "samsung,exynos4210-mipi-dsi",
338 .data = &exynos4_dsi_driver_data },
339 { .compatible = "samsung,exynos4415-mipi-dsi",
340 .data = &exynos4415_dsi_driver_data },
341 { .compatible = "samsung,exynos5410-mipi-dsi",
342 .data = &exynos5_dsi_driver_data },
346 static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
347 struct platform_device *pdev)
349 const struct of_device_id *of_id =
350 of_match_device(exynos_dsi_of_match, &pdev->dev);
352 return (struct exynos_dsi_driver_data *)of_id->data;
355 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
357 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
360 dev_err(dsi->dev, "timeout waiting for reset\n");
363 static void exynos_dsi_reset(struct exynos_dsi *dsi)
365 reinit_completion(&dsi->completed);
366 writel(DSIM_SWRST, dsi->reg_base + DSIM_SWRST_REG);
370 #define MHZ (1000*1000)
373 static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
374 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
376 unsigned long best_freq = 0;
377 u32 min_delta = 0xffffffff;
379 u8 _p, uninitialized_var(best_p);
380 u16 _m, uninitialized_var(best_m);
381 u8 _s, uninitialized_var(best_s);
383 p_min = DIV_ROUND_UP(fin, (12 * MHZ));
384 p_max = fin / (6 * MHZ);
386 for (_p = p_min; _p <= p_max; ++_p) {
387 for (_s = 0; _s <= 5; ++_s) {
391 tmp = (u64)fout * (_p << _s);
394 if (_m < 41 || _m > 125)
399 if (tmp < 500 * MHZ || tmp > 1000 * MHZ)
403 do_div(tmp, _p << _s);
405 delta = abs(fout - tmp);
406 if (delta < min_delta) {
425 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
428 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
429 unsigned long fin, fout;
435 clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate);
437 fin = clk_get_rate(dsi->pll_clk);
439 dev_err(dsi->dev, "failed to get PLL clock frequency\n");
443 dev_dbg(dsi->dev, "PLL input frequency: %lu\n", fin);
445 fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
448 "failed to find PLL PMS for requested frequency\n");
451 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
453 writel(500, dsi->reg_base + driver_data->plltmr_reg);
455 reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
457 if (driver_data->has_freqband) {
458 static const unsigned long freq_bands[] = {
459 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
460 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
461 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
462 770 * MHZ, 870 * MHZ, 950 * MHZ,
466 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
467 if (fout < freq_bands[band])
470 dev_dbg(dsi->dev, "band %d\n", band);
472 reg |= DSIM_FREQ_BAND(band);
475 writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
479 if (timeout-- == 0) {
480 dev_err(dsi->dev, "PLL failed to stabilize\n");
483 reg = readl(dsi->reg_base + DSIM_STATUS_REG);
484 } while ((reg & DSIM_PLL_STABLE) == 0);
489 static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
491 unsigned long hs_clk, byte_clk, esc_clk;
492 unsigned long esc_div;
495 hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
497 dev_err(dsi->dev, "failed to configure DSI PLL\n");
501 byte_clk = hs_clk / 8;
502 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
503 esc_clk = byte_clk / esc_div;
505 if (esc_clk > 20 * MHZ) {
507 esc_clk = byte_clk / esc_div;
510 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
511 hs_clk, byte_clk, esc_clk);
513 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
514 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
515 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
516 | DSIM_BYTE_CLK_SRC_MASK);
517 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
518 | DSIM_ESC_PRESCALER(esc_div)
519 | DSIM_LANE_ESC_CLK_EN_CLK
520 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
521 | DSIM_BYTE_CLK_SRC(0)
522 | DSIM_TX_REQUEST_HSCLK;
523 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
528 static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
530 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
533 if (driver_data->has_freqband)
536 /* B D-PHY: D-PHY Master & Slave Analog Block control */
537 reg = DSIM_PHYCTRL_ULPS_EXIT(0x0af);
538 writel(reg, dsi->reg_base + DSIM_PHYCTRL_REG);
541 * T LPX: Transmitted length of any Low-Power state period
542 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
545 reg = DSIM_PHYTIMING_LPX(0x06) | DSIM_PHYTIMING_HS_EXIT(0x0b);
546 writel(reg, dsi->reg_base + DSIM_PHYTIMING_REG);
549 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
550 * Line state immediately before the HS-0 Line state starting the
552 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
553 * transmitting the Clock.
554 * T CLK_POST: Time that the transmitter continues to send HS clock
555 * after the last associated Data Lane has transitioned to LP Mode
556 * Interval is defined as the period from the end of T HS-TRAIL to
557 * the beginning of T CLK-TRAIL
558 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
559 * the last payload clock bit of a HS transmission burst
561 reg = DSIM_PHYTIMING1_CLK_PREPARE(0x07) |
562 DSIM_PHYTIMING1_CLK_ZERO(0x27) |
563 DSIM_PHYTIMING1_CLK_POST(0x0d) |
564 DSIM_PHYTIMING1_CLK_TRAIL(0x08);
565 writel(reg, dsi->reg_base + DSIM_PHYTIMING1_REG);
568 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
569 * Line state immediately before the HS-0 Line state starting the
571 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
572 * transmitting the Sync sequence.
573 * T HS-TRAIL: Time that the transmitter drives the flipped differential
574 * state after last payload data bit of a HS transmission burst
576 reg = DSIM_PHYTIMING2_HS_PREPARE(0x09) | DSIM_PHYTIMING2_HS_ZERO(0x0d) |
577 DSIM_PHYTIMING2_HS_TRAIL(0x0b);
578 writel(reg, dsi->reg_base + DSIM_PHYTIMING2_REG);
581 static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
585 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
586 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
587 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
588 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
590 reg = readl(dsi->reg_base + DSIM_PLLCTRL_REG);
592 writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
595 static int exynos_dsi_init_link(struct exynos_dsi *dsi)
597 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
602 /* Initialize FIFO pointers */
603 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
605 writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
607 usleep_range(9000, 11000);
610 writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
612 usleep_range(9000, 11000);
614 /* DSI configuration */
618 * The first bit of mode_flags specifies display configuration.
619 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
620 * mode, otherwise it will support command mode.
622 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
623 reg |= DSIM_VIDEO_MODE;
626 * The user manual describes that following bits are ignored in
629 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
630 reg |= DSIM_MFLUSH_VS;
631 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
632 reg |= DSIM_SYNC_INFORM;
633 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
634 reg |= DSIM_BURST_MODE;
635 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
636 reg |= DSIM_AUTO_MODE;
637 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
638 reg |= DSIM_HSE_MODE;
639 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
640 reg |= DSIM_HFP_MODE;
641 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
642 reg |= DSIM_HBP_MODE;
643 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
644 reg |= DSIM_HSA_MODE;
647 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
648 reg |= DSIM_EOT_DISABLE;
650 switch (dsi->format) {
651 case MIPI_DSI_FMT_RGB888:
652 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
654 case MIPI_DSI_FMT_RGB666:
655 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
657 case MIPI_DSI_FMT_RGB666_PACKED:
658 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
660 case MIPI_DSI_FMT_RGB565:
661 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
664 dev_err(dsi->dev, "invalid pixel format\n");
668 reg |= DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1);
670 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
672 reg |= DSIM_LANE_EN_CLK;
673 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
675 lanes_mask = BIT(dsi->lanes) - 1;
676 reg |= DSIM_LANE_EN(lanes_mask);
677 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
680 * Use non-continuous clock mode if the periparal wants and
681 * host controller supports
683 * In non-continous clock mode, host controller will turn off
684 * the HS clock between high-speed transmissions to reduce
687 if (driver_data->has_clklane_stop &&
688 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
689 reg |= DSIM_CLKLANE_STOP;
690 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
693 /* Check clock and data lane state are stop state */
696 if (timeout-- == 0) {
697 dev_err(dsi->dev, "waiting for bus lanes timed out\n");
701 reg = readl(dsi->reg_base + DSIM_STATUS_REG);
702 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
703 != DSIM_STOP_STATE_DAT(lanes_mask))
705 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
707 reg = readl(dsi->reg_base + DSIM_ESCMODE_REG);
708 reg &= ~DSIM_STOP_STATE_CNT_MASK;
709 reg |= DSIM_STOP_STATE_CNT(0xf);
710 writel(reg, dsi->reg_base + DSIM_ESCMODE_REG);
712 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
713 writel(reg, dsi->reg_base + DSIM_TIMEOUT_REG);
718 static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
720 struct videomode *vm = &dsi->vm;
723 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
724 reg = DSIM_CMD_ALLOW(0xf)
725 | DSIM_STABLE_VFP(vm->vfront_porch)
726 | DSIM_MAIN_VBP(vm->vback_porch);
727 writel(reg, dsi->reg_base + DSIM_MVPORCH_REG);
729 reg = DSIM_MAIN_HFP(vm->hfront_porch)
730 | DSIM_MAIN_HBP(vm->hback_porch);
731 writel(reg, dsi->reg_base + DSIM_MHPORCH_REG);
733 reg = DSIM_MAIN_VSA(vm->vsync_len)
734 | DSIM_MAIN_HSA(vm->hsync_len);
735 writel(reg, dsi->reg_base + DSIM_MSYNC_REG);
738 reg = DSIM_MAIN_HRESOL(vm->hactive) | DSIM_MAIN_VRESOL(vm->vactive);
739 writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
741 dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive);
744 static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
748 reg = readl(dsi->reg_base + DSIM_MDRESOL_REG);
750 reg |= DSIM_MAIN_STAND_BY;
752 reg &= ~DSIM_MAIN_STAND_BY;
753 writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
756 static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
761 u32 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
763 if (!(reg & DSIM_SFR_HEADER_FULL))
767 usleep_range(950, 1050);
773 static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
775 u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
778 v |= DSIM_CMD_LPDT_LP;
780 v &= ~DSIM_CMD_LPDT_LP;
782 writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
785 static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
787 u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
790 writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
793 static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
794 struct exynos_dsi_transfer *xfer)
796 struct device *dev = dsi->dev;
797 const u8 *payload = xfer->tx_payload + xfer->tx_done;
798 u16 length = xfer->tx_len - xfer->tx_done;
799 bool first = !xfer->tx_done;
802 dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n",
803 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
805 if (length > DSI_TX_FIFO_SIZE)
806 length = DSI_TX_FIFO_SIZE;
808 xfer->tx_done += length;
811 while (length >= 4) {
812 reg = (payload[3] << 24) | (payload[2] << 16)
813 | (payload[1] << 8) | payload[0];
814 writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
822 reg |= payload[2] << 16;
825 reg |= payload[1] << 8;
829 writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
836 /* Send packet header */
840 reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id;
841 if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
842 dev_err(dev, "waiting for header FIFO timed out\n");
846 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
847 dsi->state & DSIM_STATE_CMD_LPM)) {
848 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
849 dsi->state ^= DSIM_STATE_CMD_LPM;
852 writel(reg, dsi->reg_base + DSIM_PKTHDR_REG);
854 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
855 exynos_dsi_force_bta(dsi);
858 static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
859 struct exynos_dsi_transfer *xfer)
861 u8 *payload = xfer->rx_payload + xfer->rx_done;
862 bool first = !xfer->rx_done;
863 struct device *dev = dsi->dev;
868 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
870 switch (reg & 0x3f) {
871 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
872 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
873 if (xfer->rx_len >= 2) {
874 payload[1] = reg >> 16;
878 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
879 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
880 payload[0] = reg >> 8;
882 xfer->rx_len = xfer->rx_done;
885 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
886 dev_err(dev, "DSI Error Report: 0x%04x\n",
887 (reg >> 8) & 0xffff);
892 length = (reg >> 8) & 0xffff;
893 if (length > xfer->rx_len) {
895 "response too long (%u > %u bytes), stripping\n",
896 xfer->rx_len, length);
897 length = xfer->rx_len;
898 } else if (length < xfer->rx_len)
899 xfer->rx_len = length;
902 length = xfer->rx_len - xfer->rx_done;
903 xfer->rx_done += length;
905 /* Receive payload */
906 while (length >= 4) {
907 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
908 payload[0] = (reg >> 0) & 0xff;
909 payload[1] = (reg >> 8) & 0xff;
910 payload[2] = (reg >> 16) & 0xff;
911 payload[3] = (reg >> 24) & 0xff;
917 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
920 payload[2] = (reg >> 16) & 0xff;
923 payload[1] = (reg >> 8) & 0xff;
926 payload[0] = reg & 0xff;
930 if (xfer->rx_done == xfer->rx_len)
934 length = DSI_RX_FIFO_SIZE / 4;
936 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
937 if (reg == DSI_RX_FIFO_EMPTY)
942 static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
945 struct exynos_dsi_transfer *xfer;
949 spin_lock_irqsave(&dsi->transfer_lock, flags);
951 if (list_empty(&dsi->transfer_list)) {
952 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
956 xfer = list_first_entry(&dsi->transfer_list,
957 struct exynos_dsi_transfer, list);
959 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
961 if (xfer->tx_len && xfer->tx_done == xfer->tx_len)
965 exynos_dsi_send_to_fifo(dsi, xfer);
967 if (xfer->tx_len || xfer->rx_len)
971 complete(&xfer->completed);
973 spin_lock_irqsave(&dsi->transfer_lock, flags);
975 list_del_init(&xfer->list);
976 start = !list_empty(&dsi->transfer_list);
978 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
984 static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
986 struct exynos_dsi_transfer *xfer;
990 spin_lock_irqsave(&dsi->transfer_lock, flags);
992 if (list_empty(&dsi->transfer_list)) {
993 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
997 xfer = list_first_entry(&dsi->transfer_list,
998 struct exynos_dsi_transfer, list);
1000 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1003 "> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n",
1004 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
1006 if (xfer->tx_done != xfer->tx_len)
1009 if (xfer->rx_done != xfer->rx_len)
1010 exynos_dsi_read_from_fifo(dsi, xfer);
1012 if (xfer->rx_done != xfer->rx_len)
1015 spin_lock_irqsave(&dsi->transfer_lock, flags);
1017 list_del_init(&xfer->list);
1018 start = !list_empty(&dsi->transfer_list);
1020 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1024 complete(&xfer->completed);
1029 static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
1030 struct exynos_dsi_transfer *xfer)
1032 unsigned long flags;
1035 spin_lock_irqsave(&dsi->transfer_lock, flags);
1037 if (!list_empty(&dsi->transfer_list) &&
1038 xfer == list_first_entry(&dsi->transfer_list,
1039 struct exynos_dsi_transfer, list)) {
1040 list_del_init(&xfer->list);
1041 start = !list_empty(&dsi->transfer_list);
1042 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1044 exynos_dsi_transfer_start(dsi);
1048 list_del_init(&xfer->list);
1050 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1053 static int exynos_dsi_transfer(struct exynos_dsi *dsi,
1054 struct exynos_dsi_transfer *xfer)
1056 unsigned long flags;
1061 xfer->result = -ETIMEDOUT;
1062 init_completion(&xfer->completed);
1064 spin_lock_irqsave(&dsi->transfer_lock, flags);
1066 stopped = list_empty(&dsi->transfer_list);
1067 list_add_tail(&xfer->list, &dsi->transfer_list);
1069 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1072 exynos_dsi_transfer_start(dsi);
1074 wait_for_completion_timeout(&xfer->completed,
1075 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1076 if (xfer->result == -ETIMEDOUT) {
1077 exynos_dsi_remove_transfer(dsi, xfer);
1078 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data,
1079 xfer->tx_len, xfer->tx_payload);
1083 /* Also covers hardware timeout condition */
1084 return xfer->result;
1087 static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
1089 struct exynos_dsi *dsi = dev_id;
1092 status = readl(dsi->reg_base + DSIM_INTSRC_REG);
1094 static unsigned long int j;
1095 if (printk_timed_ratelimit(&j, 500))
1096 dev_warn(dsi->dev, "spurious interrupt\n");
1099 writel(status, dsi->reg_base + DSIM_INTSRC_REG);
1101 if (status & DSIM_INT_SW_RST_RELEASE) {
1102 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY);
1103 writel(mask, dsi->reg_base + DSIM_INTMSK_REG);
1104 complete(&dsi->completed);
1108 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY)))
1111 if (exynos_dsi_transfer_finish(dsi))
1112 exynos_dsi_transfer_start(dsi);
1117 static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
1119 struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
1120 struct drm_encoder *encoder = dsi->display.encoder;
1122 if (dsi->state & DSIM_STATE_ENABLED)
1123 exynos_drm_crtc_te_handler(encoder->crtc);
1128 static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
1130 enable_irq(dsi->irq);
1132 if (gpio_is_valid(dsi->te_gpio))
1133 enable_irq(gpio_to_irq(dsi->te_gpio));
1136 static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
1138 if (gpio_is_valid(dsi->te_gpio))
1139 disable_irq(gpio_to_irq(dsi->te_gpio));
1141 disable_irq(dsi->irq);
1144 static int exynos_dsi_init(struct exynos_dsi *dsi)
1146 exynos_dsi_reset(dsi);
1147 exynos_dsi_enable_irq(dsi);
1148 exynos_dsi_enable_clock(dsi);
1149 exynos_dsi_wait_for_reset(dsi);
1150 exynos_dsi_set_phy_ctrl(dsi);
1151 exynos_dsi_init_link(dsi);
1156 static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
1161 dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0);
1162 if (!gpio_is_valid(dsi->te_gpio)) {
1163 dev_err(dsi->dev, "no te-gpios specified\n");
1168 ret = gpio_request_one(dsi->te_gpio, GPIOF_IN, "te_gpio");
1170 dev_err(dsi->dev, "gpio request failed with %d\n", ret);
1174 te_gpio_irq = gpio_to_irq(dsi->te_gpio);
1176 irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN);
1177 ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
1178 IRQF_TRIGGER_RISING, "TE", dsi);
1180 dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1181 gpio_free(dsi->te_gpio);
1189 static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
1191 if (gpio_is_valid(dsi->te_gpio)) {
1192 free_irq(gpio_to_irq(dsi->te_gpio), dsi);
1193 gpio_free(dsi->te_gpio);
1194 dsi->te_gpio = -ENOENT;
1198 static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
1199 struct mipi_dsi_device *device)
1201 struct exynos_dsi *dsi = host_to_dsi(host);
1203 dsi->lanes = device->lanes;
1204 dsi->format = device->format;
1205 dsi->mode_flags = device->mode_flags;
1206 dsi->panel_node = device->dev.of_node;
1209 * This is a temporary solution and should be made by more generic way.
1211 * If attached panel device is for command mode one, dsi should register
1212 * TE interrupt handler.
1214 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1215 int ret = exynos_dsi_register_te_irq(dsi);
1221 if (dsi->connector.dev)
1222 drm_helper_hpd_irq_event(dsi->connector.dev);
1227 static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
1228 struct mipi_dsi_device *device)
1230 struct exynos_dsi *dsi = host_to_dsi(host);
1232 exynos_dsi_unregister_te_irq(dsi);
1234 dsi->panel_node = NULL;
1236 if (dsi->connector.dev)
1237 drm_helper_hpd_irq_event(dsi->connector.dev);
1242 /* distinguish between short and long DSI packet types */
1243 static bool exynos_dsi_is_short_dsi_type(u8 type)
1245 return (type & 0x0f) <= 8;
1248 static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
1249 const struct mipi_dsi_msg *msg)
1251 struct exynos_dsi *dsi = host_to_dsi(host);
1252 struct exynos_dsi_transfer xfer;
1255 if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1256 ret = exynos_dsi_init(dsi);
1259 dsi->state |= DSIM_STATE_INITIALIZED;
1262 if (msg->tx_len == 0)
1265 xfer.data_id = msg->type | (msg->channel << 6);
1267 if (exynos_dsi_is_short_dsi_type(msg->type)) {
1268 const char *tx_buf = msg->tx_buf;
1270 if (msg->tx_len > 2)
1273 xfer.data[0] = tx_buf[0];
1274 xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0;
1276 xfer.tx_len = msg->tx_len;
1277 xfer.data[0] = msg->tx_len & 0xff;
1278 xfer.data[1] = msg->tx_len >> 8;
1279 xfer.tx_payload = msg->tx_buf;
1282 xfer.rx_len = msg->rx_len;
1283 xfer.rx_payload = msg->rx_buf;
1284 xfer.flags = msg->flags;
1286 ret = exynos_dsi_transfer(dsi, &xfer);
1287 return (ret < 0) ? ret : xfer.rx_done;
1290 static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1291 .attach = exynos_dsi_host_attach,
1292 .detach = exynos_dsi_host_detach,
1293 .transfer = exynos_dsi_host_transfer,
1296 static int exynos_dsi_poweron(struct exynos_dsi *dsi)
1300 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1302 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1306 ret = clk_prepare_enable(dsi->bus_clk);
1308 dev_err(dsi->dev, "cannot enable bus clock %d\n", ret);
1312 ret = clk_prepare_enable(dsi->pll_clk);
1314 dev_err(dsi->dev, "cannot enable pll clock %d\n", ret);
1318 ret = phy_power_on(dsi->phy);
1320 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1327 clk_disable_unprepare(dsi->pll_clk);
1329 clk_disable_unprepare(dsi->bus_clk);
1331 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1336 static void exynos_dsi_poweroff(struct exynos_dsi *dsi)
1340 usleep_range(10000, 20000);
1342 if (dsi->state & DSIM_STATE_INITIALIZED) {
1343 dsi->state &= ~DSIM_STATE_INITIALIZED;
1345 exynos_dsi_disable_clock(dsi);
1347 exynos_dsi_disable_irq(dsi);
1350 dsi->state &= ~DSIM_STATE_CMD_LPM;
1352 phy_power_off(dsi->phy);
1354 clk_disable_unprepare(dsi->pll_clk);
1355 clk_disable_unprepare(dsi->bus_clk);
1357 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1359 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1362 static int exynos_dsi_enable(struct exynos_dsi *dsi)
1366 if (dsi->state & DSIM_STATE_ENABLED)
1369 ret = exynos_dsi_poweron(dsi);
1373 ret = drm_panel_prepare(dsi->panel);
1375 exynos_dsi_poweroff(dsi);
1379 exynos_dsi_set_display_mode(dsi);
1380 exynos_dsi_set_display_enable(dsi, true);
1382 dsi->state |= DSIM_STATE_ENABLED;
1384 ret = drm_panel_enable(dsi->panel);
1386 dsi->state &= ~DSIM_STATE_ENABLED;
1387 exynos_dsi_set_display_enable(dsi, false);
1388 drm_panel_unprepare(dsi->panel);
1389 exynos_dsi_poweroff(dsi);
1396 static void exynos_dsi_disable(struct exynos_dsi *dsi)
1398 if (!(dsi->state & DSIM_STATE_ENABLED))
1401 drm_panel_disable(dsi->panel);
1402 exynos_dsi_set_display_enable(dsi, false);
1403 drm_panel_unprepare(dsi->panel);
1404 exynos_dsi_poweroff(dsi);
1406 dsi->state &= ~DSIM_STATE_ENABLED;
1409 static void exynos_dsi_dpms(struct exynos_drm_display *display, int mode)
1411 struct exynos_dsi *dsi = display_to_dsi(display);
1415 case DRM_MODE_DPMS_ON:
1416 exynos_dsi_enable(dsi);
1418 case DRM_MODE_DPMS_STANDBY:
1419 case DRM_MODE_DPMS_SUSPEND:
1420 case DRM_MODE_DPMS_OFF:
1421 exynos_dsi_disable(dsi);
1429 static enum drm_connector_status
1430 exynos_dsi_detect(struct drm_connector *connector, bool force)
1432 struct exynos_dsi *dsi = connector_to_dsi(connector);
1435 dsi->panel = of_drm_find_panel(dsi->panel_node);
1437 drm_panel_attach(dsi->panel, &dsi->connector);
1438 } else if (!dsi->panel_node) {
1439 struct exynos_drm_display *display;
1441 display = platform_get_drvdata(to_platform_device(dsi->dev));
1442 exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF);
1443 drm_panel_detach(dsi->panel);
1448 return connector_status_connected;
1450 return connector_status_disconnected;
1453 static void exynos_dsi_connector_destroy(struct drm_connector *connector)
1455 drm_connector_unregister(connector);
1456 drm_connector_cleanup(connector);
1457 connector->dev = NULL;
1460 static struct drm_connector_funcs exynos_dsi_connector_funcs = {
1461 .dpms = drm_atomic_helper_connector_dpms,
1462 .detect = exynos_dsi_detect,
1463 .fill_modes = drm_helper_probe_single_connector_modes,
1464 .destroy = exynos_dsi_connector_destroy,
1465 .reset = drm_atomic_helper_connector_reset,
1466 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1467 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1470 static int exynos_dsi_get_modes(struct drm_connector *connector)
1472 struct exynos_dsi *dsi = connector_to_dsi(connector);
1475 return dsi->panel->funcs->get_modes(dsi->panel);
1480 static struct drm_encoder *
1481 exynos_dsi_best_encoder(struct drm_connector *connector)
1483 struct exynos_dsi *dsi = connector_to_dsi(connector);
1485 return dsi->display.encoder;
1488 static struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
1489 .get_modes = exynos_dsi_get_modes,
1490 .best_encoder = exynos_dsi_best_encoder,
1493 static int exynos_dsi_create_connector(struct exynos_drm_display *display,
1494 struct drm_encoder *encoder)
1496 struct exynos_dsi *dsi = display_to_dsi(display);
1497 struct drm_connector *connector = &dsi->connector;
1500 connector->polled = DRM_CONNECTOR_POLL_HPD;
1502 ret = drm_connector_init(encoder->dev, connector,
1503 &exynos_dsi_connector_funcs,
1504 DRM_MODE_CONNECTOR_DSI);
1506 DRM_ERROR("Failed to initialize connector with drm\n");
1510 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1511 drm_connector_register(connector);
1512 drm_mode_connector_attach_encoder(connector, encoder);
1517 static void exynos_dsi_mode_set(struct exynos_drm_display *display,
1518 struct drm_display_mode *mode)
1520 struct exynos_dsi *dsi = display_to_dsi(display);
1521 struct videomode *vm = &dsi->vm;
1523 vm->hactive = mode->hdisplay;
1524 vm->vactive = mode->vdisplay;
1525 vm->vfront_porch = mode->vsync_start - mode->vdisplay;
1526 vm->vback_porch = mode->vtotal - mode->vsync_end;
1527 vm->vsync_len = mode->vsync_end - mode->vsync_start;
1528 vm->hfront_porch = mode->hsync_start - mode->hdisplay;
1529 vm->hback_porch = mode->htotal - mode->hsync_end;
1530 vm->hsync_len = mode->hsync_end - mode->hsync_start;
1533 static struct exynos_drm_display_ops exynos_dsi_display_ops = {
1534 .create_connector = exynos_dsi_create_connector,
1535 .mode_set = exynos_dsi_mode_set,
1536 .dpms = exynos_dsi_dpms
1539 MODULE_DEVICE_TABLE(of, exynos_dsi_of_match);
1541 /* of_* functions will be removed after merge of of_graph patches */
1542 static struct device_node *
1543 of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg)
1545 struct device_node *np;
1547 for_each_child_of_node(parent, np) {
1550 if (!np->name || of_node_cmp(np->name, name))
1553 if (of_property_read_u32(np, "reg", &r) < 0)
1563 static struct device_node *of_graph_get_port_by_reg(struct device_node *parent,
1566 struct device_node *ports, *port;
1568 ports = of_get_child_by_name(parent, "ports");
1572 port = of_get_child_by_name_reg(parent, "port", reg);
1579 static struct device_node *
1580 of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg)
1582 return of_get_child_by_name_reg(port, "endpoint", reg);
1585 static int exynos_dsi_of_read_u32(const struct device_node *np,
1586 const char *propname, u32 *out_value)
1588 int ret = of_property_read_u32(np, propname, out_value);
1591 pr_err("%s: failed to get '%s' property\n", np->full_name,
1602 static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
1604 struct device *dev = dsi->dev;
1605 struct device_node *node = dev->of_node;
1606 struct device_node *port, *ep;
1609 ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
1610 &dsi->pll_clk_rate);
1614 port = of_graph_get_port_by_reg(node, DSI_PORT_OUT);
1616 dev_err(dev, "no output port specified\n");
1620 ep = of_graph_get_endpoint_by_reg(port, 0);
1623 dev_err(dev, "no endpoint specified in output port\n");
1627 ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency",
1628 &dsi->burst_clk_rate);
1632 ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency",
1633 &dsi->esc_clk_rate);
1641 static int exynos_dsi_bind(struct device *dev, struct device *master,
1644 struct exynos_drm_display *display = dev_get_drvdata(dev);
1645 struct exynos_dsi *dsi = display_to_dsi(display);
1646 struct drm_device *drm_dev = data;
1649 ret = exynos_drm_create_enc_conn(drm_dev, display);
1651 DRM_ERROR("Encoder create [%d] failed with %d\n",
1652 display->type, ret);
1656 return mipi_dsi_host_register(&dsi->dsi_host);
1659 static void exynos_dsi_unbind(struct device *dev, struct device *master,
1662 struct exynos_drm_display *display = dev_get_drvdata(dev);
1663 struct exynos_dsi *dsi = display_to_dsi(display);
1665 exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF);
1667 mipi_dsi_host_unregister(&dsi->dsi_host);
1670 static const struct component_ops exynos_dsi_component_ops = {
1671 .bind = exynos_dsi_bind,
1672 .unbind = exynos_dsi_unbind,
1675 static int exynos_dsi_probe(struct platform_device *pdev)
1677 struct device *dev = &pdev->dev;
1678 struct resource *res;
1679 struct exynos_dsi *dsi;
1682 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1686 dsi->display.type = EXYNOS_DISPLAY_TYPE_LCD;
1687 dsi->display.ops = &exynos_dsi_display_ops;
1689 ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CONNECTOR,
1694 /* To be checked as invalid one */
1695 dsi->te_gpio = -ENOENT;
1697 init_completion(&dsi->completed);
1698 spin_lock_init(&dsi->transfer_lock);
1699 INIT_LIST_HEAD(&dsi->transfer_list);
1701 dsi->dsi_host.ops = &exynos_dsi_ops;
1702 dsi->dsi_host.dev = dev;
1705 dsi->driver_data = exynos_dsi_get_driver_data(pdev);
1707 ret = exynos_dsi_parse_dt(dsi);
1709 goto err_del_component;
1711 dsi->supplies[0].supply = "vddcore";
1712 dsi->supplies[1].supply = "vddio";
1713 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1716 dev_info(dev, "failed to get regulators: %d\n", ret);
1717 return -EPROBE_DEFER;
1720 dsi->pll_clk = devm_clk_get(dev, "pll_clk");
1721 if (IS_ERR(dsi->pll_clk)) {
1722 dev_info(dev, "failed to get dsi pll input clock\n");
1723 ret = PTR_ERR(dsi->pll_clk);
1724 goto err_del_component;
1727 dsi->bus_clk = devm_clk_get(dev, "bus_clk");
1728 if (IS_ERR(dsi->bus_clk)) {
1729 dev_info(dev, "failed to get dsi bus clock\n");
1730 ret = PTR_ERR(dsi->bus_clk);
1731 goto err_del_component;
1734 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1735 dsi->reg_base = devm_ioremap_resource(dev, res);
1736 if (IS_ERR(dsi->reg_base)) {
1737 dev_err(dev, "failed to remap io region\n");
1738 ret = PTR_ERR(dsi->reg_base);
1739 goto err_del_component;
1742 dsi->phy = devm_phy_get(dev, "dsim");
1743 if (IS_ERR(dsi->phy)) {
1744 dev_info(dev, "failed to get dsim phy\n");
1745 ret = PTR_ERR(dsi->phy);
1746 goto err_del_component;
1749 dsi->irq = platform_get_irq(pdev, 0);
1751 dev_err(dev, "failed to request dsi irq resource\n");
1753 goto err_del_component;
1756 irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN);
1757 ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1758 exynos_dsi_irq, IRQF_ONESHOT,
1759 dev_name(dev), dsi);
1761 dev_err(dev, "failed to request dsi irq\n");
1762 goto err_del_component;
1765 platform_set_drvdata(pdev, &dsi->display);
1767 ret = component_add(dev, &exynos_dsi_component_ops);
1769 goto err_del_component;
1774 exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1778 static int exynos_dsi_remove(struct platform_device *pdev)
1780 component_del(&pdev->dev, &exynos_dsi_component_ops);
1781 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1786 struct platform_driver dsi_driver = {
1787 .probe = exynos_dsi_probe,
1788 .remove = exynos_dsi_remove,
1790 .name = "exynos-dsi",
1791 .owner = THIS_MODULE,
1792 .of_match_table = exynos_dsi_of_match,
1796 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
1797 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
1798 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
1799 MODULE_LICENSE("GPL v2");